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MM54C32 MM74C32 Quad 2-Input OR Gate February 1988 MM54C32 MM74C32 Quad 2-Input OR Gate General Description Employing complementary MOS (CMOS) transistors to achieve low power and high noise margin these gates provide the basic functions used in the implementation of digital integrated circuit systems The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage This results in high noise immunity over a wide supply voltage range No DC power other than that caused by leakage current is consumed during static conditions All inputs are protected against static discharge damage Features Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility 3 0V to 15V 1 0V 0 45V VCC (typ ) fan out of 2 driving 74L Connection Diagram Dual-In-Line Package TL F 5881 - 1 Top View Order Number MM54C32 or MM74C32 C1995 National Semiconductor Corporation TL F 5881 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (Soldering 10 seconds) b 65 C to a 150 C If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range MM54C32 MM74C32 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW 3 0V to 15V 18V 260 C DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) Logical ``1'' Input Voltage VCC e 5 0V VCC e 10V VIN(0) Logical ``0'' Input Voltage VCC e 5 0V VCC e 10V VOUT(1) Logical ``1'' Output Voltage VCC e 5 0V IO e b10 mA VCC e 10V IO e b10 mA VOUT(0) Logical ``0'' Output Voltage VCC e 5 0V IO e 10 mA VCC e 10V IO e 10 mA IIN(1) IIN(0) ICC Logical ``1'' Input Current Logical ``0'' Input Current Supply Current VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V b1 0 Parameter Conditions Min Typ Max Units 35 80 15 20 45 90 05 10 0 005 b 0 005 V V V V V V V V mA mA 15 mA 10 0 05 CMOS LPTTL INTERFACE VIN(1) Logical ``1'' Input Voltage 54C VCC e 4 5V 74C VCC e 4 75V VIN(0) Logical ``0'' Input Voltage 54C VCC e 4 5V 74C VCC e 4 75V VOUT(1) Logical ``1'' Output Voltage 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA VOUT(0) Logical ``0'' Output Voltage 54C VCC e 4 5V IO e 360 mA 74C VCC e 4 75V IO e 360 mA OUTPUT DRIVE (see 54C 74C Family Characteristics Data Sheet) TA e 25 C (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC e 5 0V VOUT e 0V VCC e 10V VOUT e 0V VCC e 5 0V VOUT e VCC VCC e 10V VOUT e VCC b 1 75 b8 0 b3 3 b 15 VCC b 1 5 VCC b 1 5 08 08 24 24 04 04 V V V V V V V V mA mA mA mA 1 75 80 36 16 Note 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device operation 2 AC Electrical Characteristics Symbol tpd Parameter Propagation Delay Time to Logical ``1'' or ``0'' Input Capacitance Power Dissipation Capacitance TA e 25 C CL e 50 pF unless otherwise specified Conditions VCC e 5 0V VCC e 10V Any Input (Note 2) Per Gate (Note 3) Min Typ 80 35 5 15 Max 150 70 Units ns ns pF pF CIN CPD AC Parameters are guaranteed by DC correlated testing Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C32J or MM74C32J NS Package Number J14A 3 MM54C32 MM74C32 Quad 2-Input OR Gate Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C32N or MM74C32N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications |
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