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LH5481 LH5491
FEATURES * Fastest 64 x 8/9 Cascadable FIFO 35/25/15 MHz * Expandable in Word Width and FIFO Depth * Almost-Full/Almost-Empty and Half-Full Flags * Fully Independent Asynchronous Inputs and Outputs * LH5481 Output Enable forces Data Outputs to High-Impedance State * Pin-Compatible Replacements for Cypress CY7C408A/09A or Logic Devices L8C408/09 FIFOs * Industry Standard Pinout * Packages: 28-Pin, 300-mil DIP 28-Pin PLCC FUNCTIONAL DESCRIPTION
The LH5481 and LH5491 are high-performance, asynchronous First-In, First-Out (FIFO) memories organized 64 words deep by eight or nine bits wide. The eight-bit LH5481 has an Output Enable (OE) function, which can be used to force the eight data outputs (DO) to a high-impedance state. The LH5491 has nine data outputs. These FIFOs accept eight or nine-bit data at the Data Inputs (DI). A Shift In (SI) signal writes the DI data into the FIFO. A Shift Out (SO) signal shifts stored data to the Data Outputs (DO). The Output Ready (OR) signal indicates when valid data is present on the DO outputs. If the FIFO is full and unable to accept more DI data, Input Ready (IR) will not return HIGH, and SI pulses will be ignored. If the FIFO is empty and unable to shift data to the DO outputs, OR will not return HIGH, and SO pulses will be ignored. The Almost-Full/Almost-Empty (AFE) flag is asserted (HIGH) when the FIFO is almost-full (56 words or more) or almost- empty (eight words or less).
Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO
The Half-Full (HF) flag is asserted (HIGH) when the FIFO contains 32 words or more. Reading and writing operations may be asynchronous, allowing these FIFOs to be used as buffers between digital machines of different operating frequencies. The high speed makes these FIFOs ideal for high performance communication and controller applications.
PIN CONNECTIONS
28-PIN PDIP AFE HF IR SI DI0 DI1 VSS DI2 DI3 DI4 DI5 DI6 DI7 NC/DI8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC MR SO OR DO0 DO1 VSS DO2 DO3 DO4 DO5 DO6 DO7 OE/DO8
5481-1D
TOP VIEW
Figure 1. Pin Connections for DIP Package
28-PIN PLCC
AFE VCC MR HF IR SO SI
TOP VIEW
4 DI0 DI1 VSS DI2 DI3 DI4 DI5 5 6 7 8 9 10 11
3
2
1
28 27 26 25 24 23 22 21 20 19 OR DO0 DO1 VSS DO2 DO3 DO4
12 13 14 15 16 17 18
NC/DI8 DO6 DI6 DI7 OE/DO8 DO7 DO5
5481-2D
Figure 2. Pin Connections for PLCC Package
1
LH5481/91
64 x 8 / 64 x 9 FIFO
ALMOST-FULL/ ALMOST-EMPTY SI IR INPUT CONTROL LOGIC WRITE POINTER WRITE MULTIPLEXER HALF-FULL
AFE
HF
. . .
DATA OUT
. . .
DO0 DO7 DO8 (LH5491)
(LH5491) DI0 - DI8 (LH5481) DI0 - DI7
DATA IN
MEMORY ARRAY
READ MULTIPLEXER MR MASTER RESET READ POINTER OUTPUT CONTROL LOGIC
OE (LH5481) OR SO
5481-3
Figure 3. LH5481/91 Block Diagram
PIN DESCRIPTIONS
PIN PIN TYPE * DESCRIPTION PIN PIN TYPE * DESCRIPTION
DI0 - DI7 DO0 - DO7 DI0 - DI8 DO0 - DO8 SI SO IR OR
I O/Z I O I I O O
Data Inputs, LH5481 Data Outputs, LH5481 Data Inputs, LH5491 Data Outputs, LH5491 Shift In Shift Out Input Ready Output Ready
HF AFE MR OE VCC VSS
O O I I V V
Half-Full Flag Almost-Full / AlmostEmpty Master Reset Output Enable (LH5481 only) Positive Power Supply Ground
* I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
2
64 x 8 / 64 x 9 FIFO
LH5481/91
ABSOLUTE MAXIMUM RATINGS 1,2
PARAMETER RATING
Vcc Range Input Voltage Range DC Output Current
3
-0.5 V to 7 V -0.5 V to Vcc + 0.5 V (not to exceed 7 V) 40 mA -65oC to 150oC -0.5 V to Vcc + 0.5 V (not to exceed 7 V) > 2000 V 1.0 W
4
Storage Temperature DC Voltage Applied To Outputs In High-Z state Static Discharge Voltage
Power Dissipation (Package Limit)
NOTES: 1. All voltages are measured with respect to Vss. 2. Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the `Operating Range' of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 4. Sample tested only.
OPERATING RANGE 1
PARAMETER DESCRIPTION MIN MAX UNIT oC
TA VCC Vss VIL VIH
Temperature, Ambient Supply Voltage Ground Input Low Voltage (Logic `0') Input High Voltage (Logic `1')
2
0.0 4.5 0.0 - 0.5 2.0
70 5.5 0.0 0.8 Vcc + 0.5
V V V V
NOTES: 1. All voltages are measured with respect to Vss. 2. FIFO inputs are able to withstand a -1.5 V undershoot for less than 10 ns per cycle.
DC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range Unless Otherwise Noted)
PARAMETER DESCRIPTION TEST CONDITIONS MIN MAX UNIT
ILI ILO VOH VOL ICCQ ICC
Input Leakage Current Output Leakage Current (High-Z) Output High Voltage Output Low Voltage Power Supply Quiescent Current Power Supply Current 2
VCC = 5.5 V, VIN = 0 V to VCC V CC = 5.5 V, VOUT = 0 V to VCC VCC = 4.5 V, IOH = -4 mA V CC = 4.5 V, IOL = 8.0 mA V CC = 5.5 V, IOUT = 0 mA V IN VIL, VIN VIH fsi = 35 MHz, fso = 35 MHz
-10 -10 2.4
10 10
A A V
0.4 25 45
V mA mA
NOTES: 1. All voltages are measured with respect to Vss. 2. Icc is dependent upon actual output loading and cycle rates. Specified values are with outputs open.
3
LH5481/91
64 x 8 / 64 x 9 FIFO
AC TEST CONDITIONS 1
PARAMETER RATING
Input Pulse Levels Input Rise and Fall Times (10% / 90%) Input Timing Reference Levels Output Timing Reference Levels Output Load for AC Timing Tests
NOTE: 1. All voltages are measured with respect to Vss.
0 to 3 V Figure 4a 1.5 V 1.5 V Figure 4b
CAPACITANCE 1,2
PARAMETER DESCRIPTION TEST CONDITIONS RATING
CIN COUT
Input Capacitance Output Capacitance
TA = 25C, f = 1 MHz, V CC = 4.5 V TA = 25oC, f = 1 MHz, Vcc = 4.5 V
5 pF 7 pF
NOTES: 1. All voltages are measured with respect to Vss. 2. Sample tested only.
3.0 V 10%
90%
90% 10%
DEVICE UNDER TEST
167 1.73 V CL = 30 pF *
GND
5 ns
5 ns
5481-18
* INCLUDES JIG AND SCOPE CAPACITANCES
5481-4
Figure 4a. Input Rise and Fall Times
Figure 4b. Output Load Circuit
4
64 x 8 / 64 x 9 FIFO
LH5481/91
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)
SYMBOL PARAMETER 15MHz MIN MAX 25MHz MIN MAX 35MHz MIN MAX UNITS
fO tPHSI tPLSI tSSI tHSI tDLIR tDHIR tPHSO tPLSO tDLOR tDHOR tSOR tHSO tFT tBT tSIR tHIR tPIR tPOR tDLZOE tDHZOE tDHHF tDLHF tDLAFE tDHAFE tPMR tDSI tDOR tDIR tLXMR tAFE tHF tOD
Operating Frequency 2 SI HIGH Time SI LOW Time
3,8
15 15 20 11 18 -1 12 20 24 15 20 20 24 -1 0 36 28 5 5 5 7 7 35 35 40 40 40 40 35 25 35 -1 0 11 18
25 9 17 -1 10 18 20 9 17 18 20 -1 0 34 26 5 5 7 7 30 30 40 40 40 40 35 25 25 25 25 30 30 22
35
MHz ns ns ns ns
3,8 4 4
Data Setup to SI
-1 14
Data Hold from SI
Delay, SI HIGH to IR LOW Delay, SI LOW to IR HIGH SO HIGH Time SO LOW Time
3 3
16 18
ns ns ns ns
Delay, SO HIGH to OR LOW Delay, SO LOW to OR HIGH Data Setup to OR HIGH Data Hold from SO LOW Fallthrough Time Bubblethrough Time Data Setup to IR
5 5 8 8 6,9 6,9
16 18
ns ns ns ns
30 25
ns ns ns ns ns ns
Data Hold from IR
5 7 7
Input Ready Pulse HIGH
Output Ready Pulse HIGH
OE LOW to LOW Z (LH5481)
25 25 36 36 36 36
ns ns ns ns ns ns ns
OE HIGH to HIGH Z (LH5481) SI LOW to HF HIGH SO LOW to HF LOW SO or SI LOW to AFE LOW SO or SI LOW to AFE HIGH MR Pulse Width MR HIGH to SI HIGH MR LOW to OR LOW MR LOW to IR HIGH
7 7 7
22 20 20 20 30 30 20
ns ns ns ns ns ns ns
25 25 25 30 30 26
MR LOW to Output LOW MR LOW to AFE HIGH MR LOW to HF LOW
SO LOW to Next Data Out Valid
NOTES: 1. All time measurements performed at `AC Test Conditions.' 2. fO = fSI = fSO. 3. tPHSI + tPLSI = tPHSO + tPLSO = I/fO. 4 tSSI and tHSI apply when memory is not full. 5. tSIR and tHIR apply when memory is full and SI is HIGH. 6. High-Z transitions are referenced to the steady-state VOH - 500 mV and VOL + 500 mV levels on the output. 7. After reset goes LOW, all Data outputs will be at LOW level, IR goes HIGH and OR goes LOW. 8. Common dash number devices are guaranteed by design to function properly in a cascaded configuration.
5
LH5481/91
64 x 8 / 64 x 9 FIFO word location; FIFO data, if present, appears on the Data Output (DO) pins; and the Output Ready (OR) signal goes HIGH. If FIFO data is not present, Output Ready (OR) stays LOW, indicating that the FIFO is empty; in this case, the last valid data read from the FIFO remains on the Data Output (DO) pins. When the FIFO is not empty, Output Ready (OR) goes LOW after the rising edge of Shift Out (SO). The previous data remains on the Data Output (DO) pins until a falling edge of Shift Out (SO). Fallthrough Condition When the FIFO is empty, a data word entering through the Shift In (SI) action follows one of two sequences. If Shift Out (SO) is LOW, the data propagates to the Data Output (DO) pins; and Output Ready (OR) goes HIGH and stays HIGH until the next rising edge of Shift Out (SO). If Shift Out (SO) is held HIGH while data is shifted into an empty FIFO as occurs in depth cascading of FIFOs, data propagates to the Data Output (DO) pins, and Output Ready (OR) pulses HIGH for a minimum time duration specified by tPOR and then goes back LOW again. The stored word remains on the Data Output (DO) pins. If more words are written into the FIFO, they line up behind the first word, and do not appear on the Data Output (DO) pins until Shift Out (SO) has returned LOW. Bubblethrough Condition When the FIFO is full, Shift Out (SO) action initiates one of the following two sequences: If Shift In (SI) is LOW, Input Ready (IR) goes HIGH and stays HIGH until the next rising edge of Shift In (SI). If Shift In (SI) is held HIGH while data is shifted out of a full FIFO, as occurs in depth cascading of FIFOs, Input Ready (IR) pulses HIGH for a minimum time duration specified by tPIR, and then goes back LOW again. Special Data Input (DI) setup and hold times (tSIR and tHIR, respectively) are defined for this condition.
OPERATIONAL DESCRIPTION
Unlike earlier versions of FIFOs, the LH5481 and LH5491 use dual-port Random-Access-Memory, write and read pointers, and special control logic. The write pointer is incremented by the falling edge of the Shift In (SI) signal, while the read pointer is incremented by the falling edge of the Shift Out (SO) signal. The Input Ready (IR) signal enables data writing to the FIFO. The Output Ready (OR) signal indicates valid read information is available on the Data Output (DO) pins. Resetting The FIFO The FIFO must be reset, upon power-up, using the Master Reset (MR) signal. This causes the FIFO to enter an empty state, indicated by the Output Ready (OR) being LOW and Input Ready (IR) being HIGH. All Data Output (DO) pins will be LOW in this state. The AFE flag will be HIGH, and the HF flag will be LOW. If Shift In (SI) is HIGH, when the Master Reset (MR) signal is ended, then the data on the Data Input (DI) pins will be written into the FIFO, and Input Ready (IR) will return LOW until Shift In (SI) is brought LOW. If Shift In (SI) is LOW when the Master Reset (MR) is deasserted, then Input Ready (IR) goes HIGH, but the data on the Data Input (DI) pins does not enter the FIFO until Shift In (SI) goes HIGH. Shifting Data In Data Input (DI) is shifted into the FIFO on the rising edge of Shift In (SI). This loads input data into the FIFO, and causes Input Ready (IR) to go LOW. When a falling edge of Shift In (SI) occurs,the write pointer increments to the next word position, and Input Ready (IR) goes HIGH, indicating that the FIFO is ready to accept new data. When the FIFO is full, Input Ready (IR) remains LOW after the negative edge of Shift In (SI) signal; Shift Out (SO) action is required to unload a word of data and bring Input Ready (IR) HIGH. (See `Bubblethrough Condition' description.) Shifting Data Out Data is shifted out of the FIFO on the falling edge of Shift Out (SO). The read pointer increments to the next
6
64 x 8 / 64 x 9 FIFO
LH5481/91
TIMING DIAGRAMS
1/fo
1/fo
SHIFT IN tPHSI
*
t PLSI t DHIR
INPUT READY t HSI t DLIR
DATA IN t SSI
AFE t DLAFE HF * NOTE: FIFO Contains 8 Words
5481-5
(LOW)
Figure 5. Data In Timing
1/fo
1/fo
SHIFT OUT t PHSO
**
t PLSO t DHOR
OUTPUT READY tHSO tDLOR t SOR
DATA OUT tOD HF (LOW) tDHAFE
AFE ** NOTE: FIFO Contains 9 Words
5481-6
Figure 6. Data Out Timing
7
LH5481/91
64 x 8 / 64 x 9 FIFO
TIMING DIAGRAMS (cont'd)
1/fo
1/fo
SHIFT IN t PHSI
***
t PLSI t DHIR
INPUT READY t HSI t DLIR
DATA IN t SSI (LOW) t DHHF
AFE
HF *** NOTE: FIFO Contains 31 Words
5481-7
Figure 7. Data In Timing
1/fo
1/fo
SHIFT OUT t PHSO
****
t PLSO t DHOR
OUTPUT READY t HSO t DLOR t SOR
DATA OUT tOD
HF t DLHF AFE (LOW)
**** NOTE: FIFO Contains 32 Words
5481-8
Figure 8. Data Out Timing
8
64 x 8 / 64 x 9 FIFO
LH5481/91
TIMING DIAGRAMS (cont'd)
1/fo
1/fo
SHIFT IN t PHSI
*****
t PLSI t DHIR
INPUT READY t HSI t DLIR
DATA IN t SSI HF (HIGH) t DHAFE
AFE ***** NOTE: FIFO Contains 55 Words
5481-9
Figure 9. Data In Timing
1/fo
1/fo
SHIFT OUT t PHSO
******
t PLSO t DHOR
OUTPUT READY t HSO t DLOR t SOR
DATA OUT tOD
AFE t DLAFE HF (HIGH)
****** NOTE: FIFO Contains 56 Words
5481-10
Figure 10. Data Out Timing
9
LH5481/91
64 x 8 / 64 x 9 FIFO
TIMING DIAGRAMS (cont'd)
SHIFT OUT
SHIFT IN t BT
INPUT READY t PIR
DATA IN t SIR t HIR
5481-11
Figure 11. Bubblethrough Timing (Reading a Full FIFO)
SHIFT IN
SHIFT OUT t FT
OUTPUT READY t SOR t POR
DATA OUT
5481-12
Figure 12. Fallthrough Timing (Writing an Empty FIFO)
10
64 x 8 / 64 x 9 FIFO
LH5481/91
TIMING DIAGRAMS (cont'd)
t PMR
MASTER RESET t DIR
INPUT READY t DOR
OUTPUT READY t DSI
SHIFT IN t LXMR
DATA OUT t DHF
HF t DAFE
AFE
5481-13
Figure 13. Master Reset Timing
11
LH5481/91
64 x 8 / 64 x 9 FIFO
TIMING DIAGRAMS (cont'd)
EMPTY SHIFT IN
1
2
8
9
10
31
32
33
55
56
57
64
FULL
...
...
...
...
HF
AFE
5481-14
Figure 14. Shifting Words In
FULL SHIFT OUT
64
63
56
55
54
32
31
30
9
8
7
1
EMPTY
...
...
...
...
HF
AFE
5481-15
Figure 15. Shifting Words Out
12
64 x 8 / 64 x 9 FIFO
LH5481/91
FIFO EXPANSION
HF/AFE
HF/AFE
IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
64 x 8/9
MR
SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
IR SI DI0 DI1 DI2 DI3 256 x 8/9 DI4 DI5 DI6 DI7 DI8 MR
SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
SHIFT OUT
COMPOSITE INPUT READY IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 256 x 8/9 DI4 DI5 DI6 DI7 DI8 MR SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
COMPOSITE OUTPUT READY
64 x 8/9
MR
SHIFT IN
IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
64 x 8/9
MR
SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
IR SI DI0 DI1 DI2 DI3 256 x 8/9 DI4 DI5 DI6 DI7 DI8 MR
SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
MR
5481-16
Figure 16. 320 x 24/27 Configuration Using 64 x 8/9 (LH5481/91) & 256 x 8/9 (LH5485/95) FIFOs
13
LH5481/91
64 x 8 / 64 x 9 FIFO
FIFO EXPANSION (cont'd)
HF/AFE SI IR DI0 DI1 DI2 256 x 8/9 DI3 DI4 DI5 DI6 DI7 DI8 MR OR SO DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
HF/AFE SHIFT IN INPUT READY
DATA IN
SI IR DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
OR SO DO0 DO1 DO2 64 x 8/9 DO3 DO4 DO5 DO6 DO7 DO8 MR
OUTPUT READY SHIFT OUT
DATA OUT
MR
5481-17
Figure 17. 128 x 8/9 Configuration FIFOs are expandable in depth and width. However, in forming wider words, external logic is required to generate composite Input Ready and Output Ready flags. This is due to the variation of delays of the FIFOs. For example, the circuit of Figure 16 uses simple AND gates as the external IR and OR generators. More complex logic may be required if fallthrough and bubblethrough pulses are needed by the external system. FIFOs can be easily cascaded to any desired depth, as illustrated in Figure 17. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.
NOTES: 1. When the memory is empty, the last word read remains on the outputs until Master Reset is strobed, or a new data word bubbles through to the output. However, OR remains LOW, indicating that the data word at the output is not valid. 2. When the output data word changes as a result of a pulse on SO, the OR signal always goes LOW before the output data word changes and stays LOW until a new data word has appeared at the outputs. Anytime OR is HIGH, there is valid stable data on the outputs. 3. All SHARP FIFOs can be cascaded with other SHARP FIFOs of the same architecture (i.e., 64 x 8/9 with 64 x 8/9). However, they may not cascade with FIFOs from other manufacturers.
14
64 x 8 / 64 x 9 FIFO
LH5481/91
PACKAGE DIAGRAMS
28SK-DIP (DIP028-P-0300)
28 15 7.05 [0.278] 6.65 [0.262] 1 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 14 0.35 [0.014] 0.15 [0.006] 7.62 [0.300] TYP. 0 TO 15
DETAIL
DIMENSIONS IN MM [INCHES]
28DIP-1
28-pin, 300-mil PDIP
28PLCC (PLCC28-P-S450)
1.22 [0.048] 1.07 [0.042] x 45 1.27 [0.050] BASIC NON-ACCUM
12.57 [0.495] 12.32 [0.485] 11.56 [0.455] 11.43 [0.450]
10.92 [0.430] 9.91 [0.390]
11.56 [0.455] 11.43 [0.450] 12.57 [0.495] 12.32 [0.485] 0.81 [0.032] 0.66 [0.026]
DETAIL
4.57 [0.180] 4.19 [0.165] 2.79 [0.110] 2.52 [0.099] 0.51 [0.020] MIN. DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 0.53 [0.021] 0.33 [0.013]
28PLCC
0.10 [0.004]
28-pin, 450-mil PLCC
15
LH5481/91
64 x 8 / 64 x 9 FIFO
ORDERING INFORMATION
LH#### Device Type X Package - ## Speed 15 25 Frequency (MHz) 35 D 28-pin, 300-mil PDIP (DIP028-P-0300) U 28-pin Plastic Leaded Chip Carrier (PLCC28-P-S450) 5481 64 x 8 FIFO 5491 64 x 9 FIFO Examples: LH5481D-25 (64 x 8 FIFO, 28-pin, 300-mil PDIP, 25 MHz) LH5491U-35 (64 x 9 FIFO, 28-pin PLCC, 35 MHz)
5481MD
16

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