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| Semiconductor May 1997 NOT RE ME COM DF NDE OR NE ES WD IGN S CA3194 Single Chip PAL Luminance/Chroma Processor Features * All PAL Luminance and Chrominance Processing Circuitry on a Single Chip in a 24-Lead Plastic Package * Phase-Locked Subcarrier Regeneration Utilizing Sample-and-Hold * DC Controls for Brightness, Contrast, and Color Saturation Functions * Input for Average Beam-Current Limiting * Contrast Control Having Excellent Tracking of Luma and Chroma Channels * Low-lmpedance RGB Outputs with Excellent Tracking for Direct Coupling to Video Driver Circuitry Description The Harris CA3194E is a silicon monolithic integrated circuit designed to perform all of the signal processing functions for both the chroma and luminance signals of PAL color television receivers. This circuit performs all the functions needed between the video detector and the video RGB output stages. DC contrast, brightness, and saturation controls and average beam limiting functions are included. The RGB buffer stages are capable of delivering 5mA of current into the video output stages. NOTE: Formerly Dev. No. TA10313. Ordering Information PART NUMBER CA3194E TEMPERATURE RANGE -40oC to +85oC PACKAGE 24 Lead PDIP Pinout CA3194 (PDIP) TOP VIEW GND 1 CHROMA OUT 2 SAT. CONTR. 3 CHROMA INPUT 4 ACC FILTER 5 ACC FILTER 6 APC FILTER 7 APC FILTER 8 90o INPUT 9 0o INPUT 10 VCO OUTPUT 11 VCC 12 AVER. BEAM 24 INFO 23 BRIGHTNESS CONTROL 22 PICTURE CONTROL 21 LOW PASS FILTER 20 LUMA INPUT 19 PEAK BEAM LEVEL 18 R OUTPUT 17 G OUTPUT 16 B OUTPUT 15 VR-Y INPUT 14 VB-Y INPUT 13 SANDCASTLE TERMINAL VOLTAGE AND CURRENT RATINGS VOLTAGE (NOTE 1) -V MIN MAX 0 13 0 8 0 5 0 Note 0 Note 0 Note 0 8 0 8 0 13 0 13 0 12 0 5 0 5 0 13 0 13 0 13 0 Note 0 5 0 Note 0 8 0 5 0 12 CURRENT - mA IIN IOUT 0 30 10 0.1 0.5 0.7 10 1.5 1.5 10 10 10 - TERMINAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NOTE: 1. The maximum should not exceed the VCC voltage. Voltage with respect to Terminal 1 for VCC (Terminal 12) of 12V 10%. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 File Number 1270.3 7-56 Specifications CA3194 Absolute Maximum Ratings Supply Voltage and Current Pin 12 Voltage Range . . . . . . . . . . . . . . . . 11V (Min) to 13V (Max) Pin 12 Current Range . . . . . . . . . . . . . 44mA (Typ) to 60mA (Max) Power Dissipation Up to TA = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825mW Above TA = +25oC. . . . . . . . . . . . . . . . Derate Linearly 8.7mW/oC Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC Thermal Package Characteristics (oC/W) JA PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TA = +25oC, VCC = 12V, VS = 2.85V, VC = 2.85V, VAB = VPB = VCC, VB adjusted for V18 = 6.3V, CX adjusted for FOSC = 4.43361875MHz, Sandcastle: VBG = 8.0V, VBLANK = 3.5V - Burst Gate centered on Burst. These conditions exist except as otherwise noted. See Figure 19 for test circuit TYPICAL VALUE PARAMETER LUMINANCE SECTION Input Impedance (Terminal 20) TEST CONDITIONS UNITS 6 5 k pF VP-P MHz Luminance Channel Input Voltage Bandwidth of Luminance Channel Luma Input Signal = 30% Sync. Luma Input Signal: 0.5VP-P (30% Sync) modulated CW Adj. modulation frequency for -3dB at color outputs. For Control Characteristics, See Figures 1 and 2. Luma Input Signal: 0.5VP-P (30% Sync) VB 0V - 5V,Measured at Pin 18 black level. See Figures 1 and 2. 0.5 8 Brightness Control Range (Terminal 23) Output Black Level Range Offset Contrast Control Range (Terminal 22) 0 - 3.5 VDC 5.9-9.7 0.6 Max. VDC VDC VDC dB Luminance Input: 0.5VP-P (30% Sync), for Control Characteristics. See Figure 3 Luminance Input: 0.5VP-P (30% Sync), VC = 0.5V - 5V measure Pin 18 black level to maximum white level. See Figure 4. Luminance Input: 0.5VP-P (30% Sync), VC = 5V, read black level to peak white. See Figures 5 and 6. 0-5 Luminance Gain Control Range 32 RGB Output Swing 4 VP-P CHROMlNANCE SECTION Input Impedance (Terminal 4) See Figures 7 and 8. 4.5 5 Chroma Channel Input Voltage Chroma Burst ACC Range Input Burst Level for Kill (Note 1) Adjust chroma input Pin 4 until Pin 2 25mVP-P. Measure Burst level at Pin 4. Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P. Luminance Input: 0.35VP-P, VS adjusted for Chroma at Pin 18 = 2VP-P. VC is adjusted for luminance at Pin 18 = 2VP-P, VC is again adjusted for luminance of +6 and -9dB. Then read chroma percentage difference. See Figure 9. 220 100 +6 - (-20) 10 5 k pF mVP-P mVP-P dB mVP-P % Contrast Control Chroma/Luma Tracking 7-57 Specifications CA3194 Electrical Specifications TA = +25oC, VCC = 12V, VS = 2.85V, VC = 2.85V, VAB = VPB = VCC, VB adjusted for V18 = 6.3V, CX adjusted for FOSC = 4.43361875MHz, Sandcastle: VBG = 8.0V, VBLANK = 3.5V - Burst Gate centered on Burst. These conditions exist except as otherwise noted. See Figure 19 for test circuit (Continued) TYPICAL VALUE 0-5 2.5 PARAMETER Saturation Control Range (Terminal 3) Maximum Chroma Output Voltage (Terminal 2) TEST CONDITIONS For control characteristic, see Figure 10. Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P. Adjust VC and VS for maximum Pin 2 output. UNITS VDC VP-P OSCILLATOR SECTION Pull-In Range Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P. Adjust CX for HI/LO fOSC without Chroma signal. Apply signal to lock. 500 Hz Static Phase Error 2 Deg./ 100Hz DEMODULATOR SECTION R-Y Demodulator Conversion Gain Chroma Input: Burst =100mV, Chroma = 220mVP-P,Vo. Adjust VC for V18 = 1V. Read V15. Calculate V18/V15. Chroma Input: Burst = 100mVP-P, Uo. Read V16 and V14. Calculate V16/V14. VC remains as for R-Y gain. Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Uo read V17 and V16, Calculate V17/V16. VC remains as above. Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Vo. Read V17 and V18. Calculate V17/V18. VC remains as above. No Chroma or Luma Input. Read residual carrier at outputs. 10 Ratio B-Y Demodulator Conversion Gain 18 Ratio G-Y/B-Y Matrix Ratio 0.2 Ratio G-Y/R-Y Matrix Ratio 0.5 Ratio Sub-Carrier and Harmonic Content at Outputs SANDCASTLE PULSE Horizontal and Vertical Blanking Pedestal Burst Gate Pulse NOTES: 30 mVP-P 2-5 6.5 - VCC V V 1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17. 2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals. 3. The reference voltage can be adjusted by changing the values of the voltage divider. Circuit Description (See Block Diagram and Figure 20) The chroma signal is externally separated from the video signal by means of a bandpass or high-pass filter and applied to pin 4. The burst is separated in the first chroma stage and applied to the synchronous detector which provides information to sample-and-hold circuits for APC (phase-locked loop), ACC (automatic chroma gain control) and identification and killing. The 4.43MHz crystal oscillator is phase-locked to the burst and provides 0 degrees and 90 degrees (via an external phase shifter) carriers to the chroma demodulators. The burst and chroma amplitude at the output of the first chroma amplifier is kept constant by the automatic gain control. The second chroma stage provides saturation control (pin 3) which tracks the contrast control in the luminance channel. This stage is also used for color killing. A buffer stage drives the external PAL delay line. The separated U and V signals are applied to pins 14 and 15, respectively, and demodulated. A standard G-Y matrix is included on the chip. The luminance signal passes through the subcarrier trap and through the luminance delay line and enters the chip at pin 20. Contrast and brightness control is provided before the luminance signal is combined with the color difference signals in the Y matrix. Average and peak beam limiting circuits are controlled from pins 24 and 19. 7-58 ACC FILTER 6 5 7 8 Block Diagram ACC FILTER APC FILTER APC FILTER BG SYNCHRONOUS DETECTOR FOR APC AND ACC SAMPLE AND HOLD BG BG SAMPLE AND HOLD FF SAMPLE AND HOLD BG BG CHROMA INPUT 4 1ST CHROMA STAGE + SWITCHING BG ACC KILLER FLIP FLOP FF 0 DEGRE CARRIER 10 FF AMPLIFIER +PHASE EQ BG SANDCASTLE DECODER BL Y MATRIX B OUTPUT AMPLIFIER + PAL SWITCH + PHASE EQ BLANKING BG 90 DEGREE CARRIER BUFFER 9 COMPARATOR + LEVEL SHIFT IDENT 90o AMPLIFIER 0 DEGREE AMPLIFIER 11 VCO OUTPUT 0o INPUT 90o INPUT SAND 13 CASTLE 16 B OUTPUT BG SAT. CONTR. 3 2ND CHROMA STAGE CHROMA OUT 2 BUFFER STAGE CA3194 7-59 G-Y MATRIX Y MATRIX G OUTPUT Y MATRIX R OUTPUT BG AVERAGE BEAM LIMITER BRIGHTNESS COMPARATOR 24 AVER. BEAM INFO. 23 BRIGHTNESS CONTROL 21 LOW PASS FILTER VB-Y INPUT 14 B-Y DEMOD 17 G OUTPUT VR-Y INPUT 15 R-Y DEMOD 18 R OUTPUT 12 VCC PEAK BEAM LIMIT COMPARATOR 1 GROUND (SUB) LUMA INPUT 20 LUMA AMPLIFIER 22 19 PEAK BEAM LEVEL PICTURE CONTROL CA3194 Typical Performance Curves 11 10 PIN 18 - BLACK LEVEL (V) 9 8 7 6 5 4 3 0 1 2 3 4 PIN 23 - BRIGHTNESS CONTROL (VB, V) 5 VC = VS = 2.85V VCC = 12V PIN 20 : 0.5VP-P (30% SYNC) PIN 2 - CHROMA OUTPUT (VP-P) RED BAR 4 VS = 2.85V VCC = 12V PIN 4 : BURST = 100mVP-P CHROMA = 220mVP-P 3 2 1 0 0 1 2 3 4 PIN 22 - COLOR CONTRAST CONTROL (VC, V) 5 FIGURE 1. BRIGHTNESS CONTROL (VB) MEASURED AT PIN 18 OUTPUT TERMINAL FIGURE 2. CONTRAST CONTROL (VC) MEASURED AT 2ND CHROMA AMPLIFIER OUTPUT TERMINAL 4 VS = 2.85V VCC = 12V PIN 20 : 0.5VP-P (30% SYNC) BLACK LEVEL = 7V 32 28 LUMA AMPL GAIN (dB) 24 20 16 12 8 4 VC = VS = 2.85V V18 = 2VP-P AT VCC = 12V VB SET TO BLACK LEVEL = 7V PIN 18 - LUMA OUTPUT (V) (WHITE TO BLACK LEVEL) 3 2 1 0 0 1 2 3 4 PIN 22 - CONTRAST CONTROL (VC, V) 5 0 7 8 9 10 11 12 13 14 15 16 17 PIN 12 - SUPPLY VOLTAGE (V) FIGURE 3. CONTRAST CONTROL (VC) MEASURED AT PIN 18 OUTPUT TERMINAL FIGURE 4. LUMA GAIN vs SUPPLY VOLTAGE (VCC) MEASURED AT LUMA AMPLIFIER OUTPUT TERMINAL 18 16 BLUE OUTPUT (V16 MAX, V) 14 12 10 8 6 BOTTOM CLIPPING 4 2 11 12 13 14 15 PIN 12 - SUPPLY VOLTAGE (V) 16 BLACK LEVEL V18 - % DIFFERENCE LUMA/CHROMA VS = 2.85V VB AND VC ADJUSTED FOR MAX LINEAR V16 PIN 4: BURST = 100mVP-P CHROMA = 220mVP-P 20 10 TOP CLIPPING CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P LUMA INPUT: 0.5VP-P (30% SYNC) ADJUST VC FOR V18 = VPEAK LUMA, THEN ADJUST VS FOR V18 = 2VPEAK CHROMA (RED BAR) 0 -10 -20 0 1 2 3 4 PIN 22 - CONTRAST CONTROL (VC, V) 5 FIGURE 5. LINEAR OPERATING RANGE AS A FUNCTION OF VCC MEASURED AT PIN 16 OUTPUT TERMINAL (BEST OPERATING RANGE IS 11-13V VCC) FIGURE 6. LUMA/CHROMA TRACKING AS A FUNCTION OF VC MEASURED AT PIN 18 OUTPUT TERMINAL 7-60 CA3194 Typical Performance Curves (Continued) V18 - V (BLACK LEVEL TO WHITE) LUMA 6 5 4 3 2 1 0 0 0 CHROMA OUTPUT (V2, dB) -1 -2 -3 -4 COLOR UNKILL VC = VS = 2.85V VCC = 12V CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P (0dB) CHROMA OUTPUT: 880mVP-P (0dB) CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P LUMA INPUT: 0.5VP-P (30% SYNCH) ADJUST VC FOR V18 = 2VPEAK LUMA, THEN ADJUST VS FOR V18 = 2VPEAK CHROMA (RED BAR) COLOR KILL -5 -20 -10 CHROMA INPUT (V4, dB) 0 +6 1 2 3 4 5 PIN 22 - CONTRAST CONTROL (VC, V) FIGURE 7. ACC CHARACTERISTICS MEASURED AT PIN 2 OUTPUT TERMINAL V18 - V (BLACK LEVEL TO WHITE) RED BAR FIGURE 8. LUMA/CHROMA TRACKING vs CONTRAST CONTROL MEASURED AT PIN 18 OUTPUT TERMINAL 6 5 4 3 2 1 0 0 CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P LUMA INPUT: 0.5VP-P (30% SYNCH) ADJUST VC FOR V18 = 2VPEAK LUMA, THEN ADJUST VS FOR V18 = 2VPEAK CHROMA (RED BAR) PIN 2 - CHROMA OUTPUT (VP-P) RED BAR 4 VC = 2.85V VCC = 12V PIN 4 : BURST = 100mVP-P CHROMA = 220mVP-P 3 2 1 0 0 1 2 3 4 PIN 3 - CHROMA SATURATION CONTROL (VC , VP-P) 5 1 2 3 4 PIN 22 - CONTRAST CONTROL (VC, V) 5 FIGURE 9. LUMA/CHROMA TRACKING WITH CONTRAST CONTROL MEASURED AT PIN 18 OUTPUT TERMINAL FIGURE 10. SATURATION CONTROL (VS) MEASURED AT CHROMA AMPLIFIER OUTPUT TERMINAL PIN 2 R/G AND R/B VOLT DIFF. (mV) 100 VR - VG 0 -100 PIN 18 - RED OUTPUT (VP-P) RED BAR VC = VS = 2.85V VCC = 12V NO INPUT SIGNAL 8 6 BOTTOM CLIPPING OF RED BAR CENTER DIFF. CORRECTED TO ZERO AT 7.0V - PIN 18 100 VR - VB 0 -100 4 VS = 2.85V VCC = 12V PIN 4 : BURST = 100mVP-P CHROMA = 220mVP-P ADJUST VC (DL700 DELAY LINE IN CIRCUIT) 0 1 2 PIN 2 - CHROMA OUTPUT (VP-P) RED BAR 3 2 0 5 6 7 8 9 R - OUT (PIN 18) BLACK LEVEL REFERENCE - (VB ADJ, V) FIGURE 11. DIFFERENTIAL BLACK-LEVEL TRACKING MEASURED AT RGB OUTPUT TERMINALS FIGURE 12. PIN 18 OUTPUT vs PIN 2 VOLTAGE MEASURED AT CHROMA OUTPUT TERMINALS AND R OUTPUT 7-61 CA3194 Typical Performance Curves 10 PIN 18 - OUTPUT PEAK WHITE AND BLACK LEVEL (V) VCC = 12V VC : SET FOR V18 = 2VP-P VIN : SET FOR BLACK LEVEL = 7V PIN 20: LUMA = 0.5VP-P (30% SYNC) INITIAL LUMA SET AT 2.0 VP-P (Continued) 13 12 PIN 18 - LUMA OUTPUT (V) PEAK WHITE 11 10 9 8 7 6 5 0 2 4 6 8 10 0 1 2 3 4 PIN 24 - AVERAGE BEAM LIMITER (VAB, V) R = 47k BLACK LEVEL VCC = 12V VC = 5V VB = 3.5V PIN 20: LUMA = 0.5VP-P (30% SYNC) RC - CONTRAST TERMINAL RESISTANCE = 47k 5 6 7 8 9 10 9 PEAK WHITE LEVEL 8 7 REDUCED INITIAL BLACK LEVEL SET 7.0V LUMA BLACK LEVEL 6 PIN 24 - AVERAGE BEAM LIMITER (VAB, V) FIGURE 13. AVERAGE BEAM LIMITER (VAB) MEASURED AT PIN 18 OUTPUT FIGURE 14. AVERAGE BEAM LIMITER (VAB) MEASURED AT PIN 18 OUTPUT 12 11 10 R =15k PIN 18 (V) 9 8 7 6 5 4 0 1 2 3 4 5 6 7 8 9 10 PIN 24 - AVERAGE BEAM LIMITER (VAB, V) R =33k R = 47k R = 22k PEAK WHITE VCC = 12V VC = 5V VB : SET FOR BLACK LEVEL = 6.3V PIN 20: LUMA = 0.5VP-P (30% SYNC) VARY RC - CONTRAST TERMINAL RESISTANCE BLACK LEVEL BG PULSE VBG = 6.5V TO VCC VBLANK = 2V TO 5V 0V H+V BLANK PEDESTAL FIGURE 15. AVERAGE BEAM LIMITER (VAB) MEASURED AT PIN 18 OUTPUT FIGURE 16. SANDCASTLE INPUT WAVEFORM VCC 2 5.1M CA3194E 0.01 F +5V 5K 3 VCC 5.1M 5 47K 300 (NOTE 2) 1.0F (NOTE 1) 27K (NOTE 1) CA3194E CHROMA OUTPUT SATURATION CONTROL 5.1M 1.5K NOTES: 1. Nominal values used in NTSC system. 2. Small signal n-p-n. FIGURE 17. KILLER-THRESHOLD LEVEL CONTROL FIGURE 18. EXTERNAL OVERLOAD DETECTOR 7-62 CA3194 Test Circuit BEAM LIMIT INFO (VAB) 1K + LUMA INPUT + 24 AV. BEAM LIMIT 23 BRIGHTNESS 22 CONTRAST 21 LP FILTER 20 LUMA INPUT 19 PEAK BEAM LIMIT 18 R OUT 17 G OUT 16 B OUT 15 VR-Y BRIGHTN. CONTRAST (VB) (VC) 1K8 15K + 15K RC 220n 2.2 +12V R (VPB) OUTPUTS G B SAND CASTLE INPUT 2.2 + 1 1K 14 VB-Y 15K 13 SAND CASTLE INPUT 16 CA3194E CHROMA OUT 2 CHROMA INPUT 4 68p 15K + 22 47n 10p CO 2K2 SAT. (VS) 47 2K2 + 22n + 1 0.1 120p 330 VCO 90o 9 22H 5% RO 10% VCO 0o 10 VCO OUT 11 CHROMA INPUT 3n3 GND 1 SAT. 3 ACC 5 ACC 6 APC 7 APC 8 B+ 12 +12V 820 CX 5-25p 0.1 + 22 39pF DELAY LINE AMPLITUDE 1K 10n 390 DL PHASE 10n L4 10H 47p 2 DL 700 1 3 L5 9H BIF. 430/5% 4 FIGURE 19. TEST CIRCUIT NOTES: 4.43361875MHz Trim CO for zero phase; Trim RO for quad phase. 7-63 CA3194 Test Circuit (Continued) BEAM LIMIT INFO (VAB) 10K + LUMA INPUT + 24 AV. BEAM LIMIT BRIGHTN. CONTRAST (VB) (VC) 1K8 15K + 15K 220n 2.2 +12V R (VPB) OUTPUTS G B SAND CASTLE INPUT 2.2 + 1 1K 15K 13 SAND CASTLE INPUT 16 23 BRIGHTNESS 22 CONTRAST 21 LP FILTER 20 LUMA INPUT 19 PEAK BEAM LIMIT 18 R OUT 17 G OUT 16 B OUT 15 VR-Y 14 VB-Y CA3194E CHROMA OUT 2 CHROMA INPUT 4 68p 15K + 22 SAT. (VS) 0.05 + 22 + 0.01 22n + 0.1 120p 10% VCO 90o 9 33H 1.8K 2K2 3.3 330 5% RO VCO 0o 10 VCO OUT 11 CHROMA INPUT 3n3 GND 1 SAT. 3 ACC 5 ACC 6 APC 7 APC 8 B+ 12 +12V 0.1 + 22 1500 CX 5-25p 10p CO 2K2 39pF DELAY LINE AMPLITUDE 1K 10n 390 DL PHASE 10n L4 10H 47p 2 PAL DL 50 1 3 L5 9H BIF. 430/5% 4 FIGURE 20. APPLICATION CIRCUIT FOR PAL M NOTE: 3.575611MHz 7-64 |
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