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12BIT 10MSPS ADC
GENERAL DESCRIPTION
The BL8531H_ADC is a CMOS 12bit analog-to-digital converter (ADC). into 12bit binary It converts the analog input signal digital codes at a maximum
BL8531H_ADC
FEATURES
Resolution : 12bit - Maximum Conversion Rate : 10MHz - Power Supply : 5V - Power Consumption : 100mW (typical) - Reference Voltage : 3.5V, 1.5V (dual reference) - Input Range : 0.5V ~ 4.5V (4.0VP-P) - Differential Linearity Error : 0.7 LSB - Integral Linearity Error : 1.0 LSB - Signal to Noise & Distortion Ratio : 65dB - Total Harmonic Distortion : 74dB - 3 Channel Inputs - Digital Output : CMOS Level - Operating Temperature Range : 0C ~ 70C
-
sampling rate of 10MHz. The device is a monolithic ADC with an on-chip, high-performance, sample-and-hold Amplifier (SHA) and current referenc. The structure allows both differential and single-ended input. This 12bit ADC has also 3 channel MUX, so 3 channel inputs are acceptable.
TYPICAL APPLICATIONS
CCD Imaging (Copiers, Scanners, Cameras) Medical Instruments Digital Communication Systems
FUNCTIONAL BLOCK DIAGRAM
3CH. Analog Inputs
SHA
MDAC 1
MDAC 2
MDAC 3
Reference Input
FLASH 1 4
FLASH 2 3
FLASH 3 3
FLASH 4 3
Main Bias Clock
CLOCK GEN.
DIGITAL LOGIC
12
Digital Output
Ver 1.1 (Apr. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
12BIT 10MSPS ADC
CORE PIN DESCRIPTION
NAME
REFTOP REFBOT CML VDDA VBB VSSA R_INP R_INN G_INP G_INN B_INP B_INN REDB GREENB BLUEB STBY CKIN D[11:0] VSSD VDDD
BL8531H_ADC
I/O TYPE
AO AO AO AP AG AG AI AI AI AI AI AI DI DI DI DI DI DO DG DP
I/O PAD
poar10_bb poar10_bb poar10_bb vdda vbba vssa piar10_bb piar10_bb piar10_b piar10_bb piar10_bb piar10_bb picc_bb picc_bb picc_bb picc_bb picc_bb pot4_bb vssd vddd
PIN DESCRIPTION
Reference Top Force (3.5V) Reference Bottom Force (1.5V) Internal Bias Analog Power (5V) Analog Sub Bias Analog Ground Analog Input (RED) + (Input Range : 1.5V ~ 3.5V) Analog Input (RED) (Input Range : 1.5V ~ 3.5V) Analog Input (GREEN) + (Input Range : 1.5V ~ 3.5V) Analog Input (GREEN) (Input Range : 1.5V ~ 3.5V) Analog Input (BLUE) + (Input Range : 1.5V ~ 3.5V) Analog Input (BLUE) (Input Range : 1.5V ~ 3.5V) RED Channel Select (0:select) GREEN Channel Select (0:select) BLUE Channel Select (0:select) VDD=power saving (standby), GND=normal Sampling Clock Input Digital Output Digital GND Digital Power (5V) vdda vssa vbb vddd vssd
I/O TYPE ABBR.
-AI : Analog Input -DI : Digital Input -AO : Analog Output -DO : Analog Output -AP -AG -DP -DG : : : : Analog Power Analog Ground Digital Power Digital Ground
-AB : Analog Bidirection -DB : Digital Bidirection
R_INP R_INN G_INP G_INN B_INP B_INN
REDB GREENB BLUEB
bl8531h_adc
[MSB:LSB] D[11:0]
REFTOP REFBOT CML STBY CKIN
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12BIT 10MSPS ADC
ABSOLUTE MAXIMUM RATINGS
Characteristics
Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Range Operating Temperature Range
BL8531H_ADC
Symbol
VDD R_INP/R_INN G_INP/G_INN B_INP/B_INN CLK Tstg Topr 6.0
Value
Unit
V V V
VSS to VDD VSS to VDD -45 to 150 0 to 70
C C
NOTES 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Symbol VDDA1 VDDA2 VDDA3 Analog Input Voltage Operating Temperature R_INP/G_INP/B_INP R_INN/G_INN/B_INN Toper 0 0.5 2.5 70 4.5 V 4.75 5.0 5.25 V Min Typ Max Unit
C
NOTES It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same source to avoid power latch-up.
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12BIT 10MSPS ADC
DC ELECTRICAL CHARACTERISTICS
Characteristics Differential Nonlinearity Integral Nonlinearity Offset Voltage Symbol DNL INL Min Typ 0.7 1.0 10 Max 1 Unit LSB LSB
BL8531H_ADC
Test Condition
REFTOP=3.5V REFBOT=1.5V
OFF
-
-
mV
(Converter Specifications : VDDA=VDDD=5V, VSSA=VSSD=0V, Toper=25C, REFTOP=3.5V, REFBOT=1.5V unless otherwise specified)
AC ELECTRICAL CHARACTERISTICS
Characteristics Maximum Conversion Rate Dynamic Supply Current Signal-to-Noise & Distortion Ratio Total Harmonic Distortion Symbol Min Typ Max Unit Test Condition AINR=R_INP-R_INN fc 10 MHz AING=G_INP-G_INN AING=B_INP-B_INN IVDD SNDR THD 20 65 mA dB fc=10MHz (without system load) AIN=1MHz, Differential Input AIN=1MHz, Differential Input
-
74
-
dB
(Conversion Specifications : VDDA=VDDD=5V, VSSA=VSSD=0V, Toper=25C, REFTOP=3.5V, REFBOT=1.5V unless otherwise specified)
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12BIT 10MSPS ADC
I/O CHART
Index 0 1 2 | 8197 8192 8193 | 16381 16382 16383 R_INP Input (V) 0.500 ~ 0.501 0.501 ~ 1.502 0.502 ~ 1.503 | 2.499 ~ 2.5000 2.500 ~ 2.501 2.501 ~ 2.502 | 4.497 ~ 4.498 4.498 ~ 4.499 4.499 ~ 4.500 2.5 2.5 2.5 2.5 2.5 2.5 R_INN Input (v) 2.5 2.5 2.5 Digital Output 0000 0000 0000 0000 0000 0001 0000 0000 0010 | 0111 1111 1111 1000 0000 0000 1000 0000 0001 | 1111 1111 1101 1111 1111 1110 1111 1111 1111
BL8531H_ADC
RED Channel Input Full Scale=4V 1LSB=0.977mV REFTOP=3.5V REFBOT=1.5V
TIMING DIAGRAM
R_INP G_INP B_INP
A1 A2 A5 Input Sampling Period
CKIN
D[11:0]
D1
D2
D3
D4
D5
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FUNCTIONAL DESCRIPTION
BL8531H_ADC
1. The BL8531H_ADC is a CMOS four step pipelined Analog-to-Digital Converter. It contains 4-bit flash A/D Converters, three 3bit flash A/D converters and three multiplying D/A Convertors. The N-bit flash ADC is composed of 2N-1 latched comparators, and multiplying DAC is composed of 2*(2N+1) capacitors and two fully-differential amplifiers. 2. The BL8531H_ADC operates as follows. During the first "L" cycle of external clock the analog input data is sampled, and the input is held from the rising edge of the external clock, which is fed to the first 4-bit flash ADC, and the first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 4-bit ADC's output, and finally amplifies a residue voltage by 24. The second and third flash ADC, and MDAC are worked as same manner. Finally amplified residue voltage at the third multiplying DAC is fed to the last 3-bit flash ADC decides final 3-bit digital digital code. 3. BL8531H_ADC has the error correction scheme, which handles the output from mismatch in the first, second, third and fourth flash ADC.
MAIN BLOCK DESCRIPTION
1. SHA SHA (Sample-and-Hold Amplifier) is the circuit that samples the analog input signal and hold that value until next sample-time. It is good as small as its different value between analog input signal and output signal. SHA amp gain is higher than 70dB at 10MHz conversion rate, its settling-time must be shorten than 38ns with less than 1/2 LSB error voltage at 12bit resolution. This SHA is consist of fully differential op amp, switching tr. and sampling capacitor. The sampling clock is non-overlapping clock (Q1, Q2) and sampling capacitor value is about 4pF. SHA uses independent bias to protect interruption of any other circuit. SHA amp is designed that open-loop dc gain is higher than 70dB, phase margin is higher than 60 degrees. Its input block is designed to be the rail-to-rail architecture using complementary different pair. 2. FLASH The 4-bit flash converters compare analog signal (SAH output) with reference voltage, and that results transfer to MDAC and digital correction logic block. It is realized fully differential comparators of 15EA. Considering self-offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the reference voltage at the sampling capacitors before transferred SHA output.That operation is performed on the phase of Q2, and discharging on the phase of Q1. That is, the comparators compare relative different values dual input voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by Q1P. 3. MDAC MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of two stage op amp, selection logic and capacitor array (c_array). c_array's compositions are the capacitors to charge the analog input and and the reference voltage, switches to control the path. Selection logic controls the c_array internal switches. If Q1 is high, selection's output are all low, the switches of tsw1 are off, the switches of tsw2 are all on. Therefore the capacitors of c_array can charge analog input values held at SHA.
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CORE EVALUATION GUIDE
BL8531H_ADC
1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. If User want the specific analog input range, the reference voltages may be forced. vdda vssa vbb vddd vssd
R_INP R_INN G_INP G_INN B_INP B_INN
REDB GREENB BLUEB
bl8531h_adc
[MSB:LSB] D[11:0]
REFTOP
D[110]
D[11:0]
Digital Mux HOST DSP CORE D[110] Bidirectional PAD (ADC Function Test & externally forced Digital Input)
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USER GUIDE
1. Input Channel Select - REDB, GREENB, BLUEB - only 1 channel shoud be selected - for example for RED channel select : REDB=0, GREENB=1, BLUEB=1 2. Input Range (for example : RED channel) - If you want to using the single-ended input and RED channel is selected, you should use he input range as below. R_INP : 0.5V ~ 4.5V R_INN : 2.5V - If you want to using the differential input, you should use the input range as below. R_INP : 1.5V ~ 3.5V, R_INN : 1.5V ~ 3.5V. AINR : R_INP - R_INN - If you want to changing input range (AINR span), you can force reference voltages. AIN span = -REF ~ +REF REF = REFTOP - REFBOT
BL8531H_ADC
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PHANTOM CELL INFORMATION
BL8531H_ADC
- Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user.
Pin Name VDDA VSSA VBB VDDD B_INP B_INN G_INP G_INN R_INP VSSD R_INP R_INN G_INP G_INN B_INP B_INN CKIN BUEB GREENB REDB REFTOP REFBOT STBY REDB GREENB BLUEB DO[11] DO[10] DO[9] DO[8] DO[7] DO[6] DO[5] DO[10] STBY DO[11] VDDD VSSD DO[0] DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] DO[7] DO[8] DO[9] CKIN DO[4] DO[3] DO[2] DO[1] DO[0] VBB VSSA VBB VDDA VSSA VBB VDDA REFBOT REFTOP
Pin Usage External External External External External External/Internal External/Internal
Pin Layout Guide - Maintain the large width of lines as far as the pads. - place the port positions to minimize the length of power lines. - Do not merge the analog powers with anoter power from other blocks. - Use good power and ground source on board.
External/Internal - Do not overlap with digtal lines. External/Internal - Maintain the shotest path to pads. External/Internal External/Internal External/Internal - Separate from all other analog signals External/Internal - Maintain the larger width and the shorter length as far as the pads. External/Internal - Separate from all other digital lines. External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal - Separated from the analog clean signals if possible. - Do not exceed the length by 1,000um.
bl8531h_adc
12bit 10MSPS ADC
R_INN
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12BIT 10MSPS ADC
BL8531H_ADC
FEEDBACK REQUEST
It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much.
Characteristic
Analog Power Supply Voltage Digital Power Supply Voltage Bit Resolution Reference Input Voltage Analog Input Voltage Operating Temperature Integral Non-linearity Error Differential Non-linearity Error Bottom Offset Voltage Error Top Offset Voltage Error Maximum Conversion Rate Dynamic Supply Current Power Dissipation Signal-to-noise Ratio Pipeline Delay Digital Output Format (Provide detailed description & timing diagram)
Min
Typ
Max
Unit
V V Bit V Vpp C LSB LSB mV mV MSPS mA mW dB CLK
Remarks
1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any.
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HISTORY CARD
BL8531H_ADC
Version
ver 1.0 ver 1.1
Date
99.12 02.4.17
Modified Items
Original version published (preliminary) Phantom information added and the format changed
Comments
SEC ASIC
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MIXED

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