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LT1310 1.5A Boost DC/DC Converter with Phase-Locked Loop
FEATURES
s s s s
DESCRIPTIO
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Synchronizable or Constant Frequency Low Noise Output Synchronizable Up to 4.5MHz Wide Input Voltage Range: 2.8V to 18V Low Profile Surface Mount Solution (All Ceramic Capacitors) Low VCESAT Switch: 240mV at 1A Adjustable Output from VIN to 35V Small Thermally Enhanced 10-Lead MSOP Package
The LT(R)1310 boost DC/DC converter combines a 1.5A current mode PWM switcher with an integrated phaselocked loop, allowing the user to set the switching frequency anywhere from 10kHz to 4.5MHz. Intended for use in applications where switching frequency must be accurately controlled, the LT1310 can generate 12V at up to 400mA from a 5V input. Switching frequency is set with an external capacitor, and the device can be operated in either free-running or phaselocked mode. A wide capture range of nearly 2:1 allows the free-running frequency to be set using standard 10% tolerance NP0 dielectric capacitors. The LT1310 is available in the tiny thermally enhanced 10-lead MSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s s
Instruments Avionics Data Acquisition Communications Imaging Ultrasound
TYPICAL APPLICATIO
VIN 5V
L1 5.6H C1 4.7F CERAMIC LT1310 VIN SHDN SYNC PLL-LPF VC 3.01k 1500pF 15k 820pF CT GND* SW FB
D1
VOUT 12V 400mA 178k
90 85 80 75
SHUTDOWN SYNC 1.6MHz
20.5k
EFFICIENCY (%)
70 65 60 55 50 45 40 35 0 100 200 300 LOAD CURRENT (mA) 400
1310 F01b
100pF NP0
C2 4.7F CERAMIC
1310 F01a
C1: 4.7F, X5R OR X7R, 6.3V C2: 4.7F, X5R OR X7R, 16V D1: MICROSEMI UPS120 OR EQUIVALENT L1: PANASONIC ELL6SH-5R6M *EXPOSED PAD MUST ALSO BE GROUNDED
Figure 1. 5V to 12V Converter Synchronized at 1.6MHz
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LT1310 Efficiency
VOUT = 12V 3.3VIN 5VIN
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LT1310
ABSOLUTE
(Note 1)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW FB SHDN PLL-LPF SYNC GND 1 2 3 4 5 10 9 8 7 6 VC CT VIN SW SW
SW Voltage .............................................................. 36V VIN Voltage ............................................................. 18V SHDN Voltage ......................................................... 18V SYNC Voltage ........................................................... 5V FB Voltage ................................................................. 5V CT Voltage ................................................................. 5V VC Voltage ................................................................. 2V PLL-LPF Pin Current ............................................... 1mA Operating Temperature Range (Note 2) .. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1310EMSE MSE PART MARKING LTRZ
MSE EXPOSED PAD PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 40C/W EXPOSED PAD IS GROUND (MUST BE SOLDERED TO PCB)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER Undervoltage Lockout Maximum Input Voltage Feedback Voltage
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V, VSHDN = 3.3V, unless otherwise noted. (Note 2)
CONDITIONS MIN TYP MAX 2.8 18
q
UNITS V V V V nA %/V A/V V/V
1.242 1.236
1.255 60
1.268 1.268 150 0.05
FB Pin Bias Current Reference Line Regulation Error Amplifier Transconductance Error Amplifier Voltage Gain SW Current Limit SW Saturation Voltage SW Maximum Duty Cycle SW Minimum On Time VCO Frequency ISW = 1A CT = 220pF CT = 47pF ISW = 150mA, VC = 0.25V CT = 220pF, PLL-LPF = High CT = 220pF, PLL-LPF = High CT = 220pF, PLL-LPF = Low CT = 47pF, PLL-LPF = High CT = 220pF, PLL-LPF = High, FB = 0V CT = 220pF, Maximum CT = 220pF, Minimum (Percent Change from Max) SHDN = High SHDN = Low Switch Off, SW = 3.3V VSHDN = 2.4V Active Mode Shutdown Mode 2.4 0.950 -40
q
VIN = 2.9V to 18V I = 5A 1.5 80 78 0.950 0.800
0.01 350 200 2.1 0.240 84 83 70 1.10 500 3.3 200 1.10 -50 11.5 0.1 35
2.8 0.320
1.25 1.30 630
Frequency Foldback PLL Lock Range Supply Current SW Leakage Current SHDN Pin Bias Current SHDN Pin High SHDN Pin Low
1.25 15 1 5 65 0.4
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: The LT1310E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, chacterization and correlation with statistical process controls.
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A V % % ns MHz MHz kHz MHz kHz MHz % mA A A A V V
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LT1310 TYPICAL PERFOR A CE CHARACTERISTICS
Feedback Voltage
1.27
140 120
FEEDBACK CURRENT (nA)
1.26 FB VOLTAGE (V)
100 80 60 40 20
UNDERVOLTAGE LOCKOUT (V)
1.25
1.24
1.23
1.22 -50
-25
0 25 50 TEMPERATURE (C)
Oscillator Frequency vs CT Capacitor
6000 PLL-LPF = HIGH 2000
5000 FREQUENCY (kHz)
FREQUENCY (kHz)
4000
1200
FREQUENCY (kHz)
3000
2000
1000 20 40 80 60 CAPACITOR (pF) 100
LT1372 * G10
Oscillator Frequency 220pF Capacitor on CT Pin
1600 1400 PLL-LPF = HIGH
FREQUENCY (kHz)
FREQUENCY (kHz)
1200 1000 800 600 400 200 -50
3200 2900 2600 2300 2000 -50
MAX DUTY CYCLE (%)
-25
50 25 0 TEMPERATURE (C)
UW
75
1310 G01
Feedback Pin Current
2.80 2.75 2.70 2.65 2.60 2.55
Undervoltage Lockout
100
0 -50
-25
50 25 0 TEMPERATURE (C)
75
100
1310 G02
2.50 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1310 G03
Oscillator Frequency vs CT Capacitor
PLL-LPF = HIGH 1400 1200 1600 1000 800 600 400 200 0 100 0 300 700 500 CAPACITOR (pF) 900 1100
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Oscillator Frequency vs Feedback Voltage
220pF CT CAPACITOR
800
400
0
0.2
0.4
0.6 0.8 1.0 FEEDBACK (V)
1.2
1.4
1310 G06
Oscillator Frequency 47pF Capacitor on CT Pin
3800 3500
100
Maximum Duty Cycle vs Oscillator Frequency
PLL-LPF = HIGH
90 100C 25C 80 -50C 70
60
75
100
1310 G07
-25
0 25 50 TEMPERATURE (C)
75
100
1310 G08
50 500 1000 1500 2000 2500 3000 3500 4000 OSCILLATOR FREQENCY (kHz)
1310 G09
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LT1310 TYPICAL PERFOR A CE CHARACTERISTICS
Switch Minimum On Time
100 90 MINIMUM ON TIME (ns) 1400 1200
FREQUENCY (kHz)
80 70 60 50 40 -50
1000 800 600 MINIMUM 400 200 -50
FREQUENCY (kHz)
-25
0 25 50 TEMPERATURE (C)
Supply Current
12
400
11 SUPPLY CURRENT (mA)
VCESAT (mV)
10
9
8
7 -50
-25
Transient Response
VOUT 100mV/DIV IL 500mA/DIV 200mA ILOAD 100mA fSYNC = 1.5MHz 50s/DIV
LT1310 G16
4
UW
75
1310 G10
PLL Lock Range 220pF Capacitor on CT Pin
3500
PLL Lock Range 47pF Capacitor on CT Pin
MAXIMUM 3000
MAXIMUM
2500 2000 1500 1000 500 -50 MINIMUM
100
-25
0 25 50 TEMPERATURE (C)
75
100
1310 G11
-25
0 25 50 TEMPERATURE (C)
75
100
1310 G12
Switch VCESAT
300
200
100
0 25 50 TEMPERATURE (C)
75
100
1310 G13
0 0 0.5 1.0 SWITCH CURRENT (A) 1.5
1310 G15
PLL Response
VOUT 50mV/DIV IL 200mA/DIV fSYNC 1.9MHz 1.2MHz 50s/DIV
LT1310 G17
Start-Up Response
VOUT 5V/DIV IL 1A/DIV
VSHDN NO SYNC SIGNAL 20s/DIV f = 1.2MHz
LT1310 G18
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FB (Pin 1): Feedback Pin for Error Amplifier. Connect the resistor divider here to set output voltage according to the formula:
VOUT R1
VOUT = 1.255(1 + R1/R2)
R2
Minimize trace area at this pin. SHDN (Pin 2): Shutdown Pin. For active mode, tie this pin to a voltage between 2.4V and 18V. To disable the part and go into low current mode, pull this pin below 0.4V. PLL-LPF (Pin 3): Phase Locked-Loop Filter Pin. This is the output of the phase detector and also the input to the voltage controlled oscillator (VCO). Connect an RC filter here. Typically, R = 3k and C = 1500pF. The voltage range at the PLL-LPF pin is approximately 0V to 1.5V with 1.5V corresponding to the maximum switching frequency. For applications not requiring synchronization, use a pull-up resistor at this pin; the pull-up voltage must be above 2.4V. Set the pull-up resistor value according to:
RPULLUP =
( VPULLUP - 1.5V)
300A
For a pull-up voltage of 5V:
RPULLUP =
(5V - 1.5V) 11.6k
300A
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FB
SYNC (Pin 4): Frequency Synchronization Pin. Inject the external synchronizing signal here. The phase detector is edge triggered and when locked the rising edge of the sync signal will be aligned with the turn-on of the power transistor. The SYNC signal must have a minimum HIGH amplitude of 1.2V and a maximum LOW amplitude of 0.2V with the signal staying low for at least 100ns.
1.2V (MIN) 0.2V (MAX) 100ns (MIN)
GND (Pin 5, Exposed Pad): Ground. Tie both Pin 5 and the exposed pad directly to local ground plane. The ground metal to the exposed pad should be wide for better heat dissipation. Multiple vias (local ground plane ground backplane) placed close to the exposed pad can further aid in reducing thermal resistance. The exposed pad must be soldered to ground for the LT1310 to function properly. SW (Pins 6, 7): Switch Pin. Connect inductor/diode here. Minimize trace area at this pin to keep EMI down. VIN (Pin 8): Supply Pin. Must be bypassed as close as possible to the pin. CT (Pin 9): Timing Capacitor Pin for VCO. Place the timing capacitor from this pin to ground to set the frequency range for the oscillator. Minimize trace at this pin to reduce stray capacitance. VC (Pin 10): Compensation Pin for Error Amplifier. Tie an RC network here to compensate the voltage feedback loop.
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LT1310
BLOCK DIAGRA
FB 1
1.255V REF
SHDN 2 GND 5 EXPOSED PAD x5 SHUTDOWN
OPERATIO
To understand operation, refer to the Block Diagram. The LT1310 contains a boost switching regulator that can be phase locked to an external synchronizing signal. The boost regulator uses current mode control and contains a 1.5A NPN power transistor. This type of control uses two feedback loops. The main control loop sets output voltage and operates as follows: a load step causes VOUT and the FB voltage to be slightly perturbed. The error amplifier A1 responds to this change in FB by driving the VC pin either higher or lower. Because switch current is proportional to the VC pin voltage, this change causes the switch current to be adjusted until VOUT is once again satisfied. Loop compensation is taken care of by an RC network from the VC pin to ground. Inside this main loop is another that sets current limit on a cycle-by-cycle basis. This loop utilizes current comparator A2 to control peak current. The oscillator issues a set pulse to the flip-flop at the beginning of each cycle, turning the switch on. With the switch now in the ON state, the SW pin is effectively connected to ground. Current ramps up in the inductor linearly at a rate of VIN/L. Switch current is set by the VC pin voltage and
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VC 10 CT 9 PLL-LPF 3 SYNC
+ +
A2
-
A1
RAMP GEN.
VCO
PHASE DETECTOR
4
-
+ +
S R
Q Q SW 6, 7
0.024
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when the voltage across RSENSE trips the current comparator, a reset pulse will be generated and the switch will be turned off. Since the inductor is now loaded up with current, the SW pin will fly high until it is clamped by the catch diode, D1. Current will flow through the diode decreasing at a rate of (VOUT - VIN)/L until the oscillator issues a new set pulse, causing the cycle to repeat. The LT1310 is phase lockable up to 4.5MHz, giving the user precise control over switching frequency. The phase detector compares the incoming sync signal to the internal oscillator signal. If the switching frequency is lower than the sync signal, or if the phase lags the sync signal, then the phase detector output will source current into the PLL-LPF pin, driving it higher. The PLL-LPF pin is also the input to the voltage controlled oscillator. If the sync signal is slower than the switching frequency, the PLL-LPF pin will sink current until the PLL-LPF pin voltage drops. When locked, the PLL-LPF pin rests at a voltage between 0V and 1.5V. The PLL-LPF pin is capable of sinking or sourcing approximately 140A.
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LT1310
OPERATIO
CT Selection for Operating Frequency To synchronize to an external input signal, the timing capacitor and PLL filter components must be chosen properly. This is a simple process and can be done using the graph in Figure 2a. In Figure 2a, operating frequency is plotted versus timing capacitor (CT) with the upper and lower lines corresponding to the minimum and maximum lock frequency given a specific CT value. To choose the right timing capacitor, find the intersection of the desired operating frequency and the dashed line. Then move to the corresponding CT value. Alternately, use the following equations as a starting point: for fLOCK 2MHz:
250 * 10 - 6 CT = 0.75 - 40 * 10 -12 fLOCK
for fLOCK 2MHz:
310 * 10 -6 CT = 0.75 - 60 * 10 -12 fLOCK
100k
10k
CT VALUE (pF)
1k MINIMUM LOCK FREQUECY 100
10 10k
Figure 2a. CT vs Operating Frequency
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Because the lock range for the PLL is nearly 2:1, the nearest standard value NP0 capacitor can be used. For the application shown in Figure 1, a 1.6MHz switching frequency corresponds to an 100pF timing capacitor. Since the switching frequency affects inductor ripple current, the inductor must also be scaled. Table 1 shows recommended component values for various switching frequencies.
Table 1. Recommended Component Values for Various Switching Frequencies (RLP = 3.01k)
SWITCHING FREQUENCY 600kHz 1MHz 1.6MHz 2MHz 2.5MHz 3MHz CT 330pF 180pF 100pF 68pF 47pF 33pF CC 1500pF 1000pF 820pF 820pF 330pF 330pF CLP 2700pF 2200pF 1500pF 1500pF 1500pF 1000pF RC 10k 10k 15k 15k 20k 20k L1 10H 6.2H 5.6H 4.7H 3.3H 2.7H
VIN 5V L1 C1 4.7F CERAMIC LT1310 178k VIN SHDN SYNC PLL-LPF VC RLP CLP
1M 100k FREQUENCY (Hz) 10M
1310 F02a
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VOUT 12V SW FB 20.5k
MAXIMUM LOCK FREQUECY
SHUTDOWN SYNC IN
CT GND
RC CC
CT
C2 4.7F CERAMIC
Figure 2b. Circuit Used for CT Selection
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LT1310
APPLICATIO S I FOR ATIO
Inductor Selection
Several inductors that work well with the LT1310 are listed in Table 2. This table is not exclusive; there are many other manufacturers and inductors that can be used. Consult each manufacturer for more detailed information and for their entire selection of related parts, as many different sizes and shapes are available. Ferrite core inductors should be used to obtain the best efficiency, as core losses at high frequency are much lower for ferrite cores than for the cheaper powdered-iron ones. Choose an inductor that can handle at least 1.5A without saturating, and ensure that the inductor has a low DCR (copper wire resistance) to minimize I2R power losses. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor only carries one-half of the total switch current. Switching frequency will also affect inductor requirements with higher frequencies corresponding to lower inductance values. A good starting point is to set the inductor ripple current equal to one-third of the peak switch current. The inductors shown in Table 2 were chosen for small size. For better efficiency, use similar valued inductors with a larger volume.
Table 2. Recommended Inductors
MAX L DCR (H) (m) 4.1 5.4 5.3 6.2 8.2 2.2 3.3 4.7 5.6 6.8 4.7 1.5 2.7 4.7 10 1.2 2.2 57 76 38 45 53 71 86 50 59 62 45 25 33 45 67 80 120 SIZE LxWxH (mm) 5.7 x 5.7 x 2 5.7 x 5.7 x 3 4.5 x 4 x 3.2 6.4 x 6 x 3 Panasonic (408) 945-5660 www.panasonic.com
PART CDRH5D18-4R1 CDRH5D18-5R4 CDRH5D28-5R3 CDRH5D28-6R2 CDRH5D28-8R2 CR43-2R2 CR43-3R3 ELL6SH-4R7M ELL6SH-5R6M ELL6SH-6R8M RLF5018T-4R7M1R4 RLF5018-1R5M2R1 RLF5018-2R7M1R8 RLF5018-4R7M1R4 RLF5018-100MR94 LPO1704-122MC LPO1704-222MC
VENDOR Sumida (847) 956-0666 www.sumida.com
5.6 x 5.2 x 1.8 TDK 5.2 x 5.6 x 1.8 (847) 803-6100 www.tdk.com
5.5 x 6.6 x 1
Coilcraft (800) 322-2645 www.coilcraft.com
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Capacitor Selection Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have an extremely low ESR and are available in very small packages. X5R dielectrics are preferred, followed by X7R, as these materials retain the capacitance over wide voltage and temperature ranges. A 4.7F to 20F output capacitor is sufficient for most applications, but systems with very low output currents may need only a 1F or 2.2F output capacitor. Solid tantalum or OS-CON capacitors can be used, but they will occupy more board area than a ceramic and will have a higher ESR. Always use a capacitor with a sufficient voltage rating. Ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as close as possible to the LT1310. A 2.2F to 4.7F input capacitor is sufficient for most applications. Table 3 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts.
Table 3. Ceramic Capacitor Manufacturers
Taiyo Yuden AVX Murata (408) 573-4150 www.t-yuden.com (803) 448-9411 www.avxcorp.com (714) 852-2001 www.murata.com
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Compensation--Adjustment To compensate the feedback loop of the LT1310, a series resistor-capacitor network should be connected from the VC pin to GND. For most applications, a capacitor in the range of 220pF to 1500pF will suffice. With a switching frequency of 1.6MHz, a good starting value for the compensation capacitor, CC, is 820pF. The compensation resistor, RC, is usually in the range of 5k to 30k. A good technique to compensate a new application is to use a 30k potentiometer in place of RC, and use a 820pF capacitor for CC. By adjusting the potentiometer while observing the transient response, the optimum value for RC can be found. Figures 3a to 3c illustrate this process for the circuit of Figure 1 with a load current stepped from
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LT1310
APPLICATIO S I FOR ATIO
VOUT 100mV/DIV AC COUPLED
IL 0.5A/DIV RC = 3k 200s/DIV
1310 F03a
Figure 3a. Transient Response Shows Excessive Ringing
VOUT 100mV/DIV AC COUPLED
IL 0.5A/DIV RC = 6k 200s/DIV
1310 F03b
Figure 3b. Transient Response is Better
VOUT 100mV/DIV AC COUPLED
IL 0.5A/DIV RC = 15k 200s/DIV
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Figure 3c. Transient Response is Well Damped
100mA to 200mA. Figure 3a shows the transient response with RC equal to 3k. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 3b, the value of R C is increased to 6k, which results in a more damped response. Figure 3c shows the results when RC is increased further to 15k. The transient response is nicely damped and the compensation procedure is complete. Compensation--Theory Like all other current mode switching regulators, the LT1310 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT1310: a
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fast current loop which does not require compensation, and a slower voltage loop which does. Standard Bode plot analysis can be used to understand and adjust the voltage feedback loop. As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 4 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by the equivalent transconductance amplifier gmp. gmp acts as a current source where the output current is proportional to the VC voltage. Note that the maximum output current of gmp is finite due to the current limit in the IC. From Figure 4, the DC gain, poles and zeroes can be calculated as follows: 2 2 * * RL * COUT 1 Error Amp Pole: P2 = 2 * * RO * CC 1 Error Amp Zero: Z1= 2 * * RC * CC 1.25 DC Gain: A = * gma * RO * gmp * RL VOUT Output Pole: P1= In addition to the elements from Figure 4, current mode control aslo results in some other poles and zeroes. These are as follows: RHP Zero: Z2 = VIN2 * RL 2 * * VOUT2 * L 1 Output Zero: Z3 = 2 * * ESR * COUT f Current Mode Pole: P3 > S 3 The Current Mode zero is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection.
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LT1310
APPLICATIO S I FOR ATIO
-
gmp
COUT
VC RC CC RO
+
gma
1.255V REFERENCE R1 FB R2
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GAIN (dB) 0 -50 100
-
CC: COMPENSATION CAPACITOR COUT: OUTPUT CAPACITOR gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER RC: COMPENSATION RESISTOR RL: OUTPUT RESISTANCE DEFINED AS VOUT DIVIDED BY ILOAD(MAX) RO: OUTPUT RESISTANCE OF gma R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK
Figure 4. Boost Converter Equivalent Model
PHASE (DEG)
Using the circuit of Figure 1 as an example, the following table shows the parameters used to generate the Bode plot shown in Figure 5.
Table 4. Bode Plot Parameters
PARAMETER RL COUT RO CC RC VOUT VIN gma gmp L fS ESR VALUE 30 4.7 2 820 15 12 5 500 1.5 5.6 1.6 10 UNITS F M pF k V V mho mho H MHz m COMMENT Application Specific Application Specific Not Adjustable Adjustable Adjustable Application Specific Application Specific Not Adjustable Not Adjustable Application Specific Adjustable Not Adjustable
From Figure 5, the phase is 120 when the gain reaches 0dB giving a phase margin of 60. This is more than adequate. The crossover frequency is 50kHz, which is about three times lower than the frequency of the right half plane zero Z2. It is important that the crossover frequency be at least three times lower than the frequency of the RHP zero to achieve adequate phase margin.
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VOUT RL
50
+
1k
10k 100k FREQUENCY (Hz)
1M
1310 F05a
0
-100
60 -180 -200 100 1k 10k 100k FREQUENCY (Hz) 1M
1946 F05b
Figure 5. Bode Plot of Figure 1's Circuit
Diode Selection A Schottky diode is recommended for use with the LT1310. The Microsemi UPS120 is a very good choice. Where the input to output voltage differential exceeds 20V, use the UPS140 (a 40V diode). These diodes are rated to handle an average forward current of 1A. For applications where the average forward current of the diode is less than 0.5A, an ON Semiconductor MBR0520 diode can be used. Setting Output Voltage To set the output voltage, select the values of R1 and R2 (see Figure 1) according to the following equation: V R1 = R2 OUT - 1 1.255V A good range for R2 is from 5k to 30k.
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LT1310
APPLICATIO S I FOR ATIO
Layout Hints
The high speed operation of the LT1310 demands careful attention to board layout. You will not get advertised
CC
R1
SHDN SYNC SW RLP COUT CLP MULTIPLE VIAS
Figure 6. Recommended Component Placement for Boost Converter. Note Direct High Current Paths Using Wide PC Traces. Minimize Trace Area at Pin 10 (VC), Pin 9 (CT) and Pin 1 (FB). Use Multiple Vias to Tie Pin 5 Copper and the Exposed Pad to Ground Plane. Use Vias at One Location Only to Avoid Introducing Switching Currents Into the Ground Plane
PACKAGE DESCRIPTIO
(Reference LTC DWG # 05-08-1663)
3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF BOTTOM VIEW OF EXPOSED PAD OPTION 1 2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004)
4.90 0.15 (1.93 .006) 0.254 (.010) GAUGE PLANE 0.53 0.01 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 1.10 (.043) MAX DETAIL "A" 0 - 6 TYP 12345
0.17 - 0.27 (.007 - .011) TYP
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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performance with careless layout. Figure 6 shows the recommended component placement for a boost converter.
RC VIN CIN R2 CT LT1310 L1 D1 GND VOUT
1310 F06
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MSE Package 10-Lead Plastic MSOP
3.00 0.102 (.118 .004) NOTE 4
10 0.86 (.034) REF 2.794 0.102 (.110 .004)
0.889 0.127 (.035 .005)
0.50 (.0197) BSC
0.13 0.076 (.005 .003)
5.23 (.206) MIN
2.083 0.102 3.2 - 3.45 (.082 .004) (.126 - .136)
MSOP (MSE) 0802
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
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LT1310
TYPICAL APPLICATIO
VIN 5V C1 2.2F SHUTDOWN SYNC IN 3MHz RLP 3.01k CLP 1000pF VIN SHDN SYNC PLL-LPF VC RC 10k CC 680pF CT GND* CT 33pF NP0 C2 2.2F L1 3.3H LT1310 SW FB R2 20.5k
3MHz 5V to 12V Converter
D1 VOUT 12V 400mA
90 85 80 75
EFFICIENCY (%)
C1, C2: TAIYO YUDEN LMK212BJ225MG D1: MOTOROLA MBRM120 L1: PANASONIC ELL6RH2R7M *EXPOSED PAD MUST ALSO BE GROUNDED
RELATED PARTS
PART NUMBER LT1613 LT1618 LT1946/LT1946A LT1961 DESCRIPTION 550mA (ISW), 1.4MHz High Efficiency Step-Up DC/DC Converter 1.5A (ISW), 1.25MHz, High Efficiency Step-Up DC/DC Converter 1.5A (ISW), 1.2/2.7MHz, High Efficiency Step-Up DC/DC Converters 1.5A (ISW), 1.25MHz, High Efficiency Step-Up DC/DC Converter COMMENTS 90% Efficiency, VIN: 0.9V to 10V, VOUT(MAX): 34V, IQ: 3mA, ISD: <1A, ThinSOTTM Package 90% Efficiency, VIN: 1.6V to 18V, VOUT(MAX): 35V, IQ: 1.8mA, ISD: <1A, 10-Lead MS Package VIN: 2.45V to 16V, VOUT(MAX): 34V, IQ: 3.2mA, ISD: <1A, MS8 Package 90% Efficiency, VIN: 3V to 25V, VOUT(MAX): 35V, IQ: 0.9mA, ISD: 6A, MS8E Package 92% Efficiency, VIN: 0.85V to 5V, VOUT(MAX): 5V, IQ: 19A/300A, ISD: <1A, ThinSOT Package 97% Efficiency, VIN: 0.5V to 5V, VOUT(MAX): 6V, IQ: 38A, ISD: <1A, 10-Lead MS Package 97% Efficiency, VIN: 0.5V to 5V, VOUT(MAX): 6V, IQ: 38A, ISD: <1A, 10-Lead MS Package
LTC(R)3400/LTC3400B 600mA (ISW), 1.2MHz, Synchronous Step-Up DC/DC Converters LTC3401 LTC3402 1A (ISW), 3MHz, Synchronous Step-Up DC/DC Converter 2A (ISW), 3MHz, Synchronous Step-Up DC/DC Converter
ThinSOT is a trademark of Linear Technology Corporation.
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
Efficiency
5VIN
R1 178k
3.3VIN
70 65 60 55 50 45 40 35 0 100 200 300 LOAD CURRENT (mA) 400
1310 TA01b
1310 TA01a
1310f LT/TP 0103 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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