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INTEGRATED CIRCUITS
DATA SHEET
TDA1312A; TDA1312AT Stereo continuous calibration DAC (CC-DAC)
Preliminary specification File under Integrated Circuits, IC01 July 1993
Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
FEATURES * 8 x oversampling (simultaneous input) possible * Voltage output * Space saving package SO8 or DIL8 * Low power consumption * Wide dynamic range (16-bit resolution) * Continuous Calibration (CC) concept * Easy application: - single 4 to 5.5 V rail supply - output current and bias current are proportional to the supply voltage - integrated current-to-voltage converter * Internal bias current ensures maximum dynamic range * Wide operating temperature range (-40 C to + 85 C) * Compatible with most current Japanese input formats: time multiplexed, two's complement and TTL * No zero-crossing distortion * Cost efficient. ORDERING INFORMATION
TDA1312A; TDA1312AT
GENERAL DESCRIPTION The TDA1312A; 1312AT is a voltage driven D/A converter and is a device of a new generation of digital-to-analog converters which embodies the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated by one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy insensitive to ageing, temperature matching and process variations. The TDA1312A; 1312AT is fabricated in a 1.0 m CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment.
PACKAGE EXTENDED TYPE NUMBER PINS TDA1312A(1) TDA1312AT(2) Notes 1. SOT97-1; 1996 August 14. 2. SOT96-1; 1996 August 14. 8 8 PIN POSITION DIL SO8 MATERIAL plastic plastic CODE SOT97DE SOT96AG
July 1993
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Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
QUICK REFERENCE DATA SYMBOL VDD IDD VFS (THD+N)/S PARAMETER supply voltage supply current full scale output voltage VDD = 5 V; at code 0000H VDD = 5 V CONDITIONS
TDA1312A; TDA1312AT
MIN. 4 - 1.8 - - - - - - 86 - - - - 5
TYP. 3.4 2.0 -68 0.04 -30 3 -33 2 92 0.2 - - 400
MAX. 5.5 6.0 2.2 -63 0.07 -24 6 - - - - 18.4 18.4 - V
UNIT mA V dB % dB % dB % dB s Mbits/s MHz ppm
total harmonic distortion plus at 0 dB signal level noise at -60 dB signal level at -60 dB signal level; A-weighted
S/N tCS BR fBCK TCFS
signal-to-noise ratio at bipolar zero current settling time to 1 LSB input bit rate at data input clock frequency at clock input full scale temperature coefficient at analog outputs (IOL; IOR) operating ambient temperature total power dissipation
A-weighted; at code 0000H
Tamb Ptot
-40 VDD = 5 V; at code 0000H -
- 17
+85 30
C mW
July 1993
3
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handbook, full pagewidth
Philips Semiconductors
Stereo continuous calibration DAC (CC-DAC)
LEFT INPUT REGISTER LEFT OUTPUT REGISTER VOL 6 I/V IOL 11-BIT PASSIVE DIVIDER 32 (5-BIT) CALIBRATED CURRENT SOURCES 1 CALIBRATED SPARE SOURCE LEFT BIT SWITCHES
RIGHT INPUT REGISTER RIGHT OUTPUT REGISTER 7 RIGHT BIT SWITCHES I/V IOR 32 (5-BIT) CALIBRATED CURRENT SOURCES 1 CALIBRATED SPARE SOURCE 11-BIT PASSIVE DIVIDER VOR
4
BCK DATAR DATAL WS 1 2 3 8 CONTROL AND TIMING
REFERENCE SOURCE
TDA1312A TDA1312AT
4 C2
5
VDD
TDA1312A; TDA1312AT
GND
100 nF
MGE225
Preliminary specification
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
PINNING SYMBOL BCK DATAR DATAL GND VDD VOL VOR
WS
TDA1312A; TDA1312AT
PIN 1 2 3 4 5 6 7 8
DESCRIPTION bit clock input right data input left data input ground positive supply voltage left channel output right channel output word select input connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents. The TDA1312A; AT (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs.4 and 5. Data is placed in the right and left input registers (see Fig.1). The data in the input registers is simultaneously latched in the output registers which control the bit switches. An internal offset voltage VOFF is added to the full scale output voltage VFS; VOFF and VFS are proportional to VDD: Where VDD1/VDD2 = VFS1/VFS2 = VOFF1/VOFF2.
handbook, halfpage
BCK DATAR DATAL GND
1 2
8 7
WS VOR VOL VDD
TDA1312 3 TDA1312AT 6
4
MGE224
5
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value Iref, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the OUT terminal. The 32 current sources and the spare current source of the TDA1312A; AT are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is
July 1993
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Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
TDA1312A; TDA1312AT
handbook, halfpage
OUT IREF S2
OUT IREF S2 IREF
S1 + Cgs M1 Vgs
S1 + Cgs M1 Vgs
(a)
(b)
MGE226
Fig.3 Calibration principle; (a) calibration (b) operation.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Tstg TXTAL Tamb Ves supply voltage storage temperature maximum crystal temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1500 ; 3 zaps positive and negative. 2. Machine model: C = 200 pF; L = 0.5 H; R = 10 ; 3 zaps positive and negative. THERMAL RESISTANCE SYMBOL Rth j-a DIL8 SO8 PARAMETER from junction to ambient in free air 100 K/W 210 K/W THERMAL RESISTANCE PARAMETER CONDITIONS - -55 - -40 -2000 -200 MIN. MAX. 6.0 +150 +150 +85 +2000 +200 V C C C V V UNIT
July 1993
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Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
CHARACTERISTICS VDD = 5 V; Tamb = 25 C; measured in Fig.1; unless otherwise specified. SYMBOL Supply VDD IDD IIL IIH fBCK BR fWS tr tf tCY tBCKH tBCKL tSU;DAT tHD:DAT tHD:WS tSU;WS positive supply voltage supply current at code 0000H PARAMETER CONDITIONS
TDA1312A; TDA1312AT
MIN.
TYP.
MAX.
UNIT
4.0 - - - - - - - - 54 15 15 12 2 2 12
5.0 3.4 - - - - - - - - - - - - - -
5.5 6.0
V mA A A MHz Mbits/s kHz
Digital inputs; pins WS, BCK and DATA input leakage current LOW input leakage current HIGH clock frequency bit rate data input word select input frequency VI = 0 V VI = 5 V 10 10 18.4 18.4 384
Timing (see Fig.4) rise time fall time bit clock cycle time bit clock pulse width HIGH bit clock pulse width LOW data set-up time data hold time to bit clock word select hold time word select set-up time 12 12 - - - - - - - ns ns ns ns ns ns ns ns ns
Analog outputs; pins VOL and VOR VFS TCFS VOFF (THD+N)/S full-scale voltage full-scale temperature coefficient offset voltage total harmonic distortion plus noise at code 1000H at 0 dB signal level; note 1 1.8 - 0.42 - - 2.0 400 0.47 -68 0.04 -30 3 -33 2 -65 0.05 2.2 - 0.52 -63 0.07 -24 6 - - -61 0.09 V ppm V dB % dB % dB % dB %
at -60 dB signal level; - note 1 - at -60 dB signal level; - A-weighted; note1 - at 0 dB signal level; f = 20 Hz to 20 kHz - -
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Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
SYMBOL PARAMETER CONDITIONS
TDA1312A; TDA1312AT
MIN.
TYP.
MAX.
UNIT
Analog outputs; pins VOL and VOR tcs IO td S/N Note 1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz. current settling time to 1 LSB channel separation unbalance between outputs time delay between outputs signal-to-noise ratio at bipolar zero A-weighted; at code 0000H note 1 - 75 - - 86 0.2 80 0.2 0.2 92 - - 0.3 - - s dB dB s dB
handbook, full pagewidth
LEFT
WS RIGHT tHD; WS >2 >12 tSU; WS
tr <12 BCK
tBCKH >15
tf <12
tBCKL >15
tCY >54
tSU; DAT >12
tHD; DAT >2
DATAR DATAL
LSB
MSB
MGE227
SAMPLE OUT
Fig.4 Input signals timing.
July 1993
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DATAR DATAL MSB BCK
Philips Semiconductors
handbook, full pagewidth
Stereo continuous calibration DAC (CC-DAC)
LSB
9
WS
MGE228
SAMPLE OUT
TDA1312A; TDA1312AT
Preliminary specification
Fig.5 Input signals format.
Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil)
TDA1312A; TDA1312AT
SOT97-1
D seating plane
ME
A2
A
L
A1
c Z e b1 wM (e 1) b2 5 MH
b 8
pin 1 index E
1
4
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001AN EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
July 1993
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Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
TDA1312A; TDA1312AT
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024
0.028 0.004 0.012
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-05-22
July 1993
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Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TDA1312A; TDA1312AT
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Stereo continuous calibration DAC (CC-DAC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1312A; TDA1312AT
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
July 1993
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