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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
MCM67Q909
512K x 9 Bit Separate I/O Synchronous Fast Static RAM
The MCM67Q909 is a 4M-bit static random access memory, organized as 512K words of 9 bits. It features separate TTL input and output buffers, which drive 3.3 V output levels, and incorporates input and output registers on-board with high speed SRAM. It also features transparent-write and data pass-through capabilities. The synchronous design allows for precise cycle control with the use of an external single clock (K). The addresses (A0 - A18), data input (D0 - D8), data output (Q0 - Q8), write-enable (W), chip-enable (E), and output-enable (G), are registered on the rising edge of clock (K). The control pins (E, W, G) function differently in comparison to most synchronous SRAMs. This device will not deselect with E high. The RAM remains active at all times. If E is registered high, the output pins (Q0 - Q8) will be driven if G is registered low. The transparent write feature allows the output data to track the input data. E, G, and W must be asserted to perform a transparent write (write and pass-through). The input data is available at the ouputs on the next rising edge of clock (K). The pass-through function is always enabled. E high disables the write to the array while allowing a pass-through cycle to occur on the next rising edge of clock (K). Only a registered G high will three-state the outputs. The MCM67Q909 is available in an 86-bump surface mount PBGA (Plastic Ball Grid Array) package. * * * * * * * * * * * * Single 5 V 5% Power Supply Fast Cycle Time: 12 ns Max Single Clock Operation TTL Input and Output Levels (Outputs LVTTL Compatible) Address, Data Input, E, W, and G Registers On-Chip 83 MHz Maximum Clock Cycle Time Self-Timed Write Separate Data Input and Output Pins Transparent-Write and Pass-Through High Output Drive Capability: 50 pF/Output at Rated Access Time Boundary Scan Implementation PBGA Package for High Speed Operation
86 BUMP PBGA CASE 896A-02
PIN NAMES
A0 - A18 . . . . . . . . . . . . . . . . . Address Input E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable D0 - D8 . . . . . . . . . . . . . . . . . . . . Data Inputs Q0 - Q8 . . . . . . . . . . . . . . . . . . Data Outputs K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input SCK . . . . . . . . . . . . . . . . . . Scan Clock Input SE . . . . . . . . . . . . . . . . . . . . . . . Scan Enable SDI . . . . . . . . . . . . . . . . . . . . Scan Data Input SDO . . . . . . . . . . . . . . . . . Scan Data Output VCC . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connection
PIN ASSIGNMENT
1 A B C D E F G H J K A16 D7 VSS D5 VCC D3 VSS Q1 2 E A14 3 W G 4 VCC K 5 6 7 A4 A2 8 A0 VSS D8 Q8 Q6 VSS D6 9
SDI SDO VSS A6
A15 A17 Q7 VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS Q5 Q3 D1 A12 A13
VSS VSS VSS VSS VSS VCC D4 D2 D0 A1 A3 Not to Scale Q4 Q2 VSS Q0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A18 VSS A10 VSS VSS VSS VSS A9 A8 SE A5 A7
A11 SCK VCC TOP VIEW 86-BUMP
This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 3 12/23/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM67Q909 1
BLOCK DIAGRAM
A0 - A18 SH BSR D0 - D8 SH BSR E SH BSR G SH BSR W SH BSR K SH BSR * * SDI SE
REG
DECODERS
MEMORY ARRAY 512K x 9 ARRAY
SH BSR
REG
SENSE AMPS AND WRITE DRIVERS
MUX 2:1
OUTPUT REGISTER
Q0 - Q8
REG
WRITE PULSE GENERATOR
REG
REG
SE 1 L LM LS BYPASS SDO O *
I I
0 SCK
SCK * I SCK
SCK
NOTES: 1. Bypass mode is entered with SE low and SCK cycled. 2. SH BSR = shadow bypass scan register. 3. 41 bumps used in boundary scan. VSS, VCC, NC, SDI, SDO, SE, and SCK not used in scan path. 4. SDO output sequence: A6, A4, A2, A0, D8, Q8, D6, Q6, D4, Q4, D2, Q2, D0, Q0, A18, A1, A3, A5, A7, A8, A9, A10, A11, A12, A13, Q1, D1, Q3, D3, Q5, D5, Q7, D7, A15, A16, A14, A17, E, G, W, K. * Four added test pins.
MCM67Q909 2
MOTOROLA FAST SRAM
TRUTH TABLE
E (tn) L W (tn) L H L H L H L X H H Read Don't Care Pass-Through Read Don't Care Don't Care G (tn + 1) L Mode Write and Pass-Through Write Pass-Through D0 - D8 (tn) Valid Valid Valid Q0 - Q8 (tn + 1) D0 - D8 (tn) High-Z D0 - D8 (tn) High-Z Qout (tn) High-Z VCC Current ICC ICC ICC ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature -- Plastic Symbol VCC Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 1.7 - 10 to + 85 0 to + 70 - 55 to + 125 Unit V V mA W C C C This is a synchronous device. All synchronous inputs must meet specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) AC Supply Current (Iout = 0 mA) (VCC = max, f = fmax) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) MCM67Q909-12 ns Symbol VCC VIH VIL Ilkg(I) Ilkg(O) ICCA VOL VOH Min 4.75 2.2 - 0.5* -- -- -- -- 2.4 Max 5.25 VCC + 0.3** 0.8 1.0 1.0 230 0.4 3.3 Unit V V V A A mA V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
MOTOROLA FAST SRAM
MCM67Q909 3
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Address and Data Input Capacitance Control Pin Input Capacitance Output Capacitance Symbol Cin Cin Cout Max 6 6 8 Unit pF pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3 and 4)
MCM67Q909-12 Parameter P Cycle Time Clock Access Time Clock Low Pulse Width Clock High Pulse Width Clock High to Data Output Invalid Clock High to Data Output High-Z Setup Times: A W E G D0 - D8 A W E G D0 - D8 Symbol S bl tKHKH tKHQV tKLKH tKHKL tKHQX tKHQZ tAVKH tWVKH tEVKH tGVKH tDVKH tKHAX tKHWX tKHEX tKHGX tKHDX Min 12 -- 4 4 2 -- 3 Max -- 5 -- -- -- 5 -- Unit Ui ns ns ns ns ns ns ns 3 4 Notes N 1 2
Hold Times:
2
--
ns
4
NOTES: 1. All read and write cycles are referenced from K. 2. Valid data from clock high will be the data stored at the address or the last valid read cycle. 3. Measured at 200 mV from steady state. 4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected.
RL = 50 OUTPUT Z0 = 50 VL = 1.5 V
Figure 1. AC Test Load
MCM67Q909 4
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
READ CYCLE TIMING
tKHKH tKLKH tKHKL A (n) tKHWX tWVKH A (n + 1) A (n + 2) A (n + 3) A (n + 4) tKHGX tGVKH tKHQX Q (n - 2) Q (n - 1) tKHQV tKHQZ Q (n) tKHQX tKHQZ Q (n + 2)
K
tKHAX
tAVKH
A
W
tKHEX
tEVKH
E
G
Q
MCM67Q909 5
MCM67Q909 6
COMBINATION READ/WRITE CYCLE TIMING
WRITE D (n + 1) t KHKH t KLKH tKHKL INITIATE READ INITIATE READ WRITE D (n + 5) WRITE D (n + 3) INITIATE READ A (n) t KHWX t WVKH A (n + 1) A (n + 2) A (n + 3) A (n + 4) A (n + 5) A (n + 6) tKHEX t EVKH tKHGX tGVKH tKHQZ Q (n) tKHQV tKHQX t DVKH D (n + 1) D (n + 3) t KHDX D (n + 5) Q (n + 2) Q (n + 4)
INITIATE READ
K
t KHAX
t AVKH
A
W
E
G
tKHQX
Q
MOTOROLA FAST SRAM
D
TRANSPARENT-WRITE AND PASS-THROUGH CYCLE TIMING
WRITE WITH PASS-THROUGH tKHKH tKLKH tKHKL
MOTOROLA FAST SRAM
WRITE WITH PASS-THROUGH WRITE (TRANSPARENT-WRITE OUTPUTS HIGH-Z) PASS-THROUGH (NO WRITE) tKHAX A (n) tKHWX tWVKH A (n + 1) A (n + 2) A (n + 3) A (n + 4) NO WRITE NO WRITE tKHGX tGVKH tKHQX Q (n - 2) Q (n - 1) tKHQV tKHQZ D (n) tKHQX tKHQZ D (n + 2) D (n) D (n + 1) D (n + 2) D (n + 3) D (n + 4)
K
tAVKH
A
W
tKHEX
tEVKH
E
G
Q
tKHDX
tDVKH
MCM67Q909 7
D
BOUNDARY SCAN CYCLE TIMING
MCM67Q909-12 Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Scan Mode Setup Time Bypass Mode Setup Time Scan Mode Recovery Time SCK Low to SE Hold High SE High to SCK High Setup SCK High to SE Low Hold Time SDI Valid to SCK High Setup SCK High to SDI Don't Care SCK Low to SDO Valid Symbol S bl tCHCH2 tCHCL2 tCLCH2 tSS tBS tSR tCLMH tMHCH tCHML tIVCH tCHIX tCLOV Min 100 40 40 10 10 100 10 10 10 10 10 -- Max -- -- -- -- -- -- -- -- -- -- -- 20 Unit Ui ns ns ns ns ns ns ns ns ns ns ns ns 1 2 3 4 5 6 Notes N
NOTES: 1. The minimum delay required between ending normal operation and beginning scan operations. 2. The minimum delay required between ending shift mode and beginning bypass mode. 3. The minimum delay required before restarting normal RAM operation. 4. The minimum delay required before executing a parallel load operation. 5. The minimum delay required between a parallel load operation and a shift. 6. Minimum shift command hold time.
BOUNDARY SCAN
OVERVIEW Boundary scan is a simple, non-intrusive scheme that allows verification of electrical continuity for each of a clocked RAMs logically active inputs and I/Os without adversely affecting RAM performance. Boundary scan allows the user to monitor the logic levels applied to each signal I/O on the RAM, and to shift them out in a serial bit stream. OPERATION Boundary scan requires four signal pins for implementation: scan data in (SDI), scan data out (SDO), scan clock (SCK, active high), and scan enable (SE, active high).
Boundary scan provides three modes of operation: (1) normal RAM operation, (2) scan, and (3) bypass. For normal RAM operation, SCK and SE must be held low. The RAM will always return to normal operation immediately after the RAM receives a rising edge of the RAM input clock (K) with SCK and SE held low. To enter scan mode, SCK is activated. The first rising edge of SCK is used to latch in the data on the scan registers. SE is then driven high to disable additional input data from entering the scan registers. Every falling edge of SCK serially shifts data through the scan registers and onto the SDO pin. To enter bypass mode, simply exercise SCK with SE held low. In this mode, SDI is sampled on the rising edge of SCK. The level found on SDI is then driven out on SDO on the next falling edge of SCK.
MCM67Q909 8
MOTOROLA FAST SRAM
BOUNDARY SCAN TIMING DIAGRAM
NORMAL OPERATION BYPASS SHIFT 3 SHIFT 38 SHIFT 39 SHIFT 40 SHIFT 41 SHIFT n
SHIFT 1
SHIFT 2
NORMAL BYPASS OPERATION
MOTOROLA FAST SRAM
PARALLEL LOAD t CHCL2 t CLCH2 t SR t CLMH t CHCH2 t MHCH t BS t IVCH B1 t CHIX S1 S2 S3 S38 S39 S40 S41 Sn t CHML B2 B1 t CLOV A6 A4 A17 E G W K S1 B2
K
t SS
SCK
SE
SDI
SDO
NOTES:
B1 and B2 = bypass serial data from outside source. S1 - Sn + 1 = serial scan data from outside source. S1 - Sn = RAMs input register contents. Scan order is: A6, A4, A2, A0, D8, Q8, D6, Q6, D4, Q4, D2, Q2, D0, Q0, A18, A1, A3, A5, A7, A8, A9, A10, A11, A12, A13, Q1, D1, Q3, D3, Q5, D5, Q7, D7, A15, A16, A14, A17, E, G, W, K.
MCM67Q909 9
ORDERING INFORMATION
(Order by Full Part Number) MCM 67Q909 XX
Motorola Memory Prefix Part Number
XX
X
Shipping Method (R = Tape and Reel, Blank = Trays) Speed (12 = 12 ns) Package (ZP = PBGA)
Full Part Numbers -- MCM67Q909ZP12 MCM67Q909ZP12R
PACKAGE DIMENSIONS
ZP PACKAGE 86 PBGA CASE 896A-02 0.25 (0.010) T B -W- G 0.15 (0.006) T C L
987654321 A B C D E F G H J K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D E G N P R MILLIMETERS MIN MAX 17.78 BSC 16.26 BSC 1.84 2.44 0.69 0.81 1.33 1.73 1.524 BSC 13.80 14.20 0.762 BSC 15.29 15.69 INCHES MIN MAX 0.700 BSC 0.640 BSC 0.073 0.096 0.028 0.031 0.053 0.068 0.060 BSC 0.544 0.559 0.030 BSC 0.602 0.617
R
A -L- P
C L
N
E C 0.35 (0.014) T
86X
G D 0.30 (0.012) -T- 0.10 (0.004)
S S
4X
0.20 (0.008) TL
S
W
S
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MCM67Q909 10
MCM67Q909/D MOTOROLA FAST SRAM

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