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512kbit(64KX8) OTP EPROM ICE37C512
Description
The ICE37C512 is a low-power, high-performance 512k(524288) bit one-time programmable read only memory (OTP EPROM) organized as 64K by 8 bits. It is single 5V power supply in normal read mode operation. Any byte can be accessed in less than 70ns. The ICE37C512 typically consumes 10mA , standby mode supply current typically less than 10A. Two lines control (CE, OE) to give designers the flexibility to prevent bus contention. Programming time is typically only 100 s/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages.
Features
* Fast Read Access Time : 70ns
* Low-Power consumption - 1 gA Typ. Standby - 10 mA max. Active at 5MHz * JEDEC Standard Packages - 32-Lead 600-mil PDIP - 32-Lead PLCC - 32-Lead TSOP * Operating voltage : 5V 10% * High Reliability CMOS Technology - 2000V ESD Protection - 200 mA Latchup Immunity * Programming time : 100 gs/byte (typical) * CMOS and TTL Compatible Inputs and Outputs * Integrated Product Identification Code * Compatible pin Assignment For FLASH 512k bits Pin Configurations Pin Name A0 - A15 O0 - O7 /CE /OE/VPP NC Function Addresses Outputs Chip Enable Output Enable No Connect
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
DIP Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC NC NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
TSOP Top View Type1
A12
A11 A9 A8 A13 A14 NC NC VCC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE 1/O7 1/O6 1/O5 1/O4 1/O3 GND 1/O2 1/O1 1/O0 A0 A1 A2 A3
PLCC Top View
A15 VCC NC NC NC
31
32
3
15
16
17
18
19
14
GND
I/O1
I/O2
I/O3
I/O4
I/O5
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I/O6
20
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11
29 28 27 26 25 24 23 22 21
30
4
2
1
NC A14 A13 A8 A9 A11 OE A10 CE I/O7
12 13
ICE37C512
Block Diagram
VCC GND VPP OE/ VPP CE OE,CE AND PROGRAM LOGIC OUTPUT BUFFERS
DATA OUTPUTS O0-O7
Y DECODR A0-A15 ADDRESS INPUTS
Y-GATING CELL MATRIX
X DECODER IDENTIFICATION
Absolute Maximum Rating
Operation Temperature Commercial ... ... ... ... ... ... ... ... ... ... ... ... ... 0J to +70J Storage Temperature ... ... ... ... ... ... ... ... ... ..... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .-65J to +125J Voltage on Any Pin with Respect to Ground ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... -0.6V to +7.0V(1)
Vpp Supply Voltage with Respect to Ground... ... ... ... ... ... ... ... ... ... ..... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... -0.6V to +13.5V(1)
Operating Modes Mode\Pin
Read Output Disable Standby (2) Rapid Program PGM Inhibit Product Identification
(4)
CE VIL X VIH VIL VIH VIL
OE/VPP VIL VIH X VPP X VIL
Ai Ai X X Ai X
Outputs DOUT High Z High Z DIN High Z Identification Code
A9 = VH A0,A1 = VIH or VIL A2 - A15 = VIL
(3)
Notes: 1. X can be VIL or VIH . 2. Refer to Programming Characteristics. 3. VH = 12 0.5V. 4. See Product Identification Code item.
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
DC and Operating Characteristics for Read Operation
Symbol ILI ILO ISB ICC VIL VIH VOL VOH Notes: 1.Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2.Vpp may be connected directly to Vcc except during programming. The supply current would then be the sum of ICC and IPP. Parameter Input Load Current Output Leakage Current Vcc
(1)
Condition VIN = 0V to Vcc VOUT = 0V to Vcc Com. Com.
Min
Max 1 5 10 500 10
Units A A A A mA V V V V
Standby Current
ISB1(CMOS), /CE = Vcc 0.3V ISB2(TTL), /CE = 2.0 to Vcc + 0.5V f = 5MHz, IOUT = 0mA, /CE = VIL -0.6 2.0 IOL = 2.1 mA IOH = -400 A 2.4
Vcc Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
0.8 Vcc + 0.5 0.4
AC Waveforms for Read Operation (1)
ADDRESS CE OE/VPP
ADDRES VALID
tCE tOE tDF tACC tOH
OUTPUT VALID
OUTPUT
HIGH Z
Notes: 1.OE/VPP may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 2.OE/VPP may be delayed up to tACC - tOE after the address in valid without impact on tACC. 3.This parameter is only sampled and is not 100% tested. 4.Output float is defined as the point when data is no longer driven.
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
Input Test Waveforms and Measurement Levels
AC DRIVING LEVEL 2.4V
2.0 0.8
0.45V
Output Test Load
1.3V
(1N914)
3.3K OUTPUT PINT CL
Note: C
= 100 pF including jig capacitance
L
Programming Waveforms
PROGRAM READ
VIH
ADDRESS ADDRESS STABLE
VIL tAS
DATA DATA IN
tDV
DATA Out
tAH
tDS
6V VCC 5V
tDFP tDH
tvcs
12.5 V
OE/VPP
VIL
tOEH tPRT tVR
VIH
CE
VIL tPW
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3.When programming the ICE37C512 at 0.1 F capacitor is required across Vpp and ground to suppress spurious voltage transients. 4 ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
DC Programming Characteristics
TA = 25 5J, Vcc = 5.5 0.5V, Vpp = 12 0.5V
Symbol ILI VIL VIH VOL VOH ICC2 IPP2 VID
Parameter Input Load Current Input Low Level Input High Level Output Low Voltage Output High Voltage Vcc Supply Current (Program and Verify) /OE/VPP Current A9 Product Identification Voltage
Test Conditions IIN = VIL, VIH
IOL = 2.1 mA IOH = -400 A /CE = VIL
Limits Max 10 -0.6 0.8 2.0 Vcc + 1 0.4 2.4 40 20 11.0 12.5 Min
Units A V V V V mA mA V
AC Characteristics for Read Operation ICE27C512 -70 Min Max 70 70 30 25 7
Symbol tACC (3) tCE (2) tOE(2)(3) tDF(4)(5) tOH
Parameter
condition
Units ns ns ns ns ns
Address to Output Delay /CE=/OE/VPP=VIL /CE to Output Delay /OE/VPP=VIL /OE/Vpp to Output Delay /CE=VIL /OE/VPP or /CE Hight to Output Float,whichever occurred first Output Hold from Address,/CE or /OE/VPP whichever occurred first
Notes:2,3,4,5.-see AC Waveforms for Read Operation.
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
AC Programming Characteristics
TA = 25 5J, Vcc = 5.5 0.5V, Vpp = 12.0 0.5V Symbol tAS tOEH tOES tDS tAH tDH tDFP tVCS Parameter Address Setup Time /OE/Vpp Hold Time /OE/Vpp Setup Time Data Setup Time Address Hold Time Data Hold Time
/OE/Vpp High to Output Float Delay(2)
Test Conditions
Limits Min 2 2 2 2 0 2 0 2 95 50 2 Max
Units s s s s s s ns s s ns ns s
Input Rise and Fall Times (10% to 90%) 20ns Input Pulse Levels 0.45V to 2.4V Input Timing Reference Level 0.8V to 2.0V Output Timing Reference Level 0.8V to 2.0V
130 105 150
tPW tDV
tPRT tVR
Vcc Setup Time (3) /CE Program Pulse Width Data Valid from /CE Vpp Pulse Rise Time During Programming /OE/VPP Recover time
Notes: 1. Vcc must be applied simultaneously or before / E/V PP and removed simultaneously or after O /OE/VPP 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven - see timing diagram. 3. Program Pulse width tolerance is 100 sec 5%.
Product Identification Code
Codes Continue Code 1 Continue Code 2 Manufacturer Device Type A1 0 0 1 1 A0 0 1 0 1 O7 0 0 0 1 O6 1 1 1 1 Pins O5 O4 1 1 1 1 0 1 0 0 O3 1 1 1 0 O2 1 1 1 0 O1 1 1 1 0 O0 1 1 0 0 Hex Data 7F 7F 5E C0
Rapid Programming Algorithm
A 100 s CE pulse width is used to program. The address is set to the first location. Vcc is raised to 6.0V and /OE/V PP is raised to 12.5V. Each address is first programmed with one 100? /CE pulse without s verification. Then a verification reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 s pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. All bytes are read again and compared with the original data to determine if the device passes or fails.
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
Fast Programming Flowchart
STAR T
ADDR = FIRST LOCATION
Vcc = 6.0V Vpp = 12.5V
PROGRAM ONE 100S PULSE
N INCREMENT ADDRESS LAST ADDR? Y ADDR = FIRST LOCATION
INCREMENT ADDRESS N PASS LAST ADDR?
X=0
FAIL VERIFY BYTE? INCREMENT X
N Y PROGRAM ONE 100S PULSE
X = 10?
Vcc = 5.0V Vpp = 5.0V Y
COMPARE ALL BYTES TO ORIGINAL PASS DEVICE PASSE D
FAIL
DEVICE FAILED
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
Packaging Information
32P, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE
.025(.635)X30a-45a .012(.305) .008(.203) .553(14.0) .547(13.9) .032(.813) .026(.660)
.045(1.14)X45a
PIN NO.1 IDENTIFY
.595(15.1) .585(14.9)
.021(.533) .013(.330) .530(13.5) .490(12.4)
.050(1.27)TYP .030(.762) .015(.381) .300(7.62) REF .430(10.9) .390(9.90) .095(2.41) .060(1.52) .140(3.56) .120(3.05)
AT CONTACT POINTS
.220(.559)X45aMAX (3X)
.453(11.5) .447(11.4) .495(12.6) .485(12.3)
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
32D, 32-Lead, 0.600" wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
32T, 32-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* JEDEC OUTLINE MO- 141 BD
INDEX MARK
18.5(.728) 18.3(.720)
20.2(.795) 19.8(.780)
0.50(.020) BSC 7.50(.295) REF
0.25(.010) 0.15(.006)
8.20(.323) 7.80(.307) 1.20(.047)MAX 0.15(.006) 0.05(.002)
0 REF 5
0.70(.028) 0.50(.020)
0.20(.008) 0.10(.004)
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ICE semiconductor, inc.
Rev 1.1 2003/6/20
ICE37C512
PRODUCTION ORDERING INFORMATION Example ICE37C512 XX XX
Operating Temperature C = Commercial = 0 to 70C Package Type D = PDIP P = PLCC T1:TSOP(8*13.5) T2:TSOP(8*20) T3:TSOP(8*14)
Read Access Speed 70 = 70 ns
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ICE semiconductor, inc.
Rev 1.1 2003/6/20

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