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16Mx64bits PC133 SDRAM SO DIMM
based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16M635AT8 Series
DESCRIPTION
The Hynix HYM71V16M635AT8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V16M635AT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The Hynix HYM71V16M635AT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
* * * * PC133/PC100MHz support 144pin SDRAM SO DIMM Serial Presence Detect with EEPROM 1.155" (29.34mm) Height PCB with single sided components Single 3.30.3V power supply - 1, 2, 4 or 8 or Full page for Sequential Burst * * All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst Data mask function by DQM * Programmable CAS Latency ; 2, 3 Clocks * * * * * * SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM71V16M635AT8-K HYM71V16M635AT8-H HYM71V16M635ALT8-K HYM71V16M635ALT8-H 133MHz 4 Banks 4K Low Power
Clock Frequency
Internal Bank
Ref.
Power
Normal
SDRAM Package
Plating
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Dec. 01 2
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
PIN DESCRIPTION
PIN CK0, CK1 CKE0 /S0 BA0, BA1 A0 ~ A11 /RAS, /CAS, /WE DQM0~DQM7 DQ0 ~ DQ63 VCC VSS SCL SDA SA0~2 NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input No connection
Rev. 0.4/Dec. 01
3
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
PIN ASSIGNMENTS
FRONT SIDE PIN NO.
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
BACK SIDE PIN NO.
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
FRONT SIDE PIN NO.
71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133
BACK SIDE PIN NO.
72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
NAME
VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC
NAME
VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC
NAME
NC NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10/AP VCC DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC
NAME
NC CK1 VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
Voltage Key
61 63 65 67 69 CK0 VCC /RAS /WE /S0 62 64 66 68 70 CKE0 VCC /CAS NC NC
135 137 139 141 143
Rev. 0.4/Dec. 01
4
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
BLOCK DIAGRAM
S0 DQM0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 CS DQM4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 CS
D0
D4
DQM1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
CS
DQM5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
CS
D1
D5
DQM2 DQ 16 DQ17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23
DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
CS
DQM6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ53 DQ 54 DQ 55
DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
CS
D2
D6
DQM3 DQ 24 DQ25 DQ26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 A0 ~ A11, BA0,1 RAS CAS CKE0 WE
DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
CS
DQM7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
CS
D3
D7
D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 ~ D7 D0 ~ D7
10ohm
CK0,2 3.3pF
4 SDRAMs
VCC VSS
SCL
Serial PD
A0 A1 WP A2
SDA Vss 47kohm
SA0 SA1 SA2
Note : 1. The serial resistor values of DQs are 10ohms 2. The padding capacitance of termination R/C for CK1,CK3 is 10pF
Rev. 0.4/Dec. 01
5
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
SERIAL PRESENCE DETECT
BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 ~61 BYTE62 BYTE63 BYTE64 BYTE65 ~71 FUNCTION DESCRIPTION # of Bytes Written into Serial Memory at Module Manufacturer Total # of Bytes of SPD Memory Device Fundamental Memory Type # of Row Addresses on This Assembly # of Column Addresses on This Assembly # of Module Banks on This Assembly Data Width of This Assembly Data Width of This Assembly (Continued) Voltage Interface Standard of This Assembly SDRAM Cycle Time @/CAS Latency=3 Access Time from Clock @/CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back to Back Random Column Address Burst Lenth Supported # of Banks on Each SDRAM Device SDRAM Device Attributes, /CAS Lataency SDRAM Device Attributes, /CS Lataency SDRAM Device Attributes, /WE Lataency SDRAM Module Attributes SDRAM Device Attributes, General SDRAM Cycle Time @/CAS Latency=2 Access Time from Clock @/CAS Latency=2 SDRAM Cycle Time @/CAS Latency=1 Access Time from Clock @/CAS Latency=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active Delay (tRRD) Minimum /RAS to /CAS Delay (tRCD) Minimum /RAS Pulse Width (tRAS) Module Bank Density Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may be used in future) SPD Revision Checksum for Byte 0~62 Manufacturer JEDEC ID Code ....Manufacturer JEDEC ID Code 1.5ns 0.8ns 1.5ns 0.8ns Intel SPD 1.2A Hynix JEDED ID Unused HSI(Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) HSS(singapore) Asia Area 6Eh ADh FFh 0*h 1*h 2*h 3*h 4*h 5*h 7.5ns 5.4ns None 15.625us / Self Refresh Supported x8 None tCCD = 1 CLK 1,2,4,8,Full Page 4 Banks /CAS Latency=2,3 /CS Latency=0 /WE Latency=0 Neither Buffered nor Registered +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 7.5s 5.4ns 15ns 15ns 15ns 45ns 128MB FUNCTION -K 128 Bytes 256 Bytes SDRAM 12 10 1 Bank 64 Bits LVTTL 7.5ns 5.4ns 75h 54h 00h 80h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh 75h 54h 00h 00h 0Fh 0Fh 0Fh 2Dh 20h 2 VALUE
-H
-K 80h 08h 04h 0Ch 0Ah 01h 40h 00h 01h
-H
NOTE
1
75h 54h
10ns 6ns 20ns 15ns 20ns 45ns 1.5ns 0.8ns 1.5ns 0.8ns
A0h 60h 00h 00h 14h 0Fh 14h 2Dh 15h 08h 15h 08h
00h 12h 3, 8
15h 08h 15h 08h
AFh
BYTE72
Manufacturing Location
10
Rev. 0.4/Dec. 01
6
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
Continued
BYTE NUMBER
BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78 BYTE79 BYTE80 BYTE81 BYTE82 BYTE83 BYTE84 BYTE85 BYTE86 BYTE87 ~90 BYTE91 BYTE92 BYTE93 BYTE94 BYTE95 ~98 BYTE99 ~125 BYTE126 BYTE127 BYTE128 ~256
FUNCTION DESCRIPTION
Manufacturer's Part Number (Component) Manufacturer's Part Number (128Mb based) Manufacturer's Part Number (Voltage Interface) Manufacturer's Part Number (Memory Width) ....Manufacturer's Part Number (Memory Width) Manufacturer's Part Number (Module Type) Manufacturer's Part Number (Data Width) ....Manufacturer's Part Number (Data Width) Manufacturer's Part Number (Refresh, SDRAM Bank) Manufacturer's Part Number (Generation) Manufacturer's Part Number (Package Type) Manufacturer's Part Number (Component Configuration) Manufacturer's Part Number (Hyphent) Manufacturer's Part Number (Min. Cycle Time) Manufacturer's Part Number Revision Code (for Component) ....Revision Code (for PCB) Manufacturing Date ....Manufacturing Date Assembly Serial Number Manufacturer Specific Data (may be used in future) Reserved Reserved Unused Storage Locations
FUNCTION
-K 7 (SDRAM) 1 V (3.3V, LVTTL) 1 6 M (SO DIMM) 6 3 5 (4K Refresh, 4Banks) A T 8 (x8 based) - (Hyphen) K Blanks Process Code Process Code Year Work Week Serial Number None 100Mhz Refer to Note7 H 4Bh
VALUE -H
-K 37h 31h 56h 31h 36h 4Dh 36h 33h 35h 41h 54h 48h 2Dh 48h 20h 00h 64h CFh 00h
-H
NOTE
4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 6 4, 6 3, 6 3, 6 6
7, 8, 9 7, 8, 9
Note : 1. The bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for `HYM' in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. Not fixed but dependent 7. CK0, CK1 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support 8. Refer to the most recent Intel and JEDEC SPD Specification 9. These values are applied to PC100 applications only per Intel PC SDRAM specification 10. Refer to HSI Web site.
Byte 83~87 for L-Part
BYTE NUMBER
BYTE83 BYTE84 BYTE85 BYTE86 BYTE87
FUNCTION DESCRIPTION
Manufacturer's Part Number (Power) Manufacturer's Part Number (Package Type) Manufacturer's Part Number (Component Configuration) Manufacturer's Part Number (Hyphent) Manufacturer's Part Number (Min. Cycle Time)
FUNCTION
-K
L T 8 (x8 based) - (Hyphen)
VALUE
-H -K
4Ch 54h 38h 2Dh
-H
NOTE
4, 5 4, 5 4, 5 4, 5
K
H
4Bh
48h
4, 5
Rev. 0.4/Dec. 01
7
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 8 260 10 Rating C C V V mA W C Sec Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70C)
Parameter Power Supply Voltage Input High voltage Input Low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.0 0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1,2 1,3
Note : 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=0 to 70C, VDD=3.30.3V, VSS=0V)
Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF 1 Note
Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit
Rev. 0.4/Dec. 01
8
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
CAPACITANCE (TA=25C, f=1MHz)
-K/H Parameter CK0, CK2 CKE0 Input Capacitance /S0, /S2 A0~11, BA0, BA1 /RAS, /CAS, /WE DQM0~DQM7 Data Input / Output Capacitance DQ0 ~ DQ63 Pin Symbol Min CI1 CI2 CI3 CI4 CI5 CI6 CI/O 25 35 25 40 40 5 5 Max 45 55 40 60 60 15 15 pF pF pF pF pF pF pF Unit
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output 50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
Rev. 0.4/Dec. 01
9
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
DC CHARACTERISTICS I (TA=0 to 70C, VDD=3.30.3V)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL Symbol Min. -8 -1 2.4 Max 8 1 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = +4mA
Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6
DC CHARACTERISTICS II
Parameter Symbol Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active CL=3 CL=2
960 960 1920 16 6.4
Speed -K
880 16
-H
880
Unit
Note
Operating Current
IDD1
mA
1
IDD2P Precharge Standby Current in Power Down Mode IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current
mA 16
160 mA 80 56 mA 56
320 mA 320 960 mA 880 1760 mA mA mA 2 3 4 1
IDD4 IDD5 IDD6
tRRC tRRC(min), All banks active CKE 0.2V
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HYM71V16M635AT8-K/H 4. HYM71V16M635ALT8-K/H
Rev. 0.4/Dec. 01
10
PC133 SDRAM SO DIMM
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-K Parameter Symbol Min System Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 7.5 1000 7.5 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 2.7 5.4 5.4 5.4 5.4 10 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 3 5.4 6 5.4 6 Max Min 7.5 1000 ns ns ns ns 2 CAS Latency = 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 Max ns
HYM71V16M635AT8 Series
-H Unit Note
Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency = 3
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time CAS Latency = 3 CAS Latency = 2
Note : 1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.4/Dec. 01
11
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
AC CHARACTERISTICS II
-K Parameter Symbol Min Operation RAS Cycle Time Auto Refresh RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-In to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output Hi-Z CAS Latency = 3 CAS Latency = 2 tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 60 15 45 15 15 1 0 2 5 2 0 2 3 2 1 1 100K 64 65 20 45 20 15 1 0 2 5 2 0 2 3 2 1 1 100K 64 ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 tRC 60 Max Min 65 Max ns -H Unit Note
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 0.4/Dec. 01
12
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
DEVICE OPERATING OPTION TABLE
HYM71V16M635A(L)T8-K
CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 2CLKs 3CLKs 2CLKs tRCD 2CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 8CLKs 9CLKs 7CLKs tRP 2CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns
HYM71V16M635A(L)T8-H
CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns
Rev. 0.4/Dec. 01
13
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit Entry Exit Entry Exit CKEn-1 H H H H H H H H H H H L H L H L H X L H L H L H L L L H L H L H L H L CKEn X X X X X X X CS L H L L L L L L RAS L X H L H H L H X L L L X H X H X H X V X L L L X H X H X H X V H L H X H X H X H X V CAS L X H H L L H H WE L X H H H L L L DQM X X X X X X X V X X X X X X X X X X CA CA X RA L H L H H L X X X A9 Pin High (Other Pins OP code) MRS Mode
ADDR
A10/ AP OP code X
BA
Note
V V V X V
Precharge power down
Clock Suspend
X
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, 3. The burst read sigle write mode is entered by programming the Write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.4/Dec. 01
14
PC133 SDRAM SO DIMM
HYM71V16M635AT8 Series
PACKAGE DEMENSION
Rev. 0.4/Dec. 01
15

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