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HD404019R Series
Rev. 6.0 Sept. 1998 Description
The HD404019R series are HMCS400-series CMOS 4-bit single-chip microcomputers. Each device incorporates a ROM, RAM, I/O, serial interface, and two timer/counters, and contains high-voltage I/O pins including high-current output pins to directly drive fluorescent displays. The HD404019R series includes four chips. The HD404019R and HD40L4019R are Mask ROM versions. The HD4074019 and HD407L4019 are PROM versions. The HD40L4019R and HD407L4019 are lowvoltage operation versions.
Features
* 16,384-word x 10-bit ROM Mask ROM: HD404019R, HD40L4019R PROM: HD4074019, HD407L4019 * 992-digit x 4-bit RAM * 58 I/O pins, including 26 high-voltage I/O pins (40 V max.) * Two timer/counters 8-bit free-running timer 8-bit auto-reload timer/counter * Clock synchronous 8-bit serial interface * Five interrupt sources Two by external sources Two by timer/counters One by serial interface * Subroutine stack, up to 16 levels including interrupts * Minimum instruction execution time: 0.89 s * Low-power dissipation modes Standby: Stops instruction execution while allowing clock oscillation and interrupt functions to operate Stop: Stops instruction execution and clock oscillation while retaining RAM data
HD404019R Series
* On-chip oscillator Crystal or ceramic oscillator External clock * Packages 64-pin shrink type plastic DIP 64-pin flat plastic package 64-pin shrink type ceramic DIP with window
Ordering Information
Type Mask ROM Product Name HD404019R Model Name HD404019RS HD404019RH HD404019RFS HD40L4019R HD40L4019RS HD40L4019RH ZTATTM HD4074019 HD4074019S HD4074019H HD4074019FS HD4074019C HD407L4019 HD407L4019S HD407L4019H ZTATTM: Zero Turn Around Time. ZTAT is a trademark of Hitachi Ltd. Package DP-64S FP-64A FP-64B DP-64S FP-64A DP-64S FP-64A FP-64B DC-64S DP-64S FP-64A
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HD404019R Series
Differences between ZTATTM and Mask ROM Version
ZTATTM Item Power supply voltage (V) Instruction cycle time (tcyc ) ROM (word) RAM I/O pin circuit*
1
Mask ROM Version HD407L4019 3.0 to 5.5 V 1.12 to 20 s 16,384 x 10-bit 992 x 4-bit HD404019R 3.5 to 6.0 V 0.89 to 10 s 16,384 x 10-bit 992 x 4-bit HD40L4019R 2.7 to 6.0 V 1.12 to 10 s 16,384 x 10-bit 992 x 4-bit
HD4074019 4.5 to 5.5 V 0.89 to 20 s 16,384 x 10-bit 992 x 4-bit Standard pins
NMOS open drain NMOS open drain PMOS open drain PMOS open drain Available Available Available Available Available Available Available Available Available Available -- --
Each pin can be without pull-up MOS (NMOS open drain), with pull-up MOS, or CMOS Each pin can be without pull-down MOS (PMOS open drain) or with pull-down MOS Available Available Available Available Available -- Available Available Available Available -- --
High voltage pins Oscillator stabilization*2 Crystal Ceramic Package DP-64S FP-64A FP-64B DC-64S --: Not available Notes: 1. See table 17. 2. See table 20.
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HD404019R Series
Pin Arrangement
D11 D12 D13 D14 D15 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 RA0 RA1/Vdisp R30 R31 R32/INT0 R33/INT1 R50 R51 R52 R53 R60 R61 R62 R63 VCC
R00 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
64 63 62 61 60 59 58 57 56 55 54 53
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
DP-64S DC-64S
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GND OSC2 OSC1 TEST RESET R93 R92 R91 R90 R83 R82 R81 R80 R73 R72 R71 R70 R43 R42/SO R41/SI R40/SCK
20
21
22
23
24
25
26
27
28
29
30
31
4
R51 R52 R53 R60 R61 R62 R63 VCC R40/SCK R41/SI R42/SO R43 R70 R71 R72 R73
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
R03 R10 R11 R12 R13 R20 R21 R22 R23 RA0 RA1/Vdisp R30 R31 R32/INT0 R33/INT1 R50
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
R02 R01 R00 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FP-64A
Top view
R52 R53 R60 R61 R62 R63 VCC R40/SCK R41/SI R42/SO R43 R70 R71
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D2 D1 D0 GND OSC2 OSC1 TEST RESET R93 R92 R91 R90 R83 R82 R81 R80
32
R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 RA0 RA1/Vdisp R30 R31 R32/INT0 R33/INT1 R50 R51
52
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
51 50 49 48 47 46 45 44 43
FP-64B
42 41 40 39 38 37 36 35 34 33
D3 D2 D1 D0 GND OSC2 OSC1 TEST RESET R93 R92 R91 R90 R83 R82 R81 R80 R73 R72
R33/INT1 R32/INT0 OSC1 GND VCC OSC2 RESET
Block Diagram
R42/SO R41/SI R40/SCK TEST
RA1/Vdisp RA0 System control External interrupt 16,384 x 10-bit ROM SP Instruction decoder Serial interface Timer A Interrupt control Timer B
RA
R93 R92 R91 R90 992 x 4-bit RAM
R9
R83 R82 R81 R80
R8
R73 R72 R71 R70 W ALU SPX SPY X Y ST CA A
R7
B
PC
R63 R62 R61 R60
R6
R53 R52 R51 R50 R4 R3 R2
R5
R1
R0
D port
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
R20 R21 R22 R23
R10 R11 R12 R13
R00 R01 R02 R03
R30 R31 R32/INT0 R33/INT1
R40/SCK R41/SI R42/SO R43
indicates highvoltage I/O pins
HD404019R Series
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HD404019R Series
Pin Functions
Power Supply VCC: Apply the power supply voltage to this pin. GND: Connect to ground. Vdisp: Power supply pin (multiplexed with RA1) for high-voltage I/O pins with a maximum voltage of 40 V (V CC - 40 V). For details, see the Input/Output section. TEST: For test purposes only. Connect it to VCC. RESET: Resets the MCU. For details, see the Reset section. Oscillators OSC 1, OSC 2: OSC1 and OSC 2 can be connected to a crystal resonator, ceramic resonator or an external oscillator circuit. For details, see the Internal Oscillator Circuit section. Ports D0 to D15 (D Port): An input/output port addressed by bits. These 16 pins are all input/output pins. D0 to D3 are standard pins and D4 to D15 are high-voltage pins. The circuit type for each pin can be selected using a mask option. For details, see the Input/Output section. R0 to RA 1 (R Ports): R0 to R9 are 4-bit I/O ports. Only RA is a 2-bit port. R9 and RA are input ports, and R0 to R8 are I/O ports. R0, R1, R2, and RA are high-voltage ports, and R3 to R9 are standard ports. Each pin has a mask option which selects its circuit type. The pins R32, R33, R40, R4 1, and R42 are multiplexed with INT0, INT 1, SCK, SI, and SO, respectively. For details, see the Input/Output section. Interrupts INT0, INT1: External interrupts for the MCU. INT1 can be used as an external event input pin for timer B. INT 0 and INT1 are multiplexed with R32 and R33, respectively. For details, see the Interrupt section. Serial Interface SCK, SI, SO: The transmit clock I/O pin (SCK), serial data input pin (SI), and serial data output pin (SO) are used for serial interface. SCK, SI, and SO are multiplexed with R40, R41, and R4 2, respectively. For details, see the Serial Interface section.
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HD404019R Series
Memory Map
ROM Memory Map The MCU contains a 16,384-word x 10-bit ROM (mask ROM or PROM). It is described in the following paragraphs and by the ROM memory map in figure 1. Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL instructions to branch to the starting address of the initialization program and of the interrupt programs. After reset or an interrupt routine is processed, the program is executed from the vector address. Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for subroutines. The CAL instruction branches to subroutines. Pattern Area ($0000 to $0FFF): Locations $0000 through $0FFF are reserved for ROM data. The P instruction can refer to the ROM data as a pattern. Program Area ($0000 to $3FFF): Locations from $0000 to $3FFF can be used for program code.
0 Vector address 15 16 Zero-page subroutine (64 words) 63 64 Pattern (4096 words) 4095 4096 $0FFF $1000 $003F $0040 $000F $0010 $0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
JMPL instruction (jump to reset routine) JMPL instruction (jump to INT0 routine) JMPL instruction (jump to INT1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B routine)
JMPL instruction (jump to serial routine)
Program (16,384 words)
16383
$3FFF
Figure 1 ROM Memory Map
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HD404019R Series
RAM Memory Map The MCU also contains a 992-digit x 4-bit RAM as the data and stack area. In addition to these areas, interrupt control bits and special function registers are also mapped on the RAM memory space. The RAM memory map (figure 2) is described in the following paragraphs. Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag cannot be set by software. The RSP bit is used only to reset the stack pointer. Special Function Registers Area ($004 to $00B): The special function registers are the mode or data registers for the external interrupt, the serial interface, and the timer/counters. These registers are classified into three types: write-only, read-only, and read/write as shown in figure 2. These registers cannot be accessed by RAM bit manipulation instructions. Data Area ($020 to $3BF): The 16 digits, $020 through $02F, of the data area are called memory registers (MR) and are accessible by the LAMR and XMRA instructions (figure 4). Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for LIFO stacks to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL instruction, CALL instruction) or interrupts are processed. This area can be used as a 16-level nesting stack in which one level requires 4 digits. Figure 4 shows the save condition. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. This area, when not used as a stack, is available as a data area.
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HD404019R Series
0 RAM-mapped registers 31 32 47 48 $01F $020 $02F $030 $000 0 1 2 3 4 5 6 7 8 9 10 11 12 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C
Interrupt control bits area
Memory registers (MR)
Data (928 digits)
(PMR) Port mode register (SMR) Serial mode register Serial data register lower (SRL) Serial data register upper (SRU) (TMA) Timer mode register A (TMB) Timer mode register B (TCBL/TLRL) Timer B* (TCBU/TLRU)
W W R/W R/W W W R/W R/W
959 960 Stack (64 digits) 1023
$3BF $3C0 31 $3FF
Not used $01F
*: Two registers are mapped on the same address. R: Read only W: Write only R/W: Read/write 10 11 Timer counter B lower (TCBL) Timer counter B upper (TCBU) R R Timer load register B lower (TLRL) Timer load register B upper (TLRU) W W $00A $00B
Figure 2 RAM Memory Map
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HD404019R Series
Bit 3 0 IM0 (IM of INT0) IMTA (IM of timer A) Not used Bit 2 IF0 (IF of INT0) IFTA (IF of timer A) Not used Bit 1 RSP (Reset SP bit) IM1 (IM of INT1) IMTB (IM of timer B) IMS (IM of serial) Bit 0 IE (Interrupt enable flag) IF1 (IF of INT1) IFTB (IF of timer B) IFS (IF of serial) $000
1
$001
2
$002
3 IF: IM: IE: SP:
Not used Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer
Not used
$003
Note: Each bit of the interrupt control bit area is set by the SEM/SEMD instruction, reset by the REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by other instructions. Furthermore the interrupt request flag is not affected by the SEM/SEMD instruction. The value of the status flag becomes invalid when the unusable bits are tested.
Figure 3 Interrupt Control Bits Area Configuration
Memory registers Stack area 32 MR (0) $020 960 Level 16 $3C0 33 MR (1) $021 Level 15 34 MR (2) $022 Level 14 35 MR (3) $023 Level 13 36 MR (4) $024 Level 12 37 MR (5) $025 Level 11 38 MR (6) $026 Level 10 39 MR (7) $027 Level 9 40 MR (8) $028 Level 8 41 MR (9) $029 Level 7 42 MR (10) $02A Level 6 43 MR (11) $02B Level 5 44 MR (12) $02C Level 4 45 MR (13) $02D Level 3 46 MR (14) $02E Level 2 47 MR (15) $02F 1023 Level 1 $3FF PC13 to PC0: Program counter ST: Status flag CA: Carry flag
Bit 3 1020 1021 1022 1023 ST PC10 CA PC3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC12 PC8 PC5 PC1
Bit 0 PC11 PC7 PC4 PC0 $3FC $3FD $3FE $3FF
Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position
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HD404019R Series
Functional Description
Registers and Flags The MCU has nine registers and two flags for the CPU operations (figure 5).
3 A 3 B 1 W 3 X 3 Y 3 SPX 3 SPY 0 CA 0 ST 13 PC 9 1 1 1 1 5 SP 0 Stack pointer 0 Program counter Status flag Carry flag 0 SPY register 0 SPX register 0 Y register 0 X register 0 W register 0 B register 0 Accumulator
Figure 5 Registers and Flags Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results from the arithmetic logic unit (ALU), and transfer data to/from memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): The 2-bit W register, and the 4-bit X and Y registers indirectly address RAM. The Y register is also used for D-port addressing. SPX Register (SPX), SPY Register (SPY): The 4-bit registers SPX and SPY assist the X and Y registers, respectively. Carry Flag (CA): The carry flag (CA) stores the overflow from the ALU generated by an arithmetic operation. It is also affected by the SEC, REC, ROTL, and ROTR instructions.
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HD404019R Series
During an interrupt, a carry is pushed onto the stack. It is restored by the RTNI instruction, but not by the RTN instruction. Status Flag (ST): The status flag (ST) holds the ALU overflow, ALU non-zero, and the results of a bit test instruction for the arithmetic or compare instructions. It is a branch condition of the BR, BRL, CAL, or CALL instruction. The value for the status flag remains unchanged until the next arithmetic, compare, or bit test instruction is executed. The status becomes a 1 after the BR, BRL, CAL, or CALL instruction is either executed or skipped. During an interrupt, the status is pushed onto the stack. It is restored back from the stack by the RTNI instruction, but not by the RTN instruction. Program Counter (PC): The program counter is a 14-bit binary counter which controls the sequence in which the instructions stored in ROM are executed. Stack Pointer (SP): The stack pointer (SP) points to the address of the next stack area (up to 16 levels). The stack pointer is initialized to RAM address $3FF. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is restored from it. The stack can only be used up to 16 levels deep because the high-order four bits of the stack pointer are fixed at 1111. The stack pointer is initialized to $3FF by either MCU reset or by the RSP bit reset from the REM/REMD instruction.
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HD404019R Series
Interrupts Five interrupt sources are available on the MCU: external requests (INT0, INT1), timer/counters (timers A and B), and serial port (serial). For each source, an interrupt request flag (IF) interrupt mask (IM), and interrupt vector addresses control and maintain the interrupt request. The interrupt enable flag (IE) also controls interrupt operations. Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped on $000 through $003 of the RAM space. They are accessible by RAM bit manipulation instructions. (The interrupt request flag (IF) cannot be set by software.) The interrupt enable flag (IE) and IF are cleared to 0, and the interrupt mask (IM) is set to 1 by MCU reset. Figure 6 is a block diagram of the interrupt control circuit. Table 1 shows the interrupt priority and vector addresses, and table 2 shows the interrupt conditions corresponding to each interrupt source. An interrupt request is generated when IF is set to 1 and IM is 0. If IE is 1 at this time, the interrupt will be activated and vector addresses will be generated from the priority PLA corresponding to the interrupt source. Table 1 Vector Addresses and Interrupt Priority
Priority -- 1 2 3 4 5 Vector Addresses $0000 $0002 $0004 $0006 $0008 $000C
Reset/Interrupt RESET INT0 INT1 Timer A Timer B Serial
Table 2
Interrupt Conditions
Interrupt Source
Interrupt Control Bit IE IF0 * IM0 IF1 * IM1 IFTA * IMTA IFTB * IMTB IFS * IMS Note: * Indicates don't care
INT0 1 1 * * * *
INT1 1 0 1 * * *
Timer A 1 0 0 1 * *
Timer B 1 0 0 0 1 *
Serial 1 0 0 0 0 1
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HD404019R Series
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed onto the stack. In the third cycle, the instruction is re-executed after jumping to the vector address. At each vector address, program the JMPL instruction to branch to the starting address of the interrupt program. The IF which caused the interrupt must be reset by software in the interrupt program.
$000,0 IE
Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address
$000,2 IF0 $000,3 IM0 $001,0 IF1 $001,1 IM1 $001,2 IFTA $001,3 IMTA $002,0 IFTB $002,1 IMTB
Priority control logic
Vector address
$003,0 IFS $003,1 IMS
Note: $m, n is RAM address $m, bit number n.
Figure 6 Interrupt Control Circuit Block Diagram
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HD404019R Series
Instruction cycles 1 2 3 4 5 6
Instruction execution*
Interrupt acceptance
Stacking IE reset Vector address generation
Execution of JMPL instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction.
Execution of instruction at start address of interrupt routine
Figure 7 Interrupt Processing Sequence
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HD404019R Series
Power on
RESET = 1?
No
Yes Interrupt request? No Yes
No
IE = 1? Yes
Reset MCU
Execute instruction
Accept interrupt
PC (PC) + 1
IE 0 Stack (PC) Stack (CA) Stack (ST)
PC $0002
Yes
INT0 interrupt? No
PC $0004
Yes
INT1 interrupt? No
PC $0006
Yes
Timer A interrupt? No
PC $0008
Yes
Timer B interrupt? No
PC $000C (serial interrupt)
Figure 8 Interrupt Processing Flowchart
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HD404019R Series
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests as shown in table 3. It is reset by an interrupt and set by the RTNI instruction. Table 3
IE 0 1
Interrupt Enable Flag
Interrupt Enable/Disable Disabled Enabled
External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by the port mode register (PMR: $004). Setting bit 3 and bit 2 of PMR causes the R3 3/INT1 and R32/INT0 pins to be used as INT 1 and INT0, respectively. The external interrupt request flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs. (Refer to table 4.) The INT1 input can be used as a clock signal input to timer B in which timer B counts up at each falling edge of the INT1 input. When INT1 is used as the timer B external event input, the external interrupt mask (IM1) has to be set so that the interrupt request by INT1 will not be accepted. (Refer to table 5.) Table 4
IF0, IF1 0 1
External Interrupt Request Flags
Interrupt Request No Yes
Table 5
IM0, IM1 0 1
External Interrupt Masks
Interrupt Request Enabled Disabled (masked)
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs, respectively. External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the external interrupt requests. Port Mode Register (PMR: $004): The port mode register is a 4-bit write-only register which controls the R3 2/INT0 pin, R33/INT1 pin, R41/SI pin, and R42/SO pin as shown in table 6. The port mode register will be initialized to $0 by MCU reset. These pins are therefore initially used as ports.
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HD404019R Series
Table 6
PMR3 0 1
Port Mode Register
R3 3/INT1 Pin Used as R33 port input/output pin Used as INT1 input pin
PMR2 0 1
R3 2/INT0 Pin Used as R32 port input/output pin Used as INT0 input pin
PMR1 0 1
R4 1/SI Pin Used as R41 port input/output pin Used as SI input pin
PMR0 0 1
R4 2/SO Pin Used as R42 port input/output pin Used as SO output pin
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HD404019R Series
Serial Interface
The serial interface is used to transmit/receive 8-bit data serially. It consists of the serial data register, the serial mode register, the octal counter, and the multiplexer as illustrated in figure 9. Pin R40/SCK and the transmit clock signal are controlled by the serial mode register. The contents of the serial data register can be written into or read out by software. The data in the serial data register can be shifted synchronously with the transmit clock signal. The STS instruction initiates serial interface operations and resets the octal counter to $0. The counter starts to count at the falling edge of the transmit clock (SCK) signal and increments by one at the rising edge of SCK. When the octal counter is reset to $0 after eight transmit clock signals, or a transmit/receive operation is discontinued, the serial interrupt request flag will be set.
SROF IFS Serial interface interrupt request flag /2 Internal bus line (S1) MPX SCK 3 4 SMR (4 bits) Serial mode register 4 PMR (4 bits) Port mode register 2 SCK 4 4 SR (8 bits) Serial data register 4 4 Internal bus-line (S2)
System clock
Prescaler (11 bits)
OC (3 bits) Octal counter
Internal bus line (S2)
/2 /8 / 32 / 128 / 512 / 2048 Serial MPX R40/SCK port
R41/SI port
R42/SO port
SCK
SI
SO
Figure 9 Serial Interface Block Diagram Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the R4 0/SCK pin, prescaler divide ratio, and transmit clock source as shown in table 7. The write signal to the serial mode register controls the operating state of the serial interface. The write signal to the serial mode register stops the serial data register and octal counter from accepting the transmit clock, and it also resets the octal counter to $0 simultaneously. Therefore, when the serial interface is in the transfer state, the write signal causes the serial mode register to cease the data transmit and to set the serial interrupt request flag.
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HD404019R Series
The contents of the serial mode register will be changed on the second instruction cycle after the serial mode register has been written to. Therefore, the STS instruction must be executed after the data in the serial mode register has been changed completely. The serial mode register will be reset to $0 by MCU reset. Table 7
SMR3 0 1
Serial Mode Register
R4 0/SCK Used as R40 port input/output pin Used as SCK input/output pin
Transmit Clock SMR2 0 SMR1 0 SMR0 0 1 1 0 1 1 0 0 1 1 0 1 R4 0/SCK Port SCK output SCK output SCK output SCK output SCK output SCK output SCK output SCK input Clock Source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock Prescaler Divide System Clock Ratio Divide Ratio / 2048 / 512 / 128 / 32 /8 /2 -- -- / 4096 / 1024 / 256 / 64 / 16 /4 /1 --
Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of a loworder digit (SRL: $006) and a high-order digit (SRU: $007). The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with the falling edge of the transmit clock signal. At the same time, external data is input from the SI pin to the serial data register, MSB first, synchronously with the rising edge of the transmit clock. Figure 10 shows the I/O timing chart of the transmit clock signal and the data. The read/write operations of the serial data register should be performed after the completion of data transmit/receive. Otherwise the data may not be guaranteed.
Transmit clock 1 Serial output data Serial input data latch timing LSB 2 3 4 5 6 7 8 MSB
Figure 10 Serial Interface I/O Timing
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HD404019R Series
Serial Interrupt Request Flag (IFS: $003, Bit 0): The serial interrupt request flag will be set when the octal counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the octal counter. Refer to table 8. Table 8
IFS 0 1
Serial Interrupt Request Flag
Interrupt Request No Yes
Serial Interrupt Mask (IMS: $003, Bit 1): The serial interrupt mask masks the interrupt request. Refer to table 9. Table 9
IMS 0 1
Serial Interrupt Mask
Interrupt Request Enabled Disabled (masked)
Selection and Change of the Operation Mode: Table 10 shows the serial interface operation modes which are determined by a combination of the value in the port mode register and in the serial mode register. Initialize the serial interface by a write signal to the serial mode register when the operation mode has changed. Table 10
SMR3 1
Serial Interface Operation Mode
PMR1 0 PMR0 0 1 1 0 1 Serial Interface Operating Mode Clock continuous output mode Transmit mode Receive mode Transmit/receive mode
Operating State of Serial Interface: The serial interface has three operating states: the STS waiting state, transmit clock wait state, and transfer state, as shown in figure 11. The STS waiting state is the initialization state of the serial interface. The serial interface enters this state in one of two ways: either by the operation mode changing through a change in the data in the port mode register, or by data being written into the serial mode register. In this state, the serial interface does not operate even if the transmit clock is applied. If the STS instruction is executed, the serial interface shifts to the transmit clock wait state.
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HD404019R Series
In the transmit clock wait state the falling edge of the first transmit clock causes the serial interface to shift to the transfer state. The octal counter then counts up and the serial data register shifts simultaneously. As an exception, if the clock continuous output mode is selected, the serial interface stays in the transmit clock wait state while the transmit clock outputs continuously. The octal counter becomes 000 again after 8 transmit clocks or the execution of the STS instruction, so the serial interface returns to the transmit clock wait state and the serial interrupt request flag is set simultaneously. When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the STS instruction, and stops after 8 clocks.
STS waiting state octal counter = 000 transmit clock disable Change PMR * Write to SMR Write to SMR STS instruction (IFS 1)
Change PMR*
Transmit clock Transmit clock wait state (octal counter = 000) 8 transmit clocks, STS instruction (IFS 1) Transfer state (octal counter 000)
Note: * Change PMR means the operation mode changes as shown below. Clock continuous output mode * Transmit mode * Receive mode * Transmit/receive mode
Figure 11 Serial Interface Operation State Transmit Clock Error Detection Example: The serial interface functions abnormally when the transmit clock is disturbed by external noise. Transmit clock errors can be detected by the procedure shown in figure 12. If more than 8 transmit clocks occur in the transfer state, the state of the serial interface shifts as follows: transfer state, transmit clock wait state, and transfer state. The serial interrupt flag should be reset before entering into the STS state by writing data to SMR. This procedure sets the IFS again.
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HD404019R Series
Transmit/receive (IFS 1) Interrupt disable
IFS 0
Write to SMR
IFS = 1? No Normal end
Yes
Transmit clock error processing
Figure 12 Transmit Clock Error Detection Example
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HD404019R Series
Timers
The MCU contains a prescaler and two timer/counters (timers A and B). See figure 13. The prescaler is an 11-bit binary counter, timer A an 8-bit free-running timer, and timer B is an 8-bit auto-reload timer/event counter.
Internal bus line (S1) 4 TMB (4 bits) INT1 3 Timer B MPX /2048 /2 /4 /8 /32 /128 /512 CPTB TL (4 bits) Timer latch register TCB (8 bits) Timer counter B TLR (8 bits) Timer load register B 4 4 Internal bus line (S2) 4
Timer mode register B
TBOF
IFTB Interrupt request flag of timer B
System clock
Prescaler (11 bits) /2 /4 /8 /32 /128 /512 /1024 /2048
Timer A MPX 3 TMA (3 bits) Timer mode register A
CPTA
TCA (8 bits) Timer counter A
TAOF
IFTA Interrupt request flag of timer A
Figure 13 Timer/Counter Block Diagram Prescaler: The input to the prescaler is the system clock signal. The prescaler is initialized to $0000 by MCU reset, and it starts to count up with the system clock signal as soon as RESET input goes to logic 0. The prescaler keeps counting up except at MCU reset and stop mode. The prescaler provides clock signals to timer A, timer B, and the serial interface. The prescaler divide ratio is selected by timer mode register A (TMA), timer mode register B (TMB), or the serial mode register (SMR). Timer A Operation: After timer A is initialized to $00 by MCU reset, it counts up at every clock input signal. When the next clock signal is applied after timer A becomes $FF, it generates an overflow and becomes $00. This overflow causes the timer A interrupt request flag (IFTA: $001, bit 2) to go to 1. This timer can function as an interval timer periodically generating overflow output at every 256th clock signal input. The clock input signals to timer A are selected by timer mode register A (TMA: $008). Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock source, and the prescaler divide ratio of timer B. When the external event input is used as an input clock signal to timer B, select R33/INT1 as INT1 and set the external interrupt mask (IM1) to prevent an external interrupt request from occurring.
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HD404019R Series
Timer B is initialized according to the data written into timer load register B by software. Timer B counts up at every clock input signal. When the next clock signal is applied to timer B after it is set to $FF, it will generate an overflow output. In this case, if the autoreload function is selected, timer B is initialized according to the value of timer load register B. If it is not selected, timer B goes to $00. The timer B interrupt request flag (IFTB: $002, bit 0) will be set at this overflow output. Timer Mode Register A (TMA: $008): Timer mode register A is a 3-bit write-only register. The TMA controls the prescaler divide ratio of timer A clock input as shown in table 11. Timer mode register A is initialized to $0 by MCU reset. Table 11
TMA2 0
Timer Mode Register A
TMA1 0 TMA0 0 1 1 0 1 Prescaler Divide Ratio / 2048 / 1024 / 512 / 128 / 32 /8 /4 /2
1
0
0 1
1
0 1
Timer Mode Register B (TMB: $009): Timer mode register B (TMB) is a 4-bit write-only register which selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as shown in table 12. Timer mode register B is initialized to $0 by MCU reset. The operation mode of timer B changes at the second instruction cycle after timer mode register B is written to. Timer B should be initialized by writing data into timer load register B after the contents of TMB are changed. The configuration and function of timer mode register B is shown in figure 14. Table 12
TMB3 0 1
Timer Mode Register B
Auto-Reload Function No Yes
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HD404019R Series
TMB2 0 TMB1 0 TMB0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler Divide Ratio, Clock Input Source / 2048 / 512 / 128 / 32 /8 /4 /2 INT1 (external event input)
PMR: $004 PMR3 PMR2 PMR1 PMR0
SMR: $005 SMR3 SMR2 SMR1 SMR0
Transmit clock selection R40/SCK pin mode selection R42/SO pin mode selection R41/SI pin mode selection R32/INT0 pin mode selection R33/INT1 pin mode selection
TMA: $008 TMA2 TMA1 TMA0
TMB: $009 TMB3 TMB2 TMB1 TMB0
Timer B input clock selection Auto-reload function selection
Timer A input clock selection
Figure 14 Mode Register Configuration and Function Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit writeonly timer load register, and an 8-bit read-only timer counter. Each of them has a low-order digit (TCBL: $00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B). (Refer to figure 2.) Timer counter B can be initialized by writing data into timer load register B. Write the low-order digit first, and then the high-order digit. The timer counter is initialized when the high-order digit is written. The timer load register is initialized to $00 by the MCU reset.
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HD404019R Series
The counter value of timer B can be obtained by reading timer counter B. In this case, read the high-order digit first, and then the low-order digit. The count value of the low-order digit is latched at the time when the high-order digit is read. Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the overflow output of timer A (table 13). Table 13
IFTA 0 1
Timer A Interrupt Request Flag
Interrupt Request No Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request from being generated by the timer A interrupt request flag (table 14). Table 14
IMTA 0 1
Timer A Interrupt Mask
Interrupt Request Enabled Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the overflow output of timer B (table 15). Table 15
IFTB 0 1
Timer B Interrupt Request Flag
Interrupt Request No Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask prevents an interrupt request from being generated by the timer B interrupt request flag (table 16). Table 16
IMTB 0 1
Timer B Interrupt Mask
Interrupt Request Enabled Disabled (masked)
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HD404019R Series
Input/Output
The MCU has 58 I/O pins, 32 standard and 26 high voltage. One of three circuit types can be selected by the mask option for each standard pin: CMOS, with pull-up MOS, and without pull-up MOS (NMOS open drain); and one of two circuit types can be selected for each high-voltage pin: with pull-down MOS and without pull-down MOS (PMOS open drain). Since the pull-down MOS is connected to the internal Vdisp line, the RA 1/Vdisp pin must be selected as V disp via the mask option when the option with pull-down MOS is selected for at least one high-voltage pin. See table 17 for I/O pin circuit types. When every input/output pin is used as an input pin, the mask option and output data must be selected in the manner specified in table 18. Output Circuit Operation of With Pull-Up MOS Standard Pins: In the standard pin option with pull-up MOS, the circuit shown in figure 15 is used to shorten the rise time of the output. When the MCU executes an output instruction, it generates a write pulse to the R port addressed by this instruction. This pulse will switch the PMOS (B) on and shorten the rise time. The write pulse keeps the PMOS in the on state for one-eighth of the instruction cycle time. While the write pulse is 0, a high output level is maintained by the pull-up MOS (C). When the HLT signal becomes 0 in the stop mode, MOS (A), (B), and (C) turn off. D Port: I/O port D has 16 discrete I/O pins, each of which can be addressed independently. It can be set/reset through the SED/RED and SEDD/REDD instructions, and can be tested through the TD and TDD instructions. See tables 17 and 18 for the classification of standard pin, high-voltage pin, and the I/O pin circuit types. R Ports: The eleven R ports are composed of 36 I/O pins and 6 input-only pins. Data is input through the LAR and LBR instructions and output through the LRA and LRB instructions. The MCU will not be affected by writing into the input-only and/or non-existing ports, while invalid data will be read when the output-only and/or non-existing ports are read. The R3 2 , R33 , R40 , R4 1 , and R42 pins are multiplexed with the INT0 , INT1 , SC K, SI, and SO pins, respectively. See tables 17 and 18 for the classification of standard pins, high-voltage pins and selectable circuit types of these I/O pins. Unused I/O Pins: If unused I/O pins are left floating, the LSI may malfunction because of noise. The I/O pins should be fixed as follows to prevent malfunction. High-voltage pins: Select without pull-down MOS (PMOS open drain) via the mask option and connect to VCC on the printed circuit board. Standard pins: Select without pull-up MOS (NMOS open drain) via the mask option and connect to GND on the printed circuit board. R4 0/SCK and R42/SO should be used as R40 and R42 by the serial mode register and port mode register, respectively.
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HD404019R Series
Table 17 I/O Pin Circuit Types
Standard Pins Without Pull-Up MOS (NMOS Open Drain) (A) With Pull-Up MOS (B) I/O common pins
HLT Input data
HLT VCC VCC Input data Write pulse HLT Output data
CMOS (C)
HLT VCC HLT Input data
Applicable Pins D0-D 3, R3 0-R3 3, R4 0-R4 3, R5 0-R5 3, R6 0-R6 3,
Output data
HLT Output data
R7 0-R7 3, R8 0-R8 3 R9 0-R9 3
Input pins
HLT Input data
VCC HLT HLT Input data
--
High Voltage Pins Without Pull-Down MOS (PMOS Open Drain) (D) I/O common pins
VCC HLT Output data VCC Vdisp
With Pull-Up MOS (E)
VCC HLT Output data
Applicable Pins D4-D 15 , R0 0-R0 3, R1 0-R1 3, R2 0-R2 3
HLT
Input data
HLT
Input data Input data
Input pins
HLT Input data VCC
HLT
RA 0
Vdisp
Input pins
HLT
Input data
--
RA 1
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HD404019R Series
Standard Pins Without Pull-Up MOS (NMOS Open Drain) or CMOS (A or C) With Pull-Up MOS (B) I/O common pins
SCK HLT VCC HLT + mode select VCC HLT VCC HLT + mode select SCK
Applicable Pins SCK* (output mode)
Internal SCK
Internal SCK VCC VCC HLT
Output pins
VCC HLT
SO
SO
SO
Input pins
Input data HLT HLT Input data
INT0, INT1 SI, SCK (input mode)
Notes: In the stop mode, HLT is 0, HLT is 1 and I/O pins are in high impedance. * If the MCU is interrupted by the serial interface in the external clock input mode, the SCK terminal becomes input only.
Table 18
Data Input from Common Input/Output Pins
Input Possible CMOS Without pull-up MOS (NMOS open drain) With pull-up MOS No Yes Yes Yes Yes Input Pin State -- 1 1 0 0
I/O Pin Circuit Type Standard pins
High voltage pins
Without pull-down MOS (PMOS open drain) With pull-down MOS
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HD404019R Series
VCC VCC PMOS (B) Pull-up MOS (C) Write pulse (output instruction) HLT
NMOS (A)
Data
MOS Buffer A B C
On-Resistance Value Approximately 250 Approximately 1 k Approximately 30 k to 160 k (VCC = 5 V)
1 instruction cycle
Output instruction execution
Write pulse
Figure 15 Output Circuit Operation of With Pull-Up MOS Standard Pins
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HD404019R Series
Reset Pulling the RESET pin high resets the MCU. At power-on or when cancelling the stop mode, the reset must satisfy tRC for the oscillator to stabilize. In all other cases, at least two instruction cycles are required for the MCU to be reset. Table 19 shows the components initialized by MCU reset, and the status of each. Table 19
Item Program counter (PC) Status flag (ST) Stack pointer (SP) I/O pins, output Standard register pins (A) Without pull-up MOS (B) With pull-up MOS (C) CMOS High-voltage (D) Without pullpins down MOS
Initial Values After MCU Reset
Initial Value by MCU Reset Contents $0000 1 $3FF 1 1 1 0 Execute program from the top of ROM address Enable branching with conditional branch instructions Stack level is 0 Enable to input Enable to input -- Enable to input Enable to input Inhibit all interrupts No interrupt request Mask interrupt request See Port Mode Register section See Serial Mode Register section See Timer Mode Register A section See Timer Mode Register B section -- -- -- -- --
(E) With pull- down 0 MOS Interrupt flags Interrupt enable flag (IE) Interrupt request flag (IF) Interrupt mask (IM) Mode registers Port mode register (PMR) Serial mode register (SMR) Timer mode register A (TMA) Timer mode register B (TMB) Timer/counters Prescaler Timer counter A (TCA) Timer counter B (TCB) Timer load register (TLR) Octal counter 0 0 1 0000 0000 000 0000 $000 $00 $00 $00 000
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HD404019R Series
Item Carry flag (CA) After MCU Reset to Recover from After MCU Reset to Recover from Stop Mode Other Modes The contents of the items before MCU reset are not retained. It is necessary to initialize them by software. The contents of the items before MCU reset are not retained. It is necessary to initialize them by software.
Accumulator B register W register X/SPX register Y/SPY register Serial data register RAM
(A) (B) (W) (X/SPX) (Y/SPY) (SR) The contents of RAM before MCU Same as above for RAM reset (just before STOP instruction) are retained
Internal Oscillator Circuit Figure 16 outlines the internal oscillator circuit. A crystal oscillator or ceramic oscillator can be selected as the oscillator type. Refer to table 20 to select the oscillator type. In addition, see figure 17 for the layout of the crystal or ceramic oscillator.
OSC1 Oscillator OSC2
1/4 divider circuit
Timing generator circuit
System clock
Figure 16 Internal Oscillator Circuit
,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, GND ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, OSC,,,,,,,,,,,,,,,,,,,,,,,, 2 ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, OSC,,,,,,,,,,,,,,,,,,,,,,,, 1 ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, TEST ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, RESET ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,
D,,,,,,,,,,,,,,,,,,,,,,,, 0 ,,,,,,,,,,,,,,,,,,,,,,,,
Figure 17 Layout of Crystal or Ceramic Oscillator
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HD404019R Series
Table 20 Examples of Oscillator Circuits
Circuit Configuration External clock operation (OSC1, OSC 2) Oscillator OSC1 Circuit Constants
Open Ceramic oscillator (OSC1, OSC 2) Ceramic oscillator C2 GND Crystal oscillator (OSC1, OSC 2) Crystal Rf C2 GND C1 C1
OSC2 Ceramic oscillator OSC1 Rf OSC2 CSA4.00MG (Murata) Rf: 1 M 20% C1: 30 pF 20% C2: 30 pF 20% Rf: 1 M 20% OSC1 C1: 10 pF to 22 pF 20% C2: 10 pF to 22 pF 20% OSC2 Crystal: Equivalent circuit shown at bottom left Co: 7 pF max. Rs: 100 max. f: 1.0 MHz to 4.5 MHz OSC2
AT-cut parallel resonance crystal OSC1 L C1 C0 RS
Notes: 1. The circuit parameters written above are recommended by the crystal or ceramic oscillator manufacturer. The circuit parameters are affected by the crystal, ceramic resonator, and the floating capacitance when designing the board. When using the resonator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, and other elements should be as short as possible, and avoid crossing other wires. Refer to the recommended layout of the crystal and ceramic oscillator. Refer to figure 17.
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HD404019R Series
Operating Modes
The MCU has two low-power dissipation modes, standby mode and stop mode (table 21). Figure 18 is a mode transition diagram for these modes. Standby Mode: Executing the SBY instruction puts the MCU into standby mode. In standby mode, the oscillator circuit is active, and the interrupts, timer/counters, and serial interface remain working. On the other hand, the CPU stops since the clock related to the instruction execution stops. Registers, RAM, and I/O pins retain the states they were in just before the MCU went into standby mode. Table 21
Condition Instruction Oscillator circuit Instruction execution Registers, flags Interrupt function RAM Input/output pins Timer/counters, serial interface Cancellation method
Low-Power Dissipation Modes
Standby Mode SBY instruction Active Stopped Retained Active Retained Retained* Active RESET input, interrupt request
2
Stop Mode STOP instruction Stopped Stopped Reset*1 Stopped Retained High impedance Stopped RESET input
Notes: 1. The MCU recovers from the stop mode by RESET input. Refer to table 19 for the contents of flags and registers. 2. When I/O circuits are active, an I/O current may flow in the standby mode, depending on the state of the I/O pins. This is an additional current added to the standby mode current dissipation.
SBY instruction Interrupt request Standby mode
Active mode
STOP instruction
RESET = 1
RESET = 0
Stop mode
RESET = 1
RESET = 1
Reset
Figure 18 MCU Operating Mode Transition
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HD404019R Series
Standby mode may be cancelled by inputting RESET or by asserting an interrupt request. In the former case the MCU is reset. In the later case, the MCU becomes active and executes the next instruction following the SBY instruction. If the interrupt enable flag is 1 when an interrupt request is asserted, the interrupt is executed, while if it is 0, the interrupt request is put on hold and normal instruction execution continues. Figure 19 shows the flowchart of the standby mode.
Standby
Oscillator: Active Peripheral clocks: Active All other clocks: Stop
RESET = 1? Yes
No No No No No No IFS = 1? No Yes IMS = 0? Yes No
IF0 = 1? Yes IM0 = 0? Yes
IF1 = 1? Yes No IM1 = 0? Yes
IFTA = 1? No Yes IMTA = 0? Yes
IFTB = 1? Yes No IMTB = 0? Yes
Restart processor clocks
Restart processor clocks Execute next instruction (active mode) No
IE = 1? Yes Accept interrupt
Reset MCU
Execute instruction
Figure 19 MCU Operating Flowchart in Standby Mode
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HD404019R Series
Stop Mode: Executing the STOP instruction brings the MCU into stop mode, in which the oscillator circuit and every function of the MCU stop. The stop mode may be cancelled by resetting the MCU. At this time, as shown in figure 20, reset input must be applied for at least tRC for oscillation to be stabilized. (Refer to the AC Characteristics table.) After the stop mode is cancelled, RAM retains the state it was in just before the MCU went into stop mode, but the accumulator, B register, W register, X/SPX registers, Y/SPY registers, carry flag, and serial data register will not retain their contents.
Stop mode Oscillator
Internal clock
RESET tres STOP instruction execution tres tRC (stabilization time)
Figure 20 Timing of Stop Mode Cancellation
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HD404019R Series
PROM Mode Pin Description
Table 22 describes the pin functions in PROM mode. Table 22
Pin Number DC-64S, DP-64S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 FP-64B 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 FP-64A 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
PROM Mode Signals
MCU Mode Symbol D11 D12 D13 D14 D15 R0 0 R0 1 R0 2 R0 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 RA 0 RA 1/V disp R3 0 R3 1 R3 2/INT0 R3 3/INT1 R5 0 R5 1 R5 2 R5 3 R6 0 R6 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A13 A14 I I A1 A2 A3 A4 A5 A6 A7 A8 A0 A10 A11 A12 VCC I I I I I I I I I I I I PROM Mode Symbol VCC I/O
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HD404019R Series
Pin Number DC-64S, DP-64S 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 FP-64B 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 FP-64A 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 MCU Mode Symbol R6 2 R6 3 VCC R4 0/SCK R4 1/SI R4 2/SO R4 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 R9 3 RESET TEST OSC 1 OSC 2 GND D0 D1 D2 D3 D4 D5 I/O I/O I/O I/O I/O I/O GND O0 O1 O2 O3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I O4 O3 O2 O1 O0 VPP A9 M0 M1 RESET TEST I I I I I I/O I/O I/O I/O I/O I/O I/O I/O VCC O4 O5 O6 O7 CE OE I/O I/O I/O I/O I I PROM Mode Symbol I/O
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HD404019R Series
Pin Number DC-64S, DP-64S 60 61 62 63 64 FP-64B 54 55 56 57 58 FP-64A 52 53 54 55 56 MCU Mode Symbol D6 D7 D8 D9 D10 I/O I/O I/O I/O I/O I/O VCC PROM Mode Symbol I/O
Notes: 1. I/O: Input/output pins I: Input pins O: Output pins 2. Connect each pair of O 4, O3, O2, O1, and O 0. Hitachi supplies the socket adapter on which these pairs are internally connected.
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HD404019R Series
Programmable ROM Operation
The on-chip PROM of HD4074019 and HD407L4019 are programmed in PROM mode. The PROM mode is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 21. In PROM mode, the MCU does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM programmer and a 64-to-28-pin socket adapter. Table 24 lists the recommended PROM programmers and socket adapters. Since the instruction of the HMCS400 series consists of 10 bits, the HMCS400-series microcom puter incorporates a conversion circuit used as a general-purpose PROM programmer. By this circuit, an instruction is read or programmed using 2 addresses, the low-order 5 bits and the high-order 5 bits. For example, if 8 kwords of an on-chip PROM are programmed by a general purpose PROM programmer, 16 kbytes of addresses ($0000 to $3FFF) should be specified. Programming and Verification The HD4074019 and HD407L4019 can be programmed at high-speed without causing voltage stress or affecting data reliability. Table 23 shows how programming and verification modes are selected. Erasing PROMs with ceramic window packages can be erased by ultraviolet light. All erased bits become 1s. The erasing specifications are as follows: ultraviolet (UV) light with wavelength 2537 A with a minimum irradiation of 15 W sec/cm2. These conditions are satisfied by exposing the LSI to a 12,000-W/cm2 UV source for 15 to 20 minutes at a distance of 1 inch. Precautions 1. Addresses $0000 to $7FFF should be specified if the PROM is programmed by a PROM programmer. Note that the plastic package type cannot be erased and reprogrammed. (Only ceramic window packages can be erased and reprogrammed.) 2. Make sure that the PROM programmer, socket adapter, and LSI match properly. Using the wrong programmer for the socket adapter may cause an overvoltage and damage the LSI. Make sure that the LSI is firmly fixed in the socket adapter, and that the socket adapter is firmly fixed to the programmer. 3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to the HD4074019 and HD407L4019, the LSI may be permanently damaged. 12.5 V is the voltage for VPP of Intel's 27256.
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HD404019R Series
Table 23 PROM Modes Selection
Pin Mode Programming Verify Programming inhibited CE Low High High OE High Low High VPP VPP VPP VPP O0 to O7 Data input Data output High impedance
Table 24
Recommended PROM Programmers and Socket Adapters
Socket Adapter Type Name 280 201 29B + UniPak2B S22 Package Type DP-64S DC-64S FP-64B FP-64A DP-64S DC-64S FP-64B FP-64A HS409ESF01H HS409ESH01H HS409ESF01H HS409ESH01H HS409ESS21H Hitachi Type Name HS409ESS11H Maker Hitachi
PROM Programmer* Maker DATA I/O
AVAL DATA Corp.
PKW-1000 PKW-1100 PKW-1600 PKW-3100
Note: * Since the address pins of the HD4074019 and HD407L4019 are high voltage pins, errors may occur in device insertion tests if a PROM programmer other than those listed above is used.
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HD404019R Series
VCC VCC RESET TEST M0 M1 VPP O0 to O7 Data O0 to O7 VCC
R90/VPP
A0 to A14
Address A0 to A14
OE CE
OE CE
GND
Figure 21 PROM Mode Function Diagram
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HD404019R Series
Addressing Modes
RAM Addressing Modes As shown in figure 22, the MCU has three RAM addressing modes: register indirect addressing, direct addressing, and memory register addressing.
W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y1 Y0
RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Register Indirect Addressing
Instruction 1st word Opcode d9 d8 d7
Instruction 2nd word d6 d5 d4 d3 d2 d1 d0
RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Direct Addressing Instruction Opcode 0 0 0 0 1 0 m3 m2 m1 m0
RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0 Memory Register Addressing
Figure 22 RAM Addressing Modes Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits) are used as the RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits) following the opcode used as the RAM address. Memory Register Addressing Mode: The memory registers (16 digits from $020 to $02F) are accessed by executing the LAMR and XMRA instructions.
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HD404019R Series
ROM Addressing Modes and the P Instruction The MCU has four kinds of ROM addressing modes as shown in figure 23.
[JMPL] [BRL] [CALL]
Instruction 1st word Opcode p3 p2 p1 p0 d9 d8 d7
Instruction 2nd word d6 d5 d4 d3 d2 d1 d0
Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL]
0 0 0 0 0
Opcode
0 0 0
a5
a4
a3
a2
a1
a0
Program counter PC13 PC12 PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3
0 0
Accumulator B0 A 3 A 2 A1 A0
B2
B1
Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing
Figure 23 ROM Addressing Modes
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HD404019R Series
Direct Addressing Mode: The program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. These instructions replace the 14 program counter bits (PC 13 to PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 8 pages of ROM with 256 words per page. By executing the BR instruction, the program can branch to an address on the current page. This instruction replaces the low-order eight bits of the program counter (PC7 to PC0) with 8-bit immediate data. When the BR instruction is on a page boundary (256n + 255) (figure 24), executing it transfers the PC contents to the next page, due to the hardware architecture. Consequently, the program branches to the next page when the BR instruction is used on a page boundary. The HMCS400-series cross macroassembler has an automatic paging facility for ROM pages. Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page subroutine area, which is located at $0000 to $003F. When the CAL instruction is executed, 6 bits of immediate data are placed in the low-order six bits of the program counter (PC 5 to PC0) and 0s are placed in the high-order eight bits (PC13 to PC6). Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address determined by the contents of the 4-bit immediate data, accumulator, and B register. P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure 25). When bit 8 in the referred ROM data is 1, 8 bits of ROM data are written into the accumulator and B register. When bit 9 is 1, 8 bits of ROM data are written into the R1 and R2 port output registers. When both bits 8 and 9 are 1, ROM data are written into the accumulator and B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.
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HD404019R Series
BR AAA AAA NOP
256(n - 1) + 255 256n
BR AAA BR BBB
256n + 254 256n + 255 256(n + 1)
BBB NOP
Figure 24 BR Instruction Branch Destination on a Page Boundary
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HD404019R Series
Instruction [P] Opcode p3 p2 p1 p0 B3 B register B2 B1 B0 Accumulator A3 A2 A1 A0
0
0
Referred ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3 B2
B1
B0
A3
A2
A1
A 0 If RO 8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2 R23 R2 2 R21 R2 0 R13 R12 R11 R10 If RO 9 = 1 Pattern
Figure 25 P Instruction
48
HD404019R Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Symbol VCC VPP VT Io Io -I o Value -0.3 to +7.0 -0.3 to +14 -0.3 to VCC + 0.3 VCC - 45 to VCC + 0.3 Total permissible input current Maximum input current Maximum output current 50 15 4 6 30 Total permissible output current Operating temperature Storage temperature -Io Topr Tstg 150 -20 to +75 -55 to +125 Unit V V V V mA mA mA mA mA mA C C 10 1 2 3 5, 6 6, 7 7, 8 7, 9 4 Notes
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation should be under the conditions of the electrical characteristics. If these conditions are exceeded, it may cause a malfunction or affect the reliability of the LSI. All voltages are with respect to GND. 1. Standard pins. 2. High voltage pins. 3. Total permissible input current is the total sum of input currents which flow in from all I/O pins to GND simultaneously. 4. Total permissible output current is the total sum of the output currents which flow out from VCC to all I/O pins simultaneously. 5. Maximum input current is the maximum amount of input current from each I/O pin to GND. 6. D0 to D3 and R3 to R8. 7. Maximum output current is the maximum amount of output current from VCC to each I/O pin. 8. R0 to R2. 9. D4 to D15 . 10. Applied to HD4074019 and HD407L4019.
49
HD404019R Series
Electrical Characteristics
DC Characteristics (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified)
Item Input high voltage Symbol Pin VIH Min Typ Max -- Unit Test Conditions HD404019R, HD4074019 Note
RESET, 0.8 VCC SCK, INT0, INT1 0.9 VCC 0.8 VCC 0.9 VCC SI 0.7 VCC 0.8 VCC 0.7 VCC 0.9 VCC OSC 1 VCC -0.5 VCC -0.3
VCC + 0.3 V
-- -- -- -- -- -- -- -- -- --
VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V 0.2 VCC V
HD40L4019R HD407L4019: VCC = 4.5 V to 5.5 V HD407L4019 HD404019R, HD4074019 HD40L4019R HD407L4019: VCC = 4.5 V to 5.5 V HD407L4019 HD404019R, HD4074019, HD407L4019 HD40L4019R HD404019R, HD4074019
Input low voltage
VIL
RESET, -0.3 SCK, INT0, INT1 -0.3 -0.3 -0.3 SI -0.3 -0.3 -0.3 -0.3
-- -- -- -- -- -- -- -- -- -- --
0.1 VCC 0.2 VCC 0.1 VCC 0.3 VCC 0.2 VCC 0.3 VCC 0.1 VCC 0.5 0.3 -- --
V V V V V V V V V V V
HD40L4019R HD407L4019: VCC = 4.5 V to 5.5 V HD407L4019 HD404019R, HD4074019 HD40L4019R HD407L4019: VCC = 4.5 V to 5.5 V HD407L4019 HD404019R, HD4074019, HD407L4019 HD40L4019R -I OH = 1.0 mA -I OH = 0.5 mA
Input low voltage
VIL
OSC 1
-0.3 -0.3
Output high VOH voltage
SCK, SO VCC -1.0 VCC -0.5
50
HD404019R Series
Item Output low voltage Input/output leakage current Current dissipation in active mode Symbol VOL | IIL | Pin SCK, SO Min Typ -- -- -- Max Unit Test Conditions 0.4 1 V A I OL = 1.6 mA Vin = 0 V to VCC 1 Notes
RESET, -- SCK, INT0, INT1, SI, SO, OSC 1 VCC --
I CC
--
8.0
mA
HD404019R, HD4074019: VCC = 5 V, fOSC = 4 MHz, divide by 4 HD40L4019R, HD407L4019: VCC = 5 V, fOSC = 4 MHz, divide by 4 HD40L4019R, HD407L4019: VCC = 3 V, f OSC = 3.58 MHz, divide by 4 VCC = 5 V, fOSC = 4 MHz, divide by 4
2
-- --
-- --
8.0 3.0
mA mA
2 2
Current dissipation in standby mode Current dissipation in stop mode
I SBY
VCC
--
--
2.0
mA
3
I STOP
VCC
--
--
10
A
HD404019R, HD40L4019R: 4 Vin (TEST, R9 0) = VCC - 0.3 V to VCC, Vin (RESET) = 0 V to 0.3 V HD4074019, HD407L4019: Vin (TEST, R9 0) = VCC - 0.3 V to VCC, Vin (RESET) = 0 V to 0.3 V
--
--
10
A
Stop mode retaining voltage
VSTOP
VCC
2
--
--
V
Notes: 1. Excluding pull-up MOS current and output buffer current (HD404019R, HD40L4019R) Excluding output buffer current (HD4074019, HD407L4019) 2. The MCU is in the reset state. Input/output current does not flow. * MCU in reset state, operation mode * RESET, TEST: VCC * D0 to D3, R3 to R9: V CC * D4 to D15 , R0 to R2, RA0, RA 1: Vdisp 3. The timer/counter operates with the fastest clock. Input/output current does not flow. * MCU in standby mode * Input/output in reset state * Serial interface: stop * RESET: GND * TEST: VCC * D0 to D3, R3 to R9: V CC * D4 to D15 , R0 to R2, RA0, RA 1: Vdisp 4. Excluding pull-down MOS current.
51
HD404019R Series
Input/Output Characteristics for Standard Pins (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified)
Item Input high voltage Symbol VIH Pin D0 to D3, R3 to R9 Min 0.7 VCC 0.8 VCC 0.7 VCC 0.8 VCC Input low voltage VIL D0 to D3, R3 to R9 -0.3 -0.3 -0.3 Typ -- -- -- Max Unit Test Conditions HD404019R, HD4074019 HD40L4019R HD407L4019: VCC = 4.5 V to 5.5 V -- -- -- -- VCC + 0.3 V 0.3 VCC 0.2 VCC 0.3 VCC 0.2 VCC -- V V V HD407L4019 HD404019R, HD4074019 HD40L4019R HD407L4019: VCC = 4.5 V to 5.5 V -0.3 Output high VOH voltage D0 to D3, R3 to R8 -- V V HD407L4019 HD404019R, HD40L4019R: 1 -I OH = 1.0 mA VCC - 0.5 -- Output low VOL voltage Input/output | IIL | leakage current D0 to D3, R3 to R8 D0 to D3, R3 to R9 -- -- -- -- -- V HD404019R, HD40L4019R: 1 -I OH = 0.5 mA 0.4 1 V A I OL = 1.6 mA HD404019R, HD40L4019R: 2 Vin = 0 V to VCC -- 1 A HD4074019, HD407L4019: Vin = 0 V to VCC -- -- 20 150 A A HD404019R, HD40L4019R: 4 VCC = 5 V, Vin = 0 V 3 Note
VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V
VCC - 1.0 --
D0 to D3, -- R3 to R8, R9 1 to R93 R9 0 Pull-up MOS current Notes: 1. 2. 3. 4. -I PU D0 to D3, R3 to R9 -- 30
Applied to I/O pins selected as CMOS output by mask option. Excluding pull-up MOS current and output buffer current. Excluding output buffer current. Applied to I/O pins selected as with pull-up MOS by mask option.
52
HD404019R Series
Input/Output Characteristics for High Voltage Pins (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified)
Item Input high voltage Symbol VIH Pin D4 to D15 , R0 to R2, RA 0, RA 1 Min 0.7 VCC Typ Max -- Unit Test Conditions HD404019R, HD4074019 Note
VCC + 0.3 V
0.8 VCC 0.7 VCC 0.8 VCC Input low voltage VIL D4 to D15 , R0 to R2, RA 0, RA 1 VCC - 40
--
VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V 0.3 VCC V
HD40L4019R: VCC = 3.5 V to 6.0 V
--
HD407L4019: VCC = 4.5 V to 5.5 V
-- --
HD407L4019 HD404019R, HD4074019
VCC - 40 VCC - 40 VCC - 40 Output high voltage VOH
--
0.2 VCC 0.3 VCC 0.2 VCC --
V
HD40L4019R: VCC = 3.5 V to 6.0 V
--
V
HD407L4019: VCC = 4.5 V to 5.5 V
--
V V
HD407L4019 HD404019R, HD40L4019R: -I OH = 15 mA, VCC = 5 V 20%
D4 to D15 VCC - 3.0 --
VCC - 2.0 --
--
V
HD404019R, HD40L4019R: -I OH = 10 mA, VCC = 5 V 20%
VCC - 1.0 -- VCC - 3.0 -- VCC - 2.0 -- VCC - 1.0 -- VCC - 3.0 -- VCC - 2.0 -- VCC - 1.0 --
--
V
HD404019R, HD40L4019R: -I OH = 4 mA
-- -- -- --
V V V V
HD4074019: -I OH = 15 mA HD4074019: -I OH = 10 mA HD4074019: -I OH = 4 mA HD407L4019: -I OH = 15 mA, VCC = 4.5 V to 5.5 V HD407L4019: -I OH = 10 mA HD407L4019: -I OH = 4 mA
-- --
V V
53
HD404019R Series
Item Symbol Pin R0 to R2 Min VCC - 3.0 VCC - 2.0 VCC - 1.0 VCC - 3.0 VCC - 2.0 VCC - 1.0 VCC - 3.0 VCC - 2.0 VCC - 1.0 Output low VOL voltage D4 to D15 , R0 to R2 -- -- VCC - 37 V VCC - 37 V 20 A -- Typ Max -- -- Unit Test Conditions V HD404019R, HD40L4019R: -I OH = 3 mA, VCC = 5 V 20% -- -- V HD404019R, HD40L4019R: -I OH = 2 mA, VCC = 5 V 20% -- -- V HD404019R, HD40L4019R: -I OH = 0.8 mA -- -- -- -- -- -- -- -- V V V V HD4074019: -I OH = 3 mA HD4074019: -I OH = 2 mA HD4074019: -I OH = 0.8 mA HD407L4019: -I OH = 3 mA, VCC = 4.5 V to 5.5 V -- -- -- -- -- V V HD407L4019: -I OH = 2 mA HD407L4019: -I OH = 0.8 mA HD404019R, HD40L4019R: Vdisp = VCC - 40 V HD404019R, HD40L4019R: 150 k at V CC - 40 V -- -- HD4074019, HD407L4019: 150 k at V CC - 40 V Input/output | IIL | leakage current D4 to D15 , R0 to R2, RA 0, RA 1 -- -- 20 A A HD4074019, HD407L4019: Vin = VCC - 40 V to VCC Pull-down MOS current Notes: 1. 2. 3. 4. I PD D4 to D15 , R0 to R2, RA 0, RA 1 Applied to I/O pins selected as with pull-up MOS by mask option. Applied to I/O pins selected as with pull-up MOS (PMOS open drain) by mask option. Excluding pull-down MOS current and output buffer current. Excluding output buffer current. 125 -- 900 HD404019R, HD40L4019R: Vdisp = VCC - 35 V, Vin = VCC 1 4 -- -- HD404019R, HD40L4019R: Vin = VCC - 40 V to VCC 3 2 1 Note Output high VOH voltage
VCC - 37 V
54
HD404019R Series
AC Characteristics (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified)
Item Oscillation frequency Symbol f OSC Pin OSC 1, OSC 2 Min 0.4 0.4 Typ 4 4 Max 4.5 4.5 Unit MHz MHz Test Conditions HD404019R: divide by 4 HD40L4019R: VCC = 3.5 V to 6.0 V, divide by 4 0.4 0.2 0.2 -- 4 4 3.58 4.5 4.5 MHz MHz MHz HD40L4019R: divide by 4 HD4074019: divide by 4 HD407L4019: VCC = 4.5 V to 5.5 V, divide by 4 0.2 Instruction cycle time t cyc 0.89 0.89 -- 1 1 3.58 20 10 MHz s s s s s s ms HD407L4019 HD404019R HD40L4019R: VCC = 3.5 V to 6.0 V 1.12 0.89 0.89 -- 1 1 10 20 20 HD40L4019R HD4074019: divide by 4 HD407L4019: VCC = 4.5 V to 5.5 V, divide by 4 1.12 Oscillation stabilization time t RC OSC 1, OSC 2 -- -- -- 20 20 HD407L4019 HD404019R, HD4074019 1 Note
--
--
20
ms
HD40L4019R: VCC = 3.5 V to 6.0 V
1
-- -- --
-- -- --
40 20 40
ms ms ms
HD40L4019R HD407L4019: VCC = 4.5 V to 5.5 V HD407L4019
1 1 1
Notes: 1. The oscillator stabilization time is the period from when VCC reaches its minimum allowable voltage (HD404019R/HD40L4019R: 3.5 V, HD4074019: 4.5 V, HD407L4019: 3.0 V (3.5 V when VCC = 3.5 V to 6.0 V)) at power-on until when the oscillator stabilizes, or after RESET goes high by MCU reset to quit stop mode. At power-on or when recovering from stop mode, apply the RESET input for more than tRC to meet the necessary time for oscillator stabilization. When using a crystal or ceramic oscillator, consult with the crystal oscillator manufacturer since the oscillator stabilization time depends on the circuit constants and stray capacitance. (See figure 26.)
55
HD404019R Series
Item External clock high width
Symbol t CPH
Pin OSC 1
Min 92 92
Typ -- --
Max -- --
Unit ns ns
Test Conditions HD404019R, HD4074019: divide by 4 HD40L4019R: VCC = 3.5 V to 6.0 V, divide by 4
Note 1 1
120 92
-- --
-- --
ns ns
HD40L4019R: divide by 4 HD407L4019: VCC = 4.5 V to 5.5 V, divide by 4
1 1
115 External clock low width t CPL OSC 1 92 92
-- -- --
-- -- --
ns ns ns
HD407L4019 HD404019R, HD4074019: divide by 4 HD40L4019R: VCC = 3.5 V to 6.0 V, divide by 4
1 1 1
120 92
-- --
-- --
ns ns
HD40L4019R: divide by 4 HD407L4019: VCC = 4.5 V to 5.5 V, divide by 4
1 1
115 External clock rise time External clock fall time t CPr t CPf OSC 1 OSC 1 INT0 INT0 INT1 INT1 RESET All pins -- -- 2 2 2 2 2 --
-- -- -- -- -- -- -- -- --
-- 20 20 -- -- -- -- -- 30
ns ns ns t cyc t cyc t cyc t cyc t cyc pF
HD407L4019
1 1 1 2 2 2 2 3
INT0 high width t IH INT0 low width INT1 low width RESET high width Input capacitance t IL INT1 high width t IH t IL t RSTH Cin
HD404019R, HD40L4019R: f = 1 MHz, Vin = 0 V
All pins -- except R9 0 R9 0 RESET fall time t RSTf -- --
--
30
pF
HD4074019, HD407L4019: f = 1 MHz, Vin = 0 V
-- --
180 20
pF ms 3
Notes: 1. See figure 26. 2. See figure 27. 3. See figure 28.
56
HD404019R Series
Serial Interface Timing Characteristics (HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC - 40 V to VCC, Ta = -20C to +75C HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C - 40 V to V CC , Ta = -20C to +75C unless otherwise specified)
Item Symbol Pin SCK output SCK output SCK output SCK output Min 1 0.4 0.4 -- -- Typ -- -- -- -- -- Max -- -- -- 40 40 Unit t cyc t cyc t cyc ns ns HD404019R, HD4074019, HD407L4019 HD40L4019R: VCC = 3.5 V to 6.0 V -- Transmit clock t SCKf fall time SCK output -- -- -- -- -- 200 40 40 ns ns ns HD40L4019R HD404019R, HD4074019, HD407L4019 HD40L4019R: VCC = 3.5 V to 6.0 V -- Transmit clock t Scyc cycle time Transmit clock t SCKH high width Transmit clock t SCKL low width Transmit clock t SCKHD completion detect time Transmit clock t SCKr rise time Transmit clock t SCKf fall time SCK input SCK input SCK input SCK input 1 0.4 0.4 1 -- -- -- -- -- 200 -- -- -- -- ns t cyc t cyc t cyc t cyc HD40L4019R 1, 2 1 1 1 3 1, 2 1, 2 1, 2 Test Conditions Load shown in figure 30 Notes 1, 2 1, 2 1, 2 1, 2 1, 2
Transmit clock t Scyc cycle time Transmit clock t SCKH high widths Transmit clock t SCKL low widths Transmit clock t SCKr rise time
SCK input SCK input
-- --
-- --
40 40
ns ns
1 1
Notes: 1. See figure 29. 2. See figure 30. 3. Transmit clock completion detect time is the high level period after 8 pulses of transmit clock are input. The serial interrupt request flag is not set when the next transmit clock is input before the transmit clock completion detect time has passed.
57
HD404019R Series
Item Symbol Pin SO Min -- -- Typ -- -- Max 300 300 Unit ns ns Test Conditions HD404019R HD40L4019R: VCC = 3.5 V to 6.0 V -- -- -- -- -- -- 500 200 200 ns ns ns HD40L4019R HD4074019 HD407L4019: VCC = 4.5 V to 5.5 V -- Serial input t SSI data setup time SI 100 100 -- -- -- 400 -- -- ns ns ns HD407L4019 HD404019R HD40L4019R: VCC = 3.5 V to 6.0 V Serial input t SSI data setup time SI 300 200 Serial input data hold time t HSI SI 200 200 -- -- -- -- -- -- -- -- ns ns ns ns HD40L4019R HD4074019, HD407L4019 HD404019R HD40L4019R: VCC = 3.5 V to 6.0 V 400 100 100 -- -- -- -- -- -- ns ns ns HD40L4019R HD4074019 HD407L4019: VCC = 4.5 V to 5.5 V 200 Notes: 1. See figure 29. 2. See figure 30. -- -- ns HD407L4019 1 1 1 1 1 1 1 1 1, 2 1 1 1, 2 1, 2 1, 2 Notes 1, 2 1, 2 Serial output t DSO data delay time
58
HD404019R Series
HD404019R HD4074019 HD407L4019
1/fCP VCC - 0.5 0.5 tCPr tCPH tCPf tCPL
HD40L4019R VCC - 0.3 0.3 tCPr tCPH
1/fCP tCPL tCPf
Figure 26 Oscillator Timing
HD404019R HD4074019 HD407L4019 (VCC = 4.5 V to 5.5 V) INT0, INT1 0.8 VCC 0.2 VCC tIH tIL
HD40L4019R HD407L4019 (VCC = 3.0 V to 4.5 V) INT0, INT1 0.9 VCC 0.1 VCC tIH tIL
Figure 27 Interrupt Timing
HD404019R HD4074019 HD407L4019 (VCC = 4.5 V to 5.5 V) RESET
0.8 VCC 0.2 VCC tRSTH tRSTf
HD40L4019R HD407L4019 (VCC = 3.0 V to 4.5 V) RESET
0.9 VCC 0.1 VCC tRSTH tRSTf
Figure 28 Reset Timing
59
HD404019R Series
HD404019R HD4074019 HD407L4019 (VCC = 4.5 V to 5.5 V) tSCKf SCK VCC - 2.0 V (0.8 0.8 V (0.2 VCC)* VCC)* tSCKL tSCKH tDSO SO
VCC - 2.0 V 0.8 V
tScyc tSCKr tSCKHD
tSSI SI
0.7 VCC 0.3 VCC
tHSI
Note: * VCC - 2.0 V and 0.8 V are the threshold voltages for transmit clock output. 0.8 VCC and 0.2 VCC are the threshold voltages for transmit clock input.
HD40L4019R HD407L4019 (VCC = 3.0 V to 4.5 V) tSCKf SCK VCC - 2.0 V (0.9 VCC)* 0.8 V (0.1 VCC)* tSCKL
tScyc tSCKr tSCKH tDSO
VCC - 2.0 V 0.8 V
tSCKHD
SO
tSSI SI
0.7 VCC 0.3 VCC
tHSI
Note: * VCC - 2.0 V and 0.8 V are the threshold voltages for transmit clock output. 0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock input.
Figure 29 Timing of Serial Interface
VCC RL = 2.6 k 1S2074 H or equivalent
Test point
C
30 pF
R 12 k
Figure 30 Timing Load Circuit
60
HD404019R Series
HD404019R Option List
Date of order Customer Please check off the appropriate applications and enter the necessary information. 5 V operation: HD404019R Low-voltage operation: HD40L4019R Dept. Name ROM code name LSI type number (Hitachi's entry)
1. I/O option Pin D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Standard pins A I/O option BCD E
Note: I/O options masked by Pin R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81 R82 R83 R90 R91 R92 R93 RA0 RA1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I A
are not available. I/O option BCD E
R3
R4
High voltage pins
R5
R6
R0
R1
RA
High voltage pins
R2
R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
R7
High voltage pins
R8
R9
Standard pins
Please mark on RA1/Vdisp
A: Without pull-up MOS (NMOS open drain) B: With pull-up MOS C: CMOS (not be used as input) D: Without pull-down MOS (PMOS open drain) E: With pull-down MOS
61
HD404019R Series
HD404019R Option List
2. RA1/Vdisp RA1: Without pull-down MOS (D) Vdisp Note: If even one high-voltage pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. 3. Divider (DIV) Divide by 4
4. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS.
5. System oscillator (OSC1 and OSC2) Ceramic oscillator Crystal oscillator External clock
6. Stop mode Used Not used
7. Package HD404019R DP-64S FP-64A FP-64B HD40L4019R DP-64S FP-64A
62
HD404019R Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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