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Product Description
Sirenza Microdevices' SHF-0589 is a high performance AlGaAs/ GaAs Heterostructure FET (HFET) housed in a low-cost surface-mount plastic package. The HFET technology improves breakdown voltage while minimizing Schottky leakage current resulting in higher PAE and improved linearity. Output power at 1dB compression is +33.4 dBm when biased for Class AB operation at 7V,345mA at 1.96 GHz. The +46.5 dBm third order intercept makes it ideal for high dynamic range, high intercept point requirements. It is well suited for use in both analog and digital wireless communication infrastructure and subscriber equipment including 3G, cellular, PCS, fixed wireless, and pager systems. Typical Gain Performance (7V,345mA)
SHF-0589
0
Symbol
1
D evice C haracteristics
D E
(unless otherw ise noted)
Test C onditions, 25C VDS=7V, IDQ=345mA
D
Frequency (GHz)
2
3
4
5
6
FO
40 35 30 25 20 15 10 5 0
Gain, Gmax (dB)
Gmax Gain
Applications * Analog and Digital Wireless Systems * 3G, Cellular, PCS * Fixed Wireless, Pager Systems
R
Test Frequency 0.90 GHz 1.96 GHz 2.14 GHz 0.90 GHz 1.96 GHz 1.96 GHz 1.96 GHz 1.96 GHz 1.96 GHz
N
E
* High Drain Efficiency (>50% at P1dB)
W
U nits dB dB dB dB dB m dB m dB m dB m dB mA mS V V V
o
+33.4 dBm P1dB +46.5 dBm OIP3 +26 dBm IS-95 Channel Power +11.5 dB Gain * +23.7 dBm W-CDMA Channel Power
D E
Min 14.1 10.3 44 31.9 816 576 -3.0 3.7 -17 -22 23 -
S
Typ 22.9 17.4 16.6 15.7 11.5 46.5 33.4 26.2 Max 17.3 12.7 1536 1008 -1.0 -15 -17 8.0 480 2.4 1176 792 -1.9
Product Features * High Linearity Performance at 1.96 GHz
Gmax S 21 Gai n OIP3 P 1dB PCHAN NF IDSS gm VP
Maxi mum Avai lable Gai n Inserti on Gai n Power Gai n
[1]
M M E
[2]
Output Thi rd Order Intercept Poi nt Output 1dB C ompressi on Poi nt
[2]
IS-95 C hannel Power (-45dBc AC PR)
Saturated D rai n C urrent Tranconductance
C O
Noi se Fi gure
[2]
BVGS
R E
Pi nch-Off Voltage
[1] [1]
Gate-Source Breakdown Voltage
[1]
BVGD Rth V DS IDQ
Gate-D rai n Breakdown Voltage Thermal Resi stance
[3] [3] [3]
N
ZS=ZS*, ZL=ZL* ZS=ZL= 50 Ohms
Appli cati on C i rcui t Appli cati on C i rcui t Appli cati on C i rcui t Appli cati on C i rcui t Appli cati on C i rcui t VDS= VDSP, VGS= 0V VDS= VDSP, VGS= -0.25V VDS= 2.0V, IDS= 2.4mA IGS= 4.8mA, drai n open IGD= 4.8mA, VGS= -5.0V juncti on-to-lead drai n-source drai n-source, qui escent
[2]
C /W V mA C
N O T
Operati ng Voltage Operati ng C urrent
PDISS
Power D i ssi pati on
[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR. [3] Maximum recommended power dissipation is specified to maintain TJ<140C at TL=85C. VDS * IDQ< 2.4W is recommended for continuous reliable operation.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101242 Rev F
1
IG
N
0.05-3 GHz, 2 Watt GaAs HFET
Absolute Maximum Ratings
MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the bias condition should also satisfy the following expression: PDC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (C) TL = Lead Temperature (pin 4) (C) RTH = Thermal Resistance (C/W)
Parameter Drain Current Forward Gate Current Reverse Gate Current Drain-to-Source Voltage Gate-to-Source Voltage RF Input Power Operating Lead Temperature Storage Temperature Range Power Dissipation Channel Temperature
SHF-0589 2 Watt HFET
Symbol IDS IGSF IGSR VDS VGS PIN TL Value 640 4.8 4.8 Unit
D E
800 TJ 165
<-5 or >0
S
9.0
See Graph
W
PDISS
Tstor
-40 to +165 See Graph
E
Total Dissipated Power (W)
M M E
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
-40
N
-10
D E
Operational (Tj<140C) ABS MAX (Tj<165C)
20
D
50
FO
Power Derating Curve
80
R
Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1.
110
Lead Temperature (C)
Design Considerations and Trade-offs
2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB). 3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET's performance. Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each device to eliminate the effects of pinchoff process variation. 4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage should be increased to 8V to maximize P1dB. For small signal operation OIP3 may be improved by reducing the voltage and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V bias condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipation limit (shown on page 1).
N O T
522 Almanor Ave., Sunnyvale, CA 94085
R E
C O
1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-topart precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is recommended to maintain acceptable performance (RF and thermal).
Phone: (800) SMI-MMIC
N
140 170
http://www.sirenza.com
EDS-101242 Rev F
2
IG
mA V V mW C C W C
N
mA mA
SHF-0589 2 Watt HFET
De-embedded S-Parameters (ZS=ZL=50 Ohms, VDS=7V, IDS=345mA, 25C)
Gain
S22 1 GHz 0.2
W
S11 2.0 1.0
40 35 30 25 20 15 10 5 0 0 1
Gmax Isolation
0 -5 -10 -15 -20 -25 -30 -35 -40 6
1.0 6 GHz 5 GHz 4 GHz 6 GHz 0.2 3 GHz 5 GHz 4 GHz 3 GHz 2 GHz 0.0 0.2 2 GHz 1 GHz
Gain, Gmax (dB)
0.5
S D E
1.0 2.0 5.0 50 MHz
0.5 50 MHz
2
3
4
5
Frequency (GHz)
Note: S-parameters are de-embedded to the device leads with Z S=Z L=50. The data represents typical performace of the device. De-embedded s-parameters can be downloaded from our website (www.sirenza.com).
1.2 1
IDS (A)
0.8 0.6 0.4 0.2
D E
D
DC-IV Curves
FO
R
N
0.5
M M E
0
0
N
2
4
6
8
Typical Performance - Engineering Application Circuits
Freq (MHz ) 900 VDS (V) 7 7 7 IDQ (mA) 345 345 345 P 1d B (dBm) 32.0 33.4 32.7 -45dBc C h an n el P o w er (dBm) 25.7 26.2 23.7
[4] [4] [5]
C O
VDS (V)
-55dBc C h an n el P o w er (dBm) 23.2 23.2 20.5
[4] [4] [5]
R E
OIP3[6] (dBm) 45.0 46.5 46.4
E
VGS = -2.0 to 0V, 0.2V steps T=25 C
10
Gain (dB) 16.3 11.5 11.1
S11 (dB) -20 -15 -15
N O T
1960
2140
[4] IS-95 CDMA Channel Power (9 Fwd Channels, 885kHz offset, 30kHz Adj Chan BW) [5] W-CDMA Channel Power (64 DPCH, 5MHz offset, 3.84MHz Adj Chan BW) [6] POUT= +15dBm per tone, 1MHz tone spacing
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101242 Rev F
3
IG
2.0 5.0 inf 5.0
S 22 (dB) -10 -12 -12
N
NF (dB) 3.6 3.7 4.4
Gain & Isolation
S11, S22 vs Frequency
Isolation (dB)
Caution: ESD sensitive
Appropriate precautions in handling, packaging and testing devices must be observed.
SHF-0589 2 Watt HFET
Part Number Ordering Information
Pin #
1 2 3 4
Function
Gate Source Drain Source RF Input
Description
Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. RF Output Same as Pin 2
SHF-0589
7"
1000
Mounting and Thermal Considerations It is very important that adequate heat sinking be provided to minimize the device junction temperature. The following items should be implemented to maximize MTTF and RF performance. 1. Multiple solder-filled vias are required directly below the ground tab (pin 4). [CRITICAL] 2. Incorporate a large ground pad area with multiple plated-through vias around pin 4 of the device. [CRITICAL] 3. Use two point board seating to lower the thermal resistance between the PCB and mounting plate. Place machine screws as close to the ground tab (pin 4) as possible. [CRITICAL] 4. Use 2 ounce copper to improve the PCB's heat spreading capability. [CRITICAL] 5. Thermal transfer paste should be used between the PCB and the mounting plate to improve heat spreading capability. [RECOMMENDED]
Package Dimensions
E N
4
.177 .068
3
W
.161
H5
R
FO
.096
1
2
D
.059
D E
DIMENSIONS ARE IN INCHES
M M E
Recommended Mounting Configuration for Optimum RF and Thermal Performance
Ground Plane
C O
R E
Plated Thru Holes (0.020" DIA) SHF-0x89
N O T
Machine Screws
522 Almanor Ave., Sunnyvale, CA 94085
N
Phone: (800) SMI-MMIC
4
D E
.016 .019 .118 .041 .015
Part Symbolization The part will be symbolized with the "H5" designator and a dot signifying pin 1 on the top surface of the package.
http://www.sirenza.com
EDS-101242 Rev F
S
IG
N
Pin Description
Part Number
Reel Siz e
Devices/Reel

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