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EFG7189 EFG71891
DTMF GENERATOR FOR BINARY CODED HEXADECIMAL DATA
.GENERATES .USESLOWCOST3. .DI .ACCEPTS4BI .DATAI .LOWHARMONI .HI .LOWPOWER .PULLPAIRS
16 STANDARD DTMF TONE
579 MHz CRYSTAL RECT MICROPROCESSOR INTERFACE T DATA IN SERIAL OR PARALLEL FORMAT S STORED DURING TRANSMISSION PERIOD C DISTORTION GH GROUP PRE EMPHASIS CONSUMPTION IN STANDBY MODE UP TO V+ ON ALL LOGIC INPUTS
Minidip
DIP14
ORDERING NUMBERS : EFG71891PD (Minidip) EFG7189PD (DIP14)
PIN CONNECTIONS (Top view)
DESCRIPTION This CMOS circuit is designed specifically to provide, with a minimum number of external components, a low cost DTMF dialer for microprocessor controlled telephone sets operating in accordance with existingstandards.The4 bitsidentifyingthe frequency pair to be generated may be supplied via either 5 connectionsbetweenthe EFG7189and the microprocessor in parallel format or in serial format through 3 connections linking the EFG7189 to the microprocessor. This feature eliminates the necessity to simulate keyboard type inputs normally required by standard DTMF generators. Input data is stored on trailing edge of ISA signal. The tone pair selected by this code is generated while ISA remains low. With ISA high, the oscillator is inhibited and the device is in standby mode. SA pin is con- nectedto V while device is outputtingany tone pair.
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EFG7189 - EFG71891
BLOCK DIAGRAM
PIN DESCRIPTION
N 1 4 11 10 9 12 13 Name V+ - V B C D A H Function Supply Voltage Supply Voltage Logic Input Logic Input Logic Input Logic Input Serial Input Clock Positive Supply 0V Parallel input for hexadecimal code allowing the selection of 2 frequencies constituting the DTMF signal (see attached table). Serial or Parallel Input for Hexadecimal Code Clock Input for Hexadecimal Code Serial Input Register on Pin A Furthermore, it allows for the selection of the serial or parallel operating mode of this code. When ISA input goes low, the validated code is : * the parallel input code if input H is high. * the serial input code if input H is low. This pin allows for the inhibition of the analog output MF OUT : * when ISA is high, output MF OUT is idle and connected to V -. * when ISA is low, the hexadecimal code is validated and MF OUT output is activated. This pin indicates the state of the analog output : * if ISA is low, SA is a low impedance output at V -. * if ISA is high, SA is a high impedance output. This pin is the DTMF signal output. This pin corresponds to the input of the inverter of the oscillator. The nominal frequency of the oscillator is 3.579 MHz. Description
2
ISA
Logic Input
8
SA
Logic Output
14 5
MF OUT OSC IN
Analog Output Oscillator Input
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ABSOLUTE MAXIMUM RATINGS
Symbol V+ V in Tstg Supply Voltage Digital Input Range Storage Temperature Range Parameter Value - 0.3 to + 5.5 - 0.3 to V + 0.3 - 55 to + 125
+
Unit V V C
ELECTRICAL OPERATING CHARACTERISTICS All voltages referenced to V
Symbol V+ Toper fc Positive Supply Voltage Operating Temperature Range Crystal Frequency Parameter Min. 3 - 25 - Typ. - - 3.579545 Max. 5.25 70 - Unit V C MHz
DC ELECTRICAL CHARACTERISTICS Tamb = - 25 C to 70 C, V+ = - 3 to 5.25 V, fc = 3.579 MHz (all voltages are referenced to V-)
Symbol IDD ISB VIL V IH RT IOLSA IFSA Parameter Operating Current in Transmission Mode (V+ = 4 V, output not loaded) Standby Current (ISA, H, A, B, C, D open circuit or connected to V+) Input Low Voltage (ISA, H, A, B, C, D) Input High Voltage (ISA, H, A, B, C, D) Pull up Resistor on Logic Inputs ISA, H, A, B, C, D SA Output Current (VOLSA = 0.5 V) SA Leakage Current, Open Current (VOHSA = 5 V) Min. - - 0 0.7 V 100 500 -
+
Typ. 0.6 - - - - - -
Max. 1 10 0.3 V V
+ +
Unit mA A V V k A A
- - 2
A.C. ELECTRICAL CHARACTERISTICS Tamb = - 25 C to 70 C, V+ - 3 V to 5.25 V, fc = 3.579 MHz
Symbol tr tf TISAON TISA OFF TH THH THL TPH TMH TPISA TMISA Transmission Delay Blocking Delay Clock Period High Level Clock Width Low Level Clock Width Set-up Time of A Related to Clock Hold Time of A Related to Clock Set-up Time of the Code or Clock Related to ISA Hold Time of Code Related to ISA Parameter Rise/Fall Time on Input Signals Min. - - - 10 5 5 1 7 1 2 Typ. - - - - - - - - - - Max. 50 5 5 - - - - - - - Unit ns ms ms s s s s s s s
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TRANSMISSION CHARACTERISTICS Tamb = - 25 C to 70 C, V+ 3 V to 5.25 V, fc = 3.579
Symbol DFH DFB AFB GBH D Parameter High and Low Frequency Precision Low Frequency Transmission Level (V = 4 V) - Note 1 High Band Pre-emphasis Output Distortion
+
Min. - -8 2.3 -
Typ. - -7 2.7 -
Max. 1 -6 3.5 - 20
Unit % dBm dB dB
No te : 1. 0 dBm = 0.775 V rms. These specifications are related to the following loads.
Figure 1.
MIXED LOAD RESISTIVE LOAD
FUNCTIONAL DESCRIPTION With ISA input at logic level "1", the device is in low power mode. The oscillator is inhibited and analog output MF OUT is at ground level. DTMF input data isdetectedon trailingedgeof ISA.Thistransitionenables both the oscillator and the analog output then the data is stored and corresponding DTMF pair is generated during the low state interval of the ISA signal. Any modification to H, A, B, C and D signals during this period will not have any further effect on DTMF pair generated. The device accepts input data in two different formats : allel format: thisrequires 4 connections(A, B, C, D) betweenthe microprocessor andthe circuit. ial format : in this case data is supplied to the circuit by the microprocessor via 2 connectionsA and H (see typical application diagram).
tonesof DTMF pairare suppliedthroughanalogoutput pin. DATA ACQUISITION LOGIC This section includes : A 4-bit shift register, an 8-line to 4-line multiplexer and a 4-bit storage register. bit shift register has its input connected to pin A and is enabled by the signal applied to pin H. Its outputs are AS, BS, CS and DS signals. tiplexer is enabledby signal H and operates according to the following law : AI = H.AP + H.AS. 4-bit storage register operates on trailing edge of ISA signal. AI, BI, CI, DI and AL, BL, CL, DL are its inputs and outputs respectively.
.Par .Ser
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.The4.Themul .The
Pre-emphasisis appliedto high grouptone and both
During the low state period of ISA input, AL, BL, CL and DL signals determinethe DTMF pair to be generated.
EFG7189 - EFG71891
Figure 2 : Example of Parallel Operating Mode.
No te : If the circuit operates permanently in parallel mode, then the H input may be left floating (internally pulled-up to V+) or tied to logic 1. With ISA at logic 0, H,A,B,C, and D inputs cannot modify the generated DTMF pair.
Figure 3 : Example of Serial-Operating Mode.
H
A
ISA
MF OUT
770 . 1477
697 . 1209
AS = BS = CS = DS =
0 X X X
1 0 X X
1 1 0 X
0 1 1 0
1 X X X
0 1 X X
0 0 1 X
0 0 0 1
Stored data (H = 0) AL = AS = 0 BL = DS = 1 CL = CS = 1 DL = DS = 0
Stored data (H = 0) 0 0 0 1
Notes : 1. With ISA at logic 0, H, A, B, C and D signals cannot modify the generated DTMF pair. As a result, in serial operating mode, it is possible to enter AS, BS, CS and DS data while another DTMF pair is being generated. 2. First data to be entered is DS.
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Figure 4 : Data Acquisition Logic.
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TIMING DIAGRAM Figure 5 : Rise/Fall Time on Input Signals.
Figure 6 : Parallel Operating Mode (H = "1").
Figure 7 : Serial Operating Mode.
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Table 1
DTMF Specification (Hz) f1 f2 f3 f4 f5 f6 f7 f8 770 852 941 1209 1336 1477 1633 697 Frequencies Derived from a 3.579 MHz Quartz (Hz) 701.3 771.4 857.2 935.1 1215.9 1331.7 1471.9 1645 Division Rank 5104 4640 4176 3828 2944 2688 2432 2176 % Deviation from Standard 0.62 0.19 0.61 - 0.63 0.57 - 0.32 - 0.35 0.74
Table 2
Keyboard Code X 1 2 3 4 5 6 7 8 9 0 * A B C D Hexadecimal Code A X 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 B X 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 C X 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ISA 1 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 Generated Frequencies f(Hz) f(Hz)
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TYPICAL APPLICATION (european standards) Figure 8 : Parallel Connection.
N ote : H may be left open or connected to logic 1.
Figure 9 : Serial Connection.
No te : B, C and D may be left floating or connected to logic 1.
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SECOND ORDER LOW-PASS FILTERS Figure 10 : With Transistor (gain = 1).
Figure 11 : With Op. Amp. (gain = 1).
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MINIDIP PACKAGE MECHANICAL DATA
DIM Min. A a1 B b b1 D E e e3 e4 F i L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0260 0.200 0.150 0.060 mm Typ. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 Max. Min. inch Typ. 0.131 Max.
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DIP14 PACKAGE MECHANICAL DATA
DIM Min. a1 B b b1 D E e e3 F i L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 mm Typ. Max. Min. 0.020 0.055 0.020 0.010 0.787 0.065 inch Typ. Max.
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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