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256-Position One-Time Programmable Dual-Channel I2C Digital Potentiometers AD5172/AD5173
FEATURES
2-channel, 256-position OTP (one-time programmable) set-and-forget resistance setting, low cost alternative to EEMEM Unlimited adjustments prior to OTP activation OTP overwrite allows dynamic adjustments with user defined preset End-to-end resistance: 2.5 k, 10 k, 50 k, 100 k Compact MSOP-10 (3 mm x 4.9 mm) package Fast settling time: tS = 5 s typ in power-up Full read/write of wiper register Power-on preset to midscale Extra package address decode pins AD0 and AD1 (AD5173) Single supply 2.7 V to 5.5 V Low temperature coefficient: 35 ppm/C Low power, IDD = 6 A max Wide operating temperature: -40C to +125C Evaluation board and software are available Software replaces C in factory programming applications
FUNCTIONAL BLOCK DIAGRAMS
A1 W1 B1 A2 W2 B2
VDD 1 GND RDAC REGISTER 1
FUSE LINKS
2 RDAC REGISTER 2
/8
SDA SCL SERIAL INPUT REGISTER
04103-0-001
Figure 1. AD5172
W1 B1 W2 B2
APPLICATIONS
Systems calibration Electronics level setting Mechanical Trimmers(R) replacement in new designs Permanent factory PCB setting Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment
VDD 1 GND RDAC REGISTER 1 FUSE LINKS 2 RDAC REGISTER 2
AD0 AD1 SDA SCL
ADDRESS DECODE
/8
SERIAL INPUT REGISTER
04103-0-002
GENERAL OVERVIEW
The AD5172/AD5173 are dual channel, 256-position, one-time programmable (OTP) digital potentiometers1 that employ fuse link technology to achieve memory retention of resistance setting. OTP is a cost-effective alternative to EEMEM for users who do not need to program the digital potentiometer setting in memory more than once. This device performs the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. The AD5172/AD5173 are programmed using a 2-wire, I C compatible digital interface. Unlimited adjustments are allowed before permanently setting the resistance value. During OTP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
2
Figure 2. AD5173
Unlike traditional OTP digital potentiometers, the AD5172/ AD5173 have a unique temporary OTP overwrite feature that allows for new adjustments even after the fuse has been blown. However, the OTP setting is restored during subsequent powerup conditions. This feature allows users to treat these digital potentiometers as volatile potentiometers with a programmable preset. For applications that program the AD5172/AD5173 at the factory, Analog Devices offers device programming software running on Windows(R) NT(R), 2000, and XP(R) operating systems. This software effectively replaces any external I2C controllers, thus enhancing the time-to-market of the user's systems.
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5172/AD5173 TABLE OF CONTENTS
Electrical Characteristics--2.5 k ................................................. 3 Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4 Timing Characteristics--2.5 k, 10 k, 50 k, 100 k Versions ............................................................................................................. 5 Absolute Maximum Ratings............................................................ 6 Typical Performance Characteristics ............................................. 7 Test Circuits..................................................................................... 11 Operation......................................................................................... 12 One-Time Programming (OTP) .............................................. 12 Programming the Variable Resistor and Voltage.................... 12 Programming the Potentiometer Divider ............................... 13 ESD Protection ........................................................................... 14 Terminal Voltage Operating Range.......................................... 14 Power-Up Sequence ................................................................... 14 Power Supply Considerations................................................... 14 Layout Considerations............................................................... 15 Evaluation Software/Hardware..................................................... 16 Software Programming ............................................................. 16 I2C Interface .................................................................................... 18 I2C Compatible 2-Wire Serial Bus ........................................... 20 Pin Configuration and Function Descriptions........................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide............................................................................... 24
REVISION HISTORY
Revision A 11/03--Data Sheet Changed from Rev. 0 to Rev. A Change Location
Changes to Electrical Characteristics--2.5 k......................... 3
Rev. A | Page 2 of 24
AD5172/AD5173 ELECTRICAL CHARACTERISTICS--2.5 k
Table 1. VDD = 5 V 10% or 3 V 10%; VA = +VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted
Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect Nominal Resistor Tolerance3 RAB TA = 25C Resistance Temperature Coefficient (RAB/RAB)/T VAB = VDD, Wiper = No Connect RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to all VRs) Differential Nonlinearity4 DNL Integral Nonlinearity4 INL (VW/VW)/T Code = 0x80 Voltage Divider Temperature Coefficient Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA, VB, VW Capacitance6 A, B CA, CB f = 1 MHz, Measured to GND, Code = 0x80 Capacitance W CW f = 1 MHz, Measured to GND, Code = 0x80 7 Shutdown Supply Current IA_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance6 CIL POWER SUPPLIES Power Supply Range VDD RANGE OTP Supply Voltage VDD_OTP TA = 25C Supply Current IDD VIH = 5 V or VIL = 0 V OTP Supply Current IDD_OTP VDD_OTP = 6 V, TA = 25C Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = 5 V 10%, Code = Midscale 9 DYNAMIC CHARACTERISTICS Bandwidth -3 dB BW_2.5K Code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz VW Settling Time tS VA = 5 V, VB = 0 V, 1 LSB Error Band Resistor Noise Voltage Density eN_WB RWB = 1.25 k, RS = 0
1 2
Min -2 -6 -20
Typ1 0.1 0.75 35 160
Max +2 +6 +55 200 +1.5 +2
Unit LSB LSB % ppm/C LSB LSB ppm/C LSB LSB V pF pF
-1.5 -2
0.1 0.6 15 -2.5 2
-10 0 GND
0 10 VDD
45 60 0.01 1 2.4 0.8 2.1 0.6 1 5 2.7 6 3.5 100 0.02 4.8 0.1 1 3.2 30 0.08 5.5 6.5 6 1
A nA V V V V A pF V V A mA W %/% MHz % s nV/Hz
Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 8 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use VDD = 5 V.
Rev. A | Page 3 of 24
AD5172/AD5173 ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
Table 2. VDD = 5 V 10% or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted
Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect Nominal Resistor Tolerance3 RAB TA = 25C Resistance Temperature Coefficient (RAB/RAB)/T VAB = VDD, Wiper = No Connect RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to all VRs) Differential Nonlinearity4 DNL Integral Nonlinearity4 INL Voltage Divider Temperature Coefficient (VW/VW)/T Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA, VB, VW Capacitance6 A, B CA, CB f = 1 MHz, Measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, Measured to GND, Code = 0x80 Shutdown Supply Current7 IA_SD VDD = 5.5 V Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance6 CIL POWER SUPPLIES Power Supply Range VDD RANGE OTP Supply Voltage8 VDD_OTP Supply Current IDD VIH = 5 V or VIL = 0 V OTP Supply Current9 IDD_OTP Power Dissipation10 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = +5 V 10%, Code = Midscale DYNAMIC CHARACTERISTICS11 Bandwidth -3 dB BW RAB = 10 k, Code = 0x80 RAB = 50 k, Code = 0x80 RAB = 100 k, Code = 0x80 Total Harmonic Distortion THDW VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VW Settling Time (10 k/50 k/100 k) tS VA = 5 V, VB = 0 V, 1 LSB Error Band Resistor Noise Voltage Density eN_WB RWB = 5 k, RS = 0
1 2
Min -1 -2.5 -20
Typ1 0.1 0.25 35 160
Max +1 +2.5 +20 200 +1 +1 0 2.5 VDD
Unit LSB LSB % ppm/C LSB LSB ppm/C LSB LSB V pF pF A nA V V V V A pF V V A mA W %/% kHz kHz kHz % s nV/Hz
-1 -1 -2.5 0 GND
0.1 0.3 15 -1 1
45 60 0.01 1 2.4
1
0.8 2.1 0.6 1 5 2.7 6 3.5 100 0.02 600 100 40 0.1 2 9 30 0.08 5.5 6.5 6
Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 8 Different from operating power supply, power supply OTP is used one time only. 9 Different from operating current, supply current for OTP lasts approximately 400 ms for one time only. 10 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 11 All dynamic characteristics use VDD = 5 V.
Rev. A | Page 4 of 24
AD5172/AD5173 TIMING CHARACTERISTICS--2.5 k, 10 k, 50 k, 100 k VERSIONS
Table 3. VDD = 5 V 10% or 3V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted
Parameter Symbol Conditions I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications Apply to All Parts) SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time for Repeated START Condition t5 tHD;DAT Data Hold Time2 t6 tSU;DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Setup Time for STOP Condition t10
1 2
Min
Typ
Max 400
Unit kHz s s s s s s ns ns ns s
1.3 0.6 1.3 0.6 0.6 0.9 100 300 300 0.6
See timing diagrams for locations of measured values. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Rev. A | Page 5 of 24
AD5172/AD5173 ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25C, unless otherwise noted
Parameter VDD to GND VA, VB, VW to GND Terminal Current, Ax-Bx, Ax-Wx, Bx-Wx1 Pulsed Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance2 JA: MSOP-10 Value -0.3 V to +7 V VDD 20 mA 5 mA 0 V to 7 V -40C to +125C 150C -65C to +150C 300C 230C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 24
AD5172/AD5173 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 1.5 RHEOSTAT MODE INL (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5
04103-0-003
0.5
TA = 25C RAB = 10k POTENTIOMETER MODE DNL (LSB)
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
RAB = 10k
VDD = 2.7V
VDD = 2.7V; TA = -40C, +25C, +85C, +125C
VDD = 5.5V
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 3. R-INL vs. Code vs. Supply Voltages
Figure 6. DNL vs. Code vs. Temperature
0.5 0.4
RHEOSTAT MODE DNL (LSB)
1.0 TA = 25C RAB = 10k
POTENTIOMETER MODE INL (LSB)
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
04103-0-004
TA = 25C RAB = 10k
0.3 0.2 VDD = 2.7V 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 256 CODE (DECIMAL) VDD = 5.5V
VDD = 5.5V
VDD = 2.7V
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
Figure 4. R-DNL vs. Code vs. Supply Voltages
Figure 7. INL vs. Code vs. Supply Voltages
0.5 0.4
POTENTIOMETER MODE INL (LSB)
0.5
RAB = 10k
POTENTIOMETER MODE DNL (LSB)
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
04103-0-005
TA = 25C RAB = 10k
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96
VDD = 5.5V TA = -40C, +25C, +85C, +125C
VDD = 2.7V
VDD = 2.7V TA = -40C, +25C, +85C, +125C
VDD = 5.5V
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 5. INL vs. Code vs. Temperature
Figure 8. DNL vs. Code vs. Supply Voltages
Rev. A | Page 7 of 24
04103-0-008
-0.5
04103-0-007
-1.0
04103-0-006
-2.0
-0.5
AD5172/AD5173
2.0 RAB = 10k 1.5 RHEOSTAT MODE INL (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5
04103-0-009
4.50 RAB = 10k
ZSE, ZERO-SCALE ERROR (LSB)
VDD = 2.7V TA = -40C, +25C, +85C, +125C
3.75
3.00
2.25
VDD = 2.7V, VA = 2.7V
VDD = 5.5V TA = -40C, +25C, +85C, +125C
1.50 VDD = 5.5V, VA = 5.0V 0.75
0
32
64
96
128
160
192
224
256
-25
-10
5
20
35
50
65
80
95
110
125
CODE (DECIMAL)
TEMPERATURE (C)
Figure 9. R-INL vs. Code vs. Temperature
Figure 12. Zero-Scale Error vs. Temperature
0.5 0.4 RAB = 10k
10
RHEOSTAT MODE DNL (LSB)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
04103-0-010
VDD = 2.7V, 5.5V; TA = -40C, +25C, +85C, +125C
IDD, SUPPLY CURRENT (A)
VDD = 5V
1 VDD = 3V
0
32
64
96
128
160
192
224
256
-7
26
59
92
125
CODE (DECIMAL)
TEMPERATURE (C)
Figure 10. R-DNL vs. Code vs. Temperature
Figure 13. Supply Current vs. Temperature
2.0 RAB = 10k
120 RAB = 10k RHEOSTAT MODE TEMPCO (ppm/C) 100
1.5
FSE, FULL-SCALE ERROR (LSB)
1.0 0.5 0 -0.5 -1.0 -1.5
04103-0-011
80
60
VDD = 5.5V, VA = 5.0V
VDD = 2.7V TA = -40C TO +85C, -40C TO +125C VDD = 5.5V TA = -40C TO +85C, -40C TO +125C
40
VDD = 2.7V, VA = 2.7V
20
0
-25
-10
5
20
35
50
65
80
95
110
125
0
32
64
96
128
160
192
224
256
TEMPERATURE (C)
CODE (DECIMAL)
Figure 11. Full-Scale Error vs. Temperature
Figure 14. Rheostat Mode Tempco RWB/T vs. Code
Rev. A | Page 8 of 24
04103-0-014
-2.0 -40
-20
04103-0-013
-0.5
0.1 -40
04103-0-012
-2.0
0 -40
AD5172/AD5173
50 POTENTIOMETER MODE TEMPCO (ppm/C) RAB = 10k 40 30 20 10 0 -10 -20
04103-0-047
0 -6 -12 0x80 0x40 0x20 0x10 0x08 0x04 0x02 -42
VDD = 2.7V TA = -40C TO +85C, -40C TO +125C GAIN (dB)
-18 -24 -30 -36
VDD = 5.5V TA = -40C TO +85C, -40C TO +125C
0x01 -48 -54
0
32
64
96
128
160
192
224
256
1k
10k
100k FREQUENCY (Hz)
1M
CODE (DECIMAL)
Figure 15. AD5172 Potentiometer Mode Tempco VWB/T vs. Code
Figure 18. Gain vs. Frequency vs. Code, RAB = 50 k
0 -6 -12 -18 0x80 0x40 0x20
0 -6 -12 -18 0x10 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 -48 -54
04103-0-048
GAIN (dB)
-30 -36 -42 -48 -54 -60 10k
GAIN (dB)
-24
0x08 0x04
-24 -30 -36 -42
0x02 0x01
100k FREQUENCY (Hz)
1M
10M
1k
10k
100k FREQUENCY (Hz)
1M
Figure 16. Gain vs. Frequency vs. Code, RAB = 2.5 k
Figure 19. Gain vs. Frequency vs. Code, RAB = 100 k
0 -6 -12 -18 0x80 0x40 0x20 0x10
0 -6 -12 -18 100k 60kHz 50k 120kHz 10k 570kHz 2.5k 2.2MHz
GAIN (dB)
0x08 -30 0x04 -36 -42 -48 -54
04103-0-049
GAIN (dB)
-24
-24 -30 -36 -42 -48 -54
0x02 0x01
1k
10k
100k FREQUENCY (Hz)
1M
1k
10k
100k FREQUENCY (Hz)
1M
10M
Figure 17. Gain vs. Frequency vs. Code, RAB = 10 k
Figure 20. -3 dB Bandwidth @ Code = 0x80
Rev. A | Page 9 of 24
04103-0-052
-60
-60
04103-0-051
-60
04103-0-050
-30
-60
AD5172/AD5173
10 TA = 25C
IDD, SUPPLY CURRENT (mA)
1 VDD = 5.5V
VW2
0.1 VDD = 2.7V
VW1
04103-0-056
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIGITAL INPUT VOLTAGE (V)
04103-0-057
0.01
Figure 21. IDD vs. Input Voltage
Figure 24. Analog Crosstalk
VW
VW
SCL
04103-0-053 04103-0-058
Figure 22. Digital Feedthrough
Figure 25. Midscale Glitch, Code 0x80 to 0x7F
VW2
VW
VW1
04103-0-054
SCL
04103-0-055
Figure 23. Digital Crosstalk
Figure 26. Large Signal Settling Time
Rev. A | Page 10 of 24
AD5172/AD5173 TEST CIRCUITS
Figure 27 to Figure 34 illustrate the test circuits that define the test conditions used in the product specification tables.
DUT A V+ B W
VMS
04103-0-015
V+ = VDD 1LSB = V+/2N
VIN OFFSET GND 2.5V
DUT A W
+15V
AD8610 B -15V
VOUT
04103-0-019
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 31. Test Circuit for Gain vs. Frequency
NO CONNECT DUT A B VMS
04103-0-016
IW W
DUT W ISW B
RSW =
0.1V ISW
CODE = 0x00 0.1V
04103-0-020
GND TO VDD
Figure 28. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 32. Test Circuit for Incremental On Resistance
DUT A VMS2 B VMS1 RW = [VMS1 - VMS2]/ I W W VW I W = VDD /R NOMINAL
VDD
04103-0-017
NC DUT A GND B W ICM
NC
Figure 29. Test Circuit for Wiper Resistance Figure 33. Test Circuit for Common-Mode Leakage Current
VA DUT VDD V+ B A W V+ = VDD 10% PSRR (dB) = 20 LOG PSS (%/%) = VMS V MS% V DD%
04103-0-018
(V MS ) DD
N/C VIN
V
A1 RDAC1 W1
VDD
A2 RDAC2 W2 VOUT
B1
VSS
B2
04103-0-022
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
CTA = 20 log[VOUT/VIN]
Figure 34. Test Circuit for Analog Crosstalk
Rev. A | Page 11 of 24
04103-0-021
VCM
AD5172/AD5173 OPERATION
SCL SDA I2C INTERFACE DAC REG. A MUX DECODER W
B COMPARATOR FUSES EN ONE-TIME PROGRAM/TEST CONTROL BLOCK FUSE REG.
Figure 35. Detailed Functional Block Diagram
An internal power-on preset places the wiper at midscale during power-on. If the OTP function has been activated, the device powers up at the user-defined permanent setting.
B
B
B
Figure 36. Rheostat Mode Configuration
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5172/AD5173 presets to midscale during initial power-on. After the wiper is set at the desired position, the resistance can be permanently set by programming the T bit high along with the proper coding (see Table 5 and Table 6). Note that fuse link technology requires 6 V to blow the internal fuses to achieve a given setting. The user is allowed only one attempt at blowing the fuses. Once programming is completed, the power supply voltage must be reduced to the normal operating range of 2.7 V to 5.5 V. The device control circuit has two validation bits, E1 and E0, that can be read back to check the programming status (see Table 7). Users should always read back the validation bits to ensure that the fuses are properly blown. After the fuses have been blown, all fuse latches are enabled upon subsequent power-on; therefore, the output corresponds to the stored setting. Figure 35 shows a detailed functional block diagram.
Assuming a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Because there is a 50 wiper contact resistance, such a connection yields a minimum of 100 (2 x 50 ) resistance between terminals W and B. The second connection is the first tap point, which corresponds to 139 (RWB = RAB/256 + 2 x RW = 39 + 2 x 50 ) for data 0x01. The third connection is the next tap point, representing 178 (2 x 39 + 2 x 50 ) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 (RAB + 2 x RW).
A RS
D7 D6 D5 D4 D3 D2 D1 D0
RS
RS W
PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B is available in 2.5 k, 10 k, 50 k, and 100 k. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings.
Rev. A | Page 12 of 24
RDAC LATCH AND DECODER RS B
04103-0-028
Figure 37. AD5172/AD5173 Equivalent RDAC Circuit
04103-0-027
The AD5172/AD5173 is a 256-position, digitally controlled variable resistor (VR) that employs fuse link technology to achieve memory retention of resistance setting.
A W
A W
04103-0-026
A W
AD5172/AD5173
The general equation that determines the digitally programmed output resistance between W and B is
RWB(D) =
D x RAB + 2 x RW 128
(1)
Typical device-to-device matching is process lot dependent and may vary by up to 30%. Because the resistance element is processed using thin film technology, the change in RAB with temperature has a very low 35 ppm/C temperature coefficient.
where D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 k and the A terminal is opencircuited, the output resistance RWB is set for the RDAC latch codes, as shown in Table 5.
Table 5. Codes and Corresponding RWB Resistance
D (Dec.) 255 128 1 0 RWB () 9,961 5,060 139 100 Output State Full-Scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance)
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A-to-B. Unlike the polarity of VDD to GND, which must be positive, voltage across A-B, W-A, and W-B can be at either polarity.
VI A W VO
04103-0-029
B
Figure 38. Potentiometer Mode Configuration
Note that in the zero-scale condition, a finite wiper resistance of 100 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is
RWA(D) =
If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is
VW (D ) =
256 - D D VA + VB 256 256
(3)
For a more accurate calculation, which includes the effect of wiper resistance, VW can be found as
VW (D) = R (D) RWB (D) VB V A + WA R AB R AB (4)
256 - D x RAB + 2 x RW 128
(2)
For RAB = 10 k and the B terminal open-circuited, the following output resistance RWA is set for the RDAC latch codes, as shown in Table 6.
Table 6. Codes and Corresponding RWA Resistance
D (Dec.) 255 128 1 0 RWA () 139 5,060 9,961 10,060 Output State Full-Scale Midscale 1 LSB Zero-Scale
Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not the absolute values. Thus, the temperature drift reduces to 15 ppm/C.
Rev. A | Page 13 of 24
AD5172/AD5173
ESD PROTECTION
All digital inputs--SDA, SCL, AD0, and AD1-- are protected with a series input resistor and parallel Zener ESD structures, as shown in Figure 39 and Figure 40.
340
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time programming and normal operating voltage supplies are applied to the same VDD terminal of the AD5172/AD5173. The AD5172/ AD5173 employ fuse link technology that requires 6 V to blow the internal fuses to achieve a given setting. The user is allowed only one attempt at blowing the fuses. Once programming is completed, power supply voltage must be reduced to the normal 2.7 V to 5.5 V operating range. Such dual voltage requirements require isolation between the supplies. The fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 6 V and must be able to provide a 100 mA transient current for 400 ms for successful one-time programming. Once programming is complete, the 6 V supply must be removed to allow normal operation at 2.7 V to 5.5 V at regular microamp current levels. Figure 42 shows the simplest implementation using a jumper. This approach saves one voltage supply, but draws additional current and requires manual configuration.
6V R1 50k CONNECT J1 HERE FOR OTP VDD 5V R2 250k CONNECT J1 HERE AFTER OTP
04103-0-033
LOGIC
04103-0-030
04103-0-031
GND
Figure 39. ESD Protection of Digital Pins
A,B,W
GND
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5172/AD5173 VDD to GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or GND are clamped by the internal forwardbiased diodes (see Figure 41).
VDD
C1 1F
C2 1nF
AD5172/ AD5173
A W B
04103-0-032
Figure 42. Power Supply Requirement
GND
An alternate approach in 3.5 V to 5.5 V systems adds a signal diode between the system supply and the OTP supply for isolation, as shown in Figure 43.
6V APPLY FOR OTP ONLY D1 3.5V-5.5V C1 1F C2 1nF VDD
Figure 41. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 41), it is important to power VDD/GND before applying any voltage to terminals A, B, and W. Otherwise, the diode will be forward biased such that VDD is powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is GND, VDD, the digital inputs, and then VA/VB/VW. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND.
AD5172/ AD5173
04103-0-034
Figure 43. Isolate 6 V OTP Supply from 3.5 V to 5.5 V Normal Operating Supply. The 6 V supply must be removed once OTP is completed.
Rev. A | Page 14 of 24
AD5172/AD5173
6V R1 10k 2.7V P1 P2 C1 1F C2 1nF VDD APPLY FOR OTP ONLY
AD5172/ AD5173
04103-0-035
P1=P2=FDV302P, NDS0610
Poor PCB layout introduces parasitics that may affect the fuse programming. Therefore, it is recommended to add a 1 F tantalum capacitor in parallel with a 1 nF ceramic capacitor as close as possible to the VDD pin. These capacitors help ensure OTP programming success by providing proper current densities. This combination of capacitor values provides both a fast response for high frequency transients and a larger supply of current for extended spikes. Typically, C1 minimizes any transient disturbances and low frequency ripple, while C2 reduces high frequency noise.
Figure 44. Isolate 6 V OTP Supply from 2.7 V Normal Operating Supply. The 6 V supply must be removed once OTP is completed.
LAYOUT CONSIDERATIONS
It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.
For users who operate their systems at 2.7 V, use of the bidirectional low threshold P-Ch MOSFETs is recommended for the supply's isolation. As shown in Figure 44, this assumes that the 2.7 V system voltage is applied first, and that the P1 and P2 gates are pulled to ground, thus turning on P1 and subsequently P2. As a result, VDD of the AD5172/AD5173 approaches 2.7 V. When the AD5172/AD5173 setting is found, the factory tester applies the 6 V to VDD; the 6 V is also applied to the gates of P1 and P2 to turn them off. The OTP command is executed at this time to program the AD5172/AD5173; the 2.7 V source is therefore protected. Once the OTP is completed, the tester withdraws the 6 V and the AD5172/AD5173's setting is fixed permanently. AD5172/AD5173 achieves the OTP function through blowing internal fuses. Users should always apply the 6 V one-time program voltage requirement at the first program command. Failure to comply with this requirement may lead to the change of fuse structures, rendering programming inoperable.
VDD C1 1F
+
VDD C2 1nF
AD5172
GND
04103-0-036
Figure 45. Power Supply Bypassing
Rev. A | Page 15 of 24
AD5172/AD5173 EVALUATION SOFTWARE/HARDWARE
Figure 46. AD5172/AD5173 Computer Software Interface
There are two ways of controlling the AD5172/AD5173. Users can either program the devices with computer software or with external I2C controllers.
SOFTWARE PROGRAMMING
Due to the advantages of the one-time programmable feature, users may consider programming the device in the factory before shipping the final product to end-users. ADI offers a device programming software that can be implemented in the factory on PCs running Windows 95 or later. As a result, external controllers are not required, which significantly reduces development time. The program is an executable file that does not require any programming languages or user programming skills. It is easy to set up and to use. Figure 46 shows the software interface. The software can be downloaded from www.analog.com.
The AD5172/AD5173 starts at midscale after power-up prior to OTP programming. To increment or decrement the resistance, the user may simply move the scrollbars on the left. To write any specific value, the user should use the bit pattern in the upper screen and press the Run button. The format of writing data to the device is shown in Table 7. Once the desired setting is found, the user may press the Program Permament button to blow the internal fuse links. To read the validation bits and data out from the device, the user simply presses the Read button. The format of the read bits is shown in Table 8. To apply the device programming software in the factory, users must modify a parallel port cable and configure Pins 2, 3, 15, and 25 for SDA_write, SCL, SDA_read, and DGND, respectively, for the control signals (Figure 47). Users should also lay out the PCB of the AD5172/AD5173 with SCL and SDA pads, as shown in Figure 48, such that pogo pins can be inserted for factory programming.
Rev. A | Page 16 of 24
AD5172/AD5173
13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
AD5172
B1 A1 W2 GND VDD W1 B2 A2 SDA SCL B1 AD0 W2 GND VDD
AD5173
W1 B2 AD1 SDA SCL
04103-0-038
Figure 48. Recommended AD5172/AD5173 PCB Layout. The SCL and SDA pads allow pogo pins to be inserted so that signals can be communicated through the parallel port for programming (Figure 47).
R3 100 R2 READ 100 R1 WRITE
SCL SDA
Figure 47. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND.
04103-0-037
100
Rev. A | Page 17 of 24
AD5172/AD5173 I2C INTERFACE
Table 7. Write Mode AD5172
S 0 1 0111 1 Slave Address Byte W A A0 SD T 0 OW X Instruction Byte X X A D7 D6 D5 D4 D3 D2 D1 D0 Data Byte A P
AD5173
S 0 1 0 1 1 AD1 AD0 W Slave Address Byte A A0 SD T 0 OW X Instruction Byte X X A D7 D6 D5 D4 D3 D2 D1 D0 Data Byte A P
Table 8. Read Mode AD5172
S 0 1 0111 1 Slave Address Byte R A D7 D6 D5 D4 D3 D2 D1 D0 Instruction Byte A E1 E0 X XXX Data Byte X X A P
AD5173
S 0 1 0 1 1 AD1 AD0 R Slave Address Byte A D7 D6 D5 D4 D3 D2 D1 D0 Instruction Byte A E1 E0 X XXX Data Byte X X A P
S = Start Condition P = Stop Condition A = Acknowledge AD0, AD1 = Package Pin Programmable Address Bits X = Don't Care W = Write R = Read A0 = RDAC Subaddress Select Bit SD = Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change contents of wiper register. T = OTP Programming Bit. Logic 1 programs the wiper permanently.
OW = Overwrite the fuse setting and program the digital potentiometer to a different setting. Note that upon power-up, the digital potentiometer is preset to either midscale or fuse setting, depending on whether not the fuse link has been blown. D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits. E1, E0 = OTP Validation Bits. 0, 0 = Ready to Program. 1, 0 = Fatal Error. Some fuses not blown. Do not retry. Discard this unit. 1, 1 = Programmed Successfully. No further adjustments possible.
Rev. A | Page 18 of 24
AD5172/AD5173
t8
SCL
t6
t9
t2
t2
t3 t8 t9
t4
t7
t5
t10
SDA
t1
P S S P
Figure 49. I2C Interface Detailed Timing Diagram
1 SCL SDA
9
1
9
1
9
ACK BY AD5172 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
ACK BY AD5172 FRAME 3 DATA BYTE
ACK BY AD5172
STOP BY MASTER
Figure 50. Writing to the RDAC Register--AD5172
1 SCL SDA
9
1
9
1
9
ACK BY AD5173 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
ACK BY AD5173 FRAME 3 DATA BYTE
ACK BY AD5173
STOP BY MASTER
Figure 51. Writing to the RDAC Register--AD5173
1 SCL SDA
9
1
9
1
9
ACK BY AD5172 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
ACK BY MASTER FRAME 3 DATA BYTE
NO ACK BY MASTER
STOP BY MASTER
Figure 52. Reading Data from a Previously Selected RDAC Register in Write Mode--AD5172
1 SCL SDA
9
1
9
1
9
ACK BY AD5173 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
ACK BY MASTER FRAME 3 DATA BYTE
NO ACK BY MASTER
STOP BY MASTER
Figure 53. Reading Data from a Previously Selected RDAC Register in Write Mode--AD5173
Rev. A | Page 19 of 24
04103-0-043
0
1
0
1
1
AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
E1
E0
X
X
X
X
X
X
04103-0-042
0
1
0
1
1
1
1 R/W
D7
D6
D5
D4
D3
D2
D1
D0
E1
E0
X
X
X
X
X
X
04103-0-041
0
1
0
1
1
AD1 AD0 R/W
A0
SD
T
0
OW
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
04103-0-040
0
1
0
1
1
1
1
R/W
A0
SD
T
0
OW
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
04103-0-039
AD5172/AD5173
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 50 and Figure 51). The following byte is the slave address byte, which consists of the slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device). The AD5172 has a fixed slave address byte, whereas the AD5173 has two configurable address bits, AD0 and AD1 (see Figure 50 and Figure 51). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. If the R/W bit is low, the master writes to the slave device. 2. In the write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is the RDAC subaddress select bit. A logic low selects channel 1; a logic high selects channel 2. The second MSB, SD, is a shutdown bit. A logic high causes an open circuit at terminal A while shorting the wiper to terminal B. This operation yields almost 0 in rheostat mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting is applied to the RDAC. Also, during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting is applied to the RDAC. The third MSB, T, is the OTP programming bit. A logic high blows the poly fuses and programs the resistor setting permanently. The fourth MSB must always be at Logic 0. The fifth MSB, OW, is an overwrite bit. When raised to a logic high, OW allows the RDAC setting to be changed even after the internal fuses have been blown. However, once OW is returned to a logic zero, the position of the RDAC returns to the setting prior to overwrite. Because OW is not static, if the device is powered off and on, the RDAC presets to midscale or to the setting at which the fuses were blown, depending on whether or not the fuses have been permanently set already. The remainder of the bits in the instruction byte are don't cares (see Figure 50 and Figure 51). After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 49). 3. In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference from the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 52 and Figure 53). Note that the channel of interest is the one that is previously selected in the write mode. In the case where users need to read the RDAC values of both channels, they must program the first channel in the write mode and then change to the read mode to read the first channel value. After that, the user must change back to the write mode with the second channel selected and read the second channel value in the read mode. It is not necessary for users to issue the Frame 3 data byte in the write mode for subsequent readback operation. Refer to Figure 52 and Figure 53 for the programming format. Following the data byte, the validation byte contains two validation bits, E0 and E1. These bits signify the status of the one-time programming (see Figure 52 and Figure 53). 4. After all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a STOP condition (see Figure 50 and Figure 51). In read mode, the master issues a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a STOP condition (see Figure 52 and Figure 53).
A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its slave address and instruction bytes in the write mode, the RDAC output is updated on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. Similarly, a repeated read function of the RDAC is also allowed.
Rev. A | Page 20 of 24
AD5172/AD5173
Table 9. Validation Status
E1 0 1 1 E0 0 0 1 Status Ready for Programming. Fatal Error. Some fuses not blown. Do not retry. Discard this unit. Successful. No further programming is possible.
RP RP SDA MASTER SCL 5V SDA AD1 SCL SDA AD1 AD0 SCL 5V SDA AD1 AD0 SCL 5V SDA AD1
04103-0-044
5V
SCL
Multiple Devices on One Bus(AD5173 Only)
Figure 54 shows four AD5173s on the same serial bus. Each has a different slave address because the states of their AD0 and AD1 pins are different. This allows each device on the bus to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C compatible interface.
AD0
AD0
AD5173
AD5173
AD5173
AD5173
Figure 54. Multiple AD5173s on One I2C Bus
Rev. A | Page 21 of 24
AD5172/AD5173 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
B1 1 A1 2 W2 3 GND 4 VDD 5
10 9
W1 B2 A2
04103-0-045
B1 1 AD0 2 W2 3 GND 4 VDD 5
10 9
W1 B2 AD1
04103-0-046
AD5172
TOP VIEW
8 7 6
AD5173
TOP VIEW
8 7 6
SDA SCL
SDA SCL
Figure 55. AD5172 Pin Configuration
Figure 56. AD5173 Pin Configuration
Table 10. AD5172 Pin Function Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 Menmonic B1 A1 W2 GND VDD SCL SDA A2 B2 W1 Description B1 Terminal. A1 Terminal. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. A2 Terminal. B2 Terminal. W1 Terminal.
Table 11.AD5173 Pin Function Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 Mnemonic B1 AD0 W2 GND VDD SCL SDA AD1 B2 W1 Description B1 Terminal. Programmable Address Bit 0 for Multiple Package Decoding. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. Programmable Address Bit 1 for Multiple Package Decoding. B2 Terminal. W1 Terminal.
Rev. A | Page 22 of 24
AD5172/AD5173 OUTLINE DIMENSIONS
3.00 BSC
10 6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
Figure 57. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
Rev. A | Page 23 of 24
AD5172/AD5173 ORDERING GUIDE
Model AD5172BRM2.5 AD5172BRM2.5-RL7 AD5172BRM10 AD5172BRM10-RL7 AD5172BRM50 AD5172BRM50-RL7 AD5172BRM100 AD5172BRM100-RL7 AD5172EVAL1 AD5173BRM2.5 AD5173BRM2.5-RL7 AD5173BRM10 AD5173BRM10-RL7 AD5173BRM50 AD5173BRM50-RL7 AD5173BRM100 AD5173BRM100-RL7 AD5173EVAL1 RAB (k) 2.5 2.5 10 10 50 50 100 100 2.5 2.5 10 10 50 50 100 100 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D0U D0U D0V D0V D10 D10 D11 D11 D1K D1K D1L D1L D1M D1M D1N D1N
1
The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04103-0-11/03(A)
Rev. A | Page 24 of 24

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