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| H 40 ns Prop. Delay, SO-8 Optocoupler Preliminary Technical Data HCPL-0710 Features * * * * +5 V CMOS Compatibility 8 ns Pulse Width Distortion High Speed: 12 Mbd 10 kV/s Minimum Common Mode Rejection * Industrial Temperature Range: 0C to 85C * Safety and Regulatory Approvals UL Recognized 2500 V rms for 1 min. per UL 1577 CSA Component Acceptance Notice #5 Description Available in the SO-8 package style, the HCPL-0710 optocoupler utilizes the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-0710 requires only two bypass capacitors for complete CMOS compatibility. Basic building blocks of the HCPL-0710 are a CMOS LED driver IC and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC which supplies current to the LED. The detector IC incorporates an integrated photodiode, a highspeed transimpedance amplifier, and a voltage comparator with an output driver. Functional Diagram VDD1 1 8 VDD2 VI 2 7 * 3 6 VO GND1 4 SHIELD 5 GND2 TRUTH TABLE VI, INPUT H L VI, OUTPUT H L Applications * Digital Fieldbus Isolation: DeviceNet, SDS, PROFIBUS * Multiplexed Data Transmission * Computer Peripheral Interface * Microprocessor System Interface *Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance. Pin 7 is not connected internally. External connections to pin 7 are not recommended. **A 0.1 F bypass capacitor must be connected between pins 1 and 4, and 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. This data sheet represents the latest information at the time of publication of this catalog. All specifications subject to change. Samples available Fall 1996. 1-416 Electrical Specifications Unless otherwise noted, all specifications are guaranteed across recommended operating conditions. All Typical specifications are at TA = +25C, VDD1 = VDD2 = +5 V. Test conditions that are not specified can be anywhere within the recommended operating range. Parameter DC Specifications Logic Low Input Supply Current Logic High Input Supply Current Input Supply Current Output Supply Current Input Current Logic High Output Voltage Logic Low Output Voltage Switching Specifications Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output Pulse Width Data Rate Pulse Width Distortion |tPHL - tPLH| Propagation Delay Skew Output Rise Time (10 - 90%) Output Fall Time (90 - 10%) Common Mode Transient Immunity at Logic High Output Common Mode Transient Immunity at Logic Low Output Input Dynamic Power Dissipation Capacitance Output Dynamic Power Dissipation Capacitance Symbol IDDIL IDDIH IDDI IDD2 II VOH VOL Min. Typ. 1.5 6.0 5.5 -10 VDD2 - 0.1 0.8 *VDD2 VDD2 4.5 0 0.2 20 23 80 3 12.5 8 20 13 5 10 10 20 20 60 10 pF kV/s VI = VDDI, VO > 0.8 VDDI, VCM = 1000 V VI = 0 V, VO > 0.8 V, VCM = 1000 V CL = 15 pF CMOS Signal Levels MBd ns CL = 15 pF CMOS Signal Levels Max. Units 3.0 10.0 13.0 10.0 10 mA mA mA mA A V V Test Conditions VDD1 = 5.5 V, VI = 0 V VDD1 = 5.5 V, VI = VDDI VDD1 = 5.5 V VDD2 = 5.5 V IO = -20 A, VI = VIH IO = -4 mA, VI = VIH IO = 20 A, VI = VIL IO = 4 mA, VI = VIL CL = 15 pF CMOS Signal Levels 0.1 0.8 40 40 tPHL tPLH PW PWD tPSK tR tF |CMH| |CML| CPD1 CPD2 ns 1-417 OPTOCOUPLERS |
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