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Ne Tolew 5V Inp rant u 20L ts on V8D
Features
* HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 3.5 ns Maximum Propagation Delay -- Fmax = 250 MHz -- 2.5 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology -- TTL-Compatible Balanced 8mA Output Drive * 3.3V LOW VOLTAGE 20V8 ARCHITECTURE -- JEDEC-Compatible 3.3V Interface Standard -- 5V Compatible Inputs * ACTIVE PULL-UPS ON ALL PINS * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * EIGHT OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs -- Programmable Output Polarity * PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- Glue Logic for 3.3V Systems -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Standard Logic Speed Upgrade * ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
GAL20LV8
Low Voltage E2CMOS PLD Generic Array LogicTM
Functional Block Diagram
I/CLK I I 8 I 8 I OLMC I/O/Q IMUX
CLK
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (64 X 40)
8
OLMC
I/O/Q
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I 8 I 8 OLMC
OE
OLMC
I/O/Q
I I
I/O/Q
I IMUX I/OE
Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK Vcc NC I/O/Q
26 25
I
4 I I I NC I I I 11 12 9 7 5
I
2
28
I
I/O/Q I/O/Q
GAL20LV8D
Top View
23
I/O/Q NC
21
I/O/Q I/O/Q
14
16
19 18
I/O/Q
I
I
NC
GND
I/OE
I
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
March 2000
20lv8_05
1
Specifications GAL20LV8
GAL20LV8D Ordering Information
Commercial Grade Specifications
Tpd (ns)
3.5 5 7.5
Tsu (ns)
3 4 5
Tco (ns)
2.5 3 5
Icc (mA)
70 70 70
Ordering #
GAL20LV8D-3LJ GAL20LV8D-5LJ GAL20LV8D-7LJ
Package
28-Lead PLCC 28-Lead PLCC 28-Lead PLCC
Part Number Description
XXXXXXXX _ XX X XX
GAL20LV8D Device Name Grade Blank = Commercial
Speed (ns) L = Low Power Power
Package J = PLCC
2
Specifications GAL20LV8
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL20LV8D . The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL20LV8D can emulate. It also shows the OLMC mode under which the devices emulate the PAL architecture.
PAL Architectures Emulated by GAL20LV8D 20R8 20R6 20R4 20RP8 20RP6 20RP4 20L8 20H8 20P8 14L8 16L6 18L4 20L2 14H8 16H6 18H4 20H2 14P8 16P6 18P4 20P2
GAL20LV8D Global OLMC Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple
Compiler Support for OLMC
Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 2 and pin 16 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 2 and pin 16 become dedicated inputs and use the feedback paths of pin 26 and pin 18 respectively. Because of this feedback path usage, pin 26 and pin 18 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 21 and 23) will not have the feedback option as these pins are always configured as dedicated combinatorial output.
Registered ABEL CUPL LOG/iC OrCAD-PLD PLDesigner TANGO-PLD P20V8R G20V8MS GAL20V8_R "Registered"1 P20V8R2 G20V8R
Complex P20V8C G20V8MA GAL20V8_C7 "Complex"1 P20V8C2 G20V8C
Simple P20V8AS G20V8AS GAL20V8_C8 "Simple"1 P20V8C2 G20V8AS3
Auto Mode Select P20V8 G20V8 GAL20V8 GAL20V8A P20V8A G20V8
1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later.
3
Specifications GAL20LV8
Registered Mode
In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 20R8 and 20RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page.
CLK
Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 2 controls common CLK for the registered outputs. - Pin 16 controls common OE for the registered outputs. - Pin 2 & Pin 16 are permanently configured as CLK & OE for registered output configuration.
D
Q Q
XOR
OE
Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 2 & Pin 16 are permanently configured as CLK & OE for registered output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications GAL20LV8
Registered Mode Logic Diagram
PLCC Package Pinout
2
2640 0 4 8 12 16 20 24 28 32 36 PTD
3
27
0000
OLMC
26 XOR-2560 AC1-2632
0280
4
0320
OLMC
XOR-2561 AC1-2633
25
0600
5
0640
OLMC
XOR-2562 AC1-2634
24
0920
6
0960
OLMC
23 XOR-2563 AC1-2635
1240
7
1280
OLMC
XOR-2564 AC1-2636
21
1560
9
1600
OLMC
1880
20
10
XOR-2565 AC1-2637
1920
OLMC
19 XOR-2566 AC1-2638
2200
11
2240
OLMC
18 XOR-2567 AC1-2639 17
2703
2520
12 13
OE
16
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
5
Specifications GAL20LV8
Complex Mode
In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 20L8 and 20P8 devices with programmable polarity in each macrocell. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 18 & 26) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 2 and 16 are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 19 through Pin 25 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 18 and Pin 26 are configured to this function.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6
Specifications GAL20LV8
Complex Mode Logic Diagram
PLCC Package Pinout
2
2640 0 4 8 12 16 20 24 28 32 36 PTD
3
27
0000
OLMC
0280
26
4
0320
XOR-2560 AC1-2632
OLMC
25 XOR-2561 AC1-2633
0600
5
0640
OLMC
24 XOR-2562 AC1-2634
0920
6
0960
OLMC
1240
23
7
1280
XOR-2563 AC1-2635
OLMC
1560
21
9
1600
XOR-2564 AC1-2636
OLMC
1880
20
10
XOR-2565 AC1-2637
1920
OLMC
2200
19
11
XOR-2566 AC1-2638
2240
OLMC
2520
18
12 13
XOR-2567 AC1-2639 17 16
2703
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
7
Specifications GAL20LV8
Simple Mode
In the Simple mode, pins are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 14L8 and 16P6 devices with many permutations of generic output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. Pins 2 and 16 are always available as data inputs into the AND array. The "center" two macrocells (pins 21 & 23) cannot be used in the input configuration. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page.
Vcc
Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 21 & 23 can be configured to this function.
XOR
Combinatorial Output Configuration for Simple Mode
Vcc
XOR
- SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 21 & 23 are permanently configured to this function.
Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 21 & 23 can be configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
8
Specifications GAL20LV8
Simple Mode Logic Diagram
PLCC Package Pinout
2
2640 0 4 8 12 16 20 24 28 32 36 PTD
3
27
0000
OLMC
XOR-2560 AC1-2632 26
0280
4
0320
OLMC
XOR-2561 AC1-2633 25
0600
5
0640
OLMC
XOR-2562 AC1-2634 24
0920
6
0960
OLMC
XOR-2563 AC1-2635 23
1240
7
1280
OLMC
XOR-2564 AC1-2636 21
1560
9
1600
OLMC
XOR-2565 AC1-2637 20
1880
10
1920
OLMC
XOR-2566 AC1-2638 19
2200
11
2240
OLMC
XOR-2567 AC1-2639 18
2520
12 17 13 16
2703
64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB
SYN-2704 AC0-2705
9
Specifications GAL20LV8
Absolute Maximum Ratings(1)
Supply voltage VCC ................................... -0.5 to +4.6V Input voltage applied ................................ -0.5 to +5.6V I/O voltage applied ................................... -0.5 to +4.6V Off-state output voltage applied ............... -0.5 to +4.6V Storage Temperature ................................ -65 to 150C Ambient Temperature with Power Applied ........................................ -55 to 125C
1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage I/O High Voltage CONDITION MIN. Vss - 0.3 2.0 2.0 0V VIN VIL (MAX.) (Vcc-0.2)V VIN VCC Vcc VIN 5.25V Vcc VIN 4.6V IOL = MAX. Vin = VIL or VIH IOL = 500A Vin = VIL or VIH -- -- -- -- -- -- 2.4 Vcc-0.2V -- -- VCC = 3.3V VOUT = 0.5V TA= 25C -15 TYP.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX. 0.8 5.25 Vcc+0.5 -100 10 10 20 0.4 0.2 -- -- 8 -8 -80 UNITS V V V A A A mA V V V V mA mA mA
VIL VIH IIL1 IIH
Input or I/O Low Leakage Current Input or I/O High Leakage Current Input High Leakage Current I/O High Leakage Current
VOL VOH IOL IOH IOS2
Output Low Voltage
Output High Voltage
IOH = MAX. Vin = VIL or VIH IOH = -100A Vin = VIL or VIH
Low Level Output Current High Level Output Current Output Short Circuit Current
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0V VIH = 3.0V
Unused Inputs at VIL
--
45
70
mA
ftoggle = 1MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and TA = 25 C
10
Specifications GAL20LV8
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAMETER COM COM
TEST COND1. A A -- -- -- A
DESCRIPTION Input or I/O to Combinational Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled 1 1 -- 3 0 180
-3
-5
-7 UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd2 tco2 tcf3 tsu th
3.5 2.5 2 -- --
1 1 -- 4 0
5 3 2 -- --
1 1 -- 5 0 100
7.5 5 3 -- -- --
ns ns ns ns ns MHz
-- 142.8 --
fmax4
A A
200 250
-- --
166 166
-- --
125 125
-- --
MHz MHz
twh4 twl4 ten tdis
1) 2) 3) 4)
-- -- B B C C
2 2 -- -- -- --
-- -- 4.5 3.5 4.5 3.5
3 3 -- -- -- --
-- -- 6 5 6 5
4 4 -- -- -- --
-- -- 7.5 6.5 7.5 6.5
ns ns ns ns ns ns
Refer to Switching Test Conditions section. Minimum values for tpd and tco are not 100% tested but established by characterization. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. Refer to fmax Descriptions section. Characterized but not 100% tested.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance TYPICAL 5 5 UNITS pF pF TEST CONDITIONS VCC = 3.3V, VI = 0V VCC = 3.3V, VI/O = 0V
11
Specifications GAL20LV8
Switching Waveforms
INPUT or I/O FEEDBACK
VALID INPUT
tsu
INPUT or I/O FEEDBACK
CLK
th
VALID INPUT
tco
REGISTERED OUTPUT 1/fmax (external fdbk)
tpd
COMBINATIONAL OUTPUT
Combinatorial Output
Registered Output
INPUT or I/O FEEDBACK
OE
tdis
COMBINATIONAL OUTPUT
ten
REGISTERED OUTPUT
tdis
ten
Input or I/O to Output Enable/Disable
OE to Output Enable/Disable
twh
CLK 1/fmax (w/o fb)
twl
CLK 1/fmax (internal fdbk)
tcf
REGISTERED FEEDBACK
tsu
Clock Width
fmax with Feedback
12
Specifications GAL20LV8
fmax Descriptions
CL K
LOGIC ARR AY
R EG I S T E R
CLK
ts u
tc o
LOGIC ARRAY
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
tcf tpd
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC ARRAY REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
Switching Test Conditions
Output Load Conditions (see figure) Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 1.5ns 10% - 90% 1.5V 1.5V See Figure C Test Condition A B High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 50 50 50 50 50 CL 35pF 35pF 35pF 35pF 35pF
+1.45V
TEST POINT
R1
FROM OUTPUT (O/Q) UNDER TEST
Z0 = 50, CL = 35pF*
*CL includes test fixture and probe capacitance.
13
Specifications GAL20LV8
Electronic Signature
An electronic signature is provided in every GAL20LV8D device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum.
Output Register Preload
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GAL20LV8D devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically.
Security Cell
A security cell is provided in the GAL20LV8D devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
Input Buffers
GAL20LV8D devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL20LV8D input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/Os will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, VCC, or Ground. Doing this will tend to improve noise immunity and reduce ICC for the device. Typical Input Pull-up Characteristic
0 -10 Input Current (A) -20 -30 -40 -50 -60 -70 -80 0 1 2 3 0.5 1.5 2.5 Input Voltage (V) 3.5 4
Latch-Up Protection
GAL20LV8D devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots.
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
14
Specifications GAL20LV8
Power-Up Reset
Vcc (min.)
Vcc
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
FEEDBACK/EXTERNAL OUTPUT REGISTER
Device Pin Reset to Logic "1"
Circuitry within the GAL20LV8D provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some conditions must be met to
provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
Feedback
PIN
Vcc
Active Pull-up Circuit
Active Pull-up Circuit
Vcc
ESD Protection Circuit
Vref
Vcc
Tri-State Control
Vcc
Vref
PIN
Data Output
PIN
ESD Protection Circuit
Feedback (To Input Buffer)
Typical Output
Typ. Vref = Vcc Typical Input
Typ. Vref = Vcc
15
Specifications GAL20LV8
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
PT H->L
1.1
PT L->H
1.1
Normalized Tsu
RISE FALL
PT H->L
1.1
PT L->H
1
1
1
0.9
0.9
0.9
0.8 3.00 3.15 3.30 3.45 3.60
0.8 3.00
3.15
3.30
3.45
3.60
0.8 3.00
3.15
3.30
3.45
3.60
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.2 1.2
Normalized Tco vs Temp
1.2
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
Normalized Tsu
PT H->L
1.1
RISE
1.1
PT H->L
1.1
PT L->H
FALL
PT L->H
1
1
1
0.9
0.9
0.9
0.8 -55 -25 0 25 50 75 100 125
0.8 -55 -25 0 25 50 75 100 125
0.8 -55 -25 0 25 50 75 100 125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
Delta Tco (ns)
-0.1 -0.2 -0.3 -0.4 -0.5 1 2 3 4 5 6 7 8
-0.1 -0.2 -0.3 -0.4 -0.5 1 2 3 4 5 6 7 8
RISE FALL
RISE FALL
Number of Outputs Switching Delta Tpd vs Output Loading
18 16
Number of Outputs Switching
Delta Tco vs Output Loading
Delta Tpd (ns)
Delta Tco (ns)
14 10 6 2 -2 -6 0 50
RISE FALL
12 8 4 0 -4
RISE FALL
100
150
200
250
300
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
16
Specifications GAL20LV8
Typical AC and DC Characteristic Diagrams
Vol vs Iol
1 3 2.5 0.75 2.95
Voh vs Ioh
3
Voh vs Ioh
Voh (V)
Voh (V)
Vol (V)
2 1.5 1 0.5
0.5
2.9
0.25
2.85
0 0.00 5.00 10.00 15.00 20.00 25.00 30.00
0 0.00 5.00 10.00 15.00 20.00 25.00 30.00
2.8 0.00 1.00 2.00 3.00 4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.20 1.2
Normalized Icc vs Temp
1.40
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.10
1.1
Normalized Icc
-55 -25 0 25 50 75 100 125
1.30 1.20 1.10 1.00 0.90 0.80 0 25 50 75 100
1.00
1
0.90
0.9
0.80 3.00
0.8 3.15 3.30 3.45 3.60
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
10 0 5
Input Clamp (Vik)
Delta Icc (mA)
8
10
Iik (mA)
6 4 2 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
15 20 25 30 35 40 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
17

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