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PROFET(R) BTS 640 S2
Smart Sense High-Side Power Switch
Features
* Short circuit protection * Current limitation * Proportional load current sense * CMOS compatible input Package * Open drain diagnostic output * Fast demagnetization of inductive loads TO220-7-11 * Undervoltage and overvoltage shutdown with auto-restart and hysteresis * Overload protection * Thermal shutdown 1 Standard (staggered) * Overvoltage protection including load dump (with external GND-resistor) * Reverse battery protection (with external GND-resistor) * Loss of ground and loss of Vbb protection * Electrostatic discharge (ESD) protection
Product Summary Operating voltage On-state resistance Load current (ISO) Current limitation
Vbb(on) RON IL(ISO) IL(SCr)
5.0 ... 34 V 30 m 12.6 A 24 A
TO220-7-12
TO263-7-2
1 SMD
1 Straight
* C compatible power switch with diagnostic feedback for 12 V and 24 V DC grounded loads * All types of resistive, inductive and capacitve loads * Replaces electromechanical relays, fuses and discrete circuits
Application
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, proportional sense of load current, monolithically integrated in Smart SIPMOS technology. Providing embedded protective functions.
Block Diagram
4
+ V bb
Voltage source V Logic Voltage sensor
Overvoltage protection
Current limit
Gate protection
OUT
6, 7
IL
Charge pump Level shifter Rectifier
Limit for unclamped ind. loads Output Voltage detection Temperature sensor
3 1
IN
Current Sense Load
ST
ESD
Logic
R
O GND
5
R
IS
I IS
IS Signal GND GND
PROFET
Load GND
2
Semiconductor Group
Page 1 of 15
2003-Oct-01
BTS 640 S2
Pin 1 2 3 4 5 6&7 Symbol ST GND IN Vbb IS OUT (Load, L) Function Diagnostic feedback: open drain, invers to input level Logic ground Input, activates the power switch in case of logical high signal Positive power supply voltage, the tab is shorted to this pin Sense current output, proportional to the load current, zero in the case of current limitation of load current Output, protected high-side power output to the load. Both output pins have to be connected in parallel for operation according this spec (e.g. kILIS). Design the wiring for the max. short circuit current
Maximum Ratings at Tj = 25 C unless otherwise specified Parameter Supply voltage (overvoltage protection see page 4) Supply voltage for full short circuit protection
Tj Start=-40 ...+150C
Symbol Vbb Vbb VLoad dump3) IL Tj Tstg Ptot
Values 43 34 60 self-limited -40 ...+150 -55 ...+150 85 0,41 3,5 1.0 4.0 8.0 -10 ... +16 2.0 5.0 14
Unit V V V A C W J kV
Load dump protection1) VLoadDump = VA + Vs, VA = 13.5V
RI2)= 2 , RL= 1 , td= 200 ms, IN= low or high
Load current (Short circuit current, see page 5) Operating temperature range Storage temperature range Power dissipation (DC), TC 25 C Inductive load switch-off energy dissipation, single pulse
Vbb = 12V, Tj,start = 150C, TC = 150C const.
IL = 12.6 A, ZL = 4,2 mH, 0 : EAS IL = 4 A, ZL = 330 mH, 0 : EAS Electrostatic discharge capability (ESD) IN: VESD (Human Body Model) ST, IS: out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993 R=1.5k; C=100pF
Input voltage (DC) Current through input pin (DC) Current through status pin (DC) Current through current sense pin (DC)
see internal circuit diagrams page 8
VIN IIN IST IIS
V mA
1) 2) 3)
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 resistor in the GND connection is recommended). RI = internal resistance of the load dump test pulse generator VLoad dump is setup without the DUT connected to the generator according to ISO 7637-1 and DIN 40839
Semiconductor Group
Page 2
2003-Oct-01
BTS 640 S2 Thermal Characteristics
Parameter and Conditions Thermal resistance Symbol min ---chip - case: RthJC junction - ambient (free air): RthJA SMD version, device on PCB4): Values typ max -- 1.47 -75 33 -Unit K/W
Electrical Characteristics
Parameter and Conditions
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Load Switching Capabilities and Characteristics On-state resistance (pin 4 to 6&7)
IL = 5 A
Tj=25 C: RON Tj=150 C: VON(NL) IL(ISO) IL(NOM) IL(GNDhigh) ton toff dV /dton -dV/dtoff
--
27 54 50 12.6 4.5 -70 80 ---
30 60 ---8 150 200 1 1
m
Output voltage drop limitation at small load currents (pin 4 to 6&7), see page 14
IL = 0.5 A VON = 0.5 V, TC = 85 C Tj =-40...+150C:
-11.4 4.0 -25 25 0.1 0.1
mV A A mA s V/s V/s
Nominal load current, ISO Norm (pin 4 to 6&7) Nominal load current, device on PCB4)
TA = 85 C, Tj 150 C VON 0.5 V,
Output current (pin 6&7) while GND disconnected or GND pulled up, Vbb=30 V, VIN= 0, see diagram page
9; not subject to production test, specified by design Turn-on time IN to 90% VOUT: Turn-off time IN to 10% VOUT: RL = 12 , Tj =-40...+150C
Slew rate on
10 to 30% VOUT, RL = 12 , Tj =-40...+150C 70 to 40% VOUT, RL = 12 , Tj =-40...+150C
Slew rate off
4)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb connection. PCB is vertical without blown air.
Semiconductor Group
Page 3
2003-Oct-01
BTS 640 S2
Parameter and Conditions
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Operating Parameters Operating voltage 5) Undervoltage shutdown Undervoltage restart
Vbb(on) Tj =-40...+150C: Vbb(under) Tj =-40...+25C: Vbb(u rst) Tj =+150C: Undervoltage restart of charge pump see diagram page 13 Tj =-40...+25C: Vbb(ucp) Tj =25...150C: Undervoltage hysteresis Vbb(under)
Tj =-40...+150C: Vbb(under) = Vbb(u rst) - Vbb(under)
5.0 3.2 ----34 33 -41 43 -----
--4.5 4.7 -0.5 --1 -47 4 12 -1.2
34 5.0 5.5 6.0 6.5 7.0 -43 ---52 15 25 10 3
V V V V V V V V V A A mA
Overvoltage shutdown Overvoltage restart Overvoltage hysteresis Overvoltage protection6)
Ibb=40 mA
Vbb(over) Tj =-40...+150C: Vbb(o rst) Tj =-40...+150C: Vbb(over) Tj =-40C: Vbb(AZ) Tj =+25...+150C
Tj =-40...+150C:
Standby current (pin 4) Tj=-40...+25C: Ibb(off) Tj= 150C: IL(off) Off state output current (included in Ibb(off))
VIN=0 VIN=0, Tj =-40...+150C:
Operating current (Pin 2)7), VIN=5 V
IGND
5) 6)
7)
At supply voltage increase up to Vbb= 4.7 V typ without charge pump, VOUT Vbb - 2 V Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 resistor in the GND connection is recommended). See also VON(CL) in table of protection functions and circuit diagram page 9. Add IST, if IST > 0, add IIN, if VIN>5.5 V
Semiconductor Group
Page 4
2003-Oct-01
BTS 640 S2
Parameter and Conditions
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Protection Functions8) Initial peak short circuit current limit (pin 4 to 6&7) IL(SCp) Tj =-40C: Tj =25C: =+150C: Tj Repetitive short circuit shutdown current limit IL(SCr)
Tj = Tjt (see timing diagrams, page 12)
48 40 31 --
56 50 37 24 -47 -10 -600
65 58 45 --52 --32 --
A
A V C K V mV
Output clamp (inductive load switch off) Tj =-40C: Tj =+25..+150C: Thermal overload trip temperature Thermal hysteresis Reverse battery (pin 4 to 2) 9) Reverse battery voltage drop (Vout > Vbb) IL = -5 A Tj=150 C:
at VOUT = Vbb - VON(CL); IL= 40 mA,
VON(CL) Tjt
Tjt
-Vbb -VON(rev)
41 43 150 ----
Diagnostic Characteristics Current sense ratio10), static on-condition,
VIS = 0...5 V, Vbb(on) = 6.511)...27V, Tj kILIS = IL / IIS
= -40C, IL = 5 A: kILIS Tj= -40C, IL= 0.5 A:
4550 3300 4550 4000
5000 5000 5000 5000 6.1 ----
6000 8000 5550 6500 6.9 1 15 10 V A
Tj= 25...+150C, IL= 5 A: , Tj= 25...+150C, IL = 0.5 A: Current sense output voltage limitation
Tj = -40 ...+150C IIS = 0, IL = 5 A:
VIS(lim)
5.4 0 0 0
Current sense leakage/offset current Tj = -40 ...+150C VIN=0, VIS = 0, IL = 0: IIS(LL) VIN=5 V, VIS = 0, IL = 0: IIS(LH) VIN=5 V, VIS = 0, VOUT = 0 (short circuit): IIS(SH)12 )
8)
9)
10)
11) 12)
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. Requires 150 resistor in GND connection. The reverse load current through the intrinsic drain-source diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 2 and circuit page 9). This range for the current sense ratio refers to all devices. The accuracy of the kILIS can be raised at least by a factor of two by matching the value of kILIS for every single device. In the case of current limitation the sense current IIS is zero and the diagnostic feedback potential VST is High. See figure 2b, page 11. Valid if Vbb(u rst) was exceeded before. not subject to production test, specified by design
Semiconductor Group
Page 5
2003-Oct-01
BTS 640 S2
Parameter and Conditions
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max --300
Unit
Current sense settling time to IIS static10% after positive input slope13) , IL = 0 5 A,
Tj= -40...+150C
tson(IS)
s s s V k
Current sense settling time to 10% of IIS static after negative input slope13) , IL = 5 0A, tsoff(IS)
Tj= -40...+150C
--2 5
30 10 3 15
100 -4 40
Current sense rise time (60% to 90%) after change of load current13) , IL = 2.5 5A tslc(IS) Open load detection voltage14) (off-condition)
Tj=-40..150C:
VOUT(OL) RO
Internal output pull down
(pin 6 to 2), VOUT=5 V, Tj=-40..150C
Input and Status Feedback15) Input resistance
see circuit page 8
RI
3,0 -1.5 -1 20 ---5.4 ----
4,5 --0.5 -50 400 13 1 6.1 ----
7,0 3.5 --50 90 ---6.9 0.4 0.7 2
k V V V A A s s s V
Input turn-on threshold voltage Tj =-40..+150C: VIN(T+) Input turn-off threshold voltage Tj =-40..+150C: VIN(T-) Input threshold hysteresis VIN(T) Off state input current (pin 3), VIN = 0.4 V Tj =-40..+150C IIN(off) On state input current (pin 3), VIN = 5 V
Tj =-40..+150C
IIN(on) td(ST OL3) tdon(ST) tdoff(ST)
Delay time for status with open load
after Input neg. slope (see diagram page 13)
Status delay after positive input slope13)
Tj=-40 ... +150C:
Status delay after negative input
slope13) Tj=-40 ... +150C:
Status output (open drain) Zener limit voltage Tj =-40...+150C, IST = +1.6 mA: VST(high) ST low voltage Tj =-40...+25C, IST = +1.6 mA: VST(low) Tj = +150C, IST = +1.6 mA: Status leakage current, VST = 5 V, Tj=25 ... +150C: IST(high)
A
13) 14)
not subject to production test, specified by design External pull up resistor required for open load detection in off state. 15) If a ground resistor R GND is used, add the voltage drop across this resistor.
Semiconductor Group
Page 6
2003-Oct-01
BTS 640 S2 Truth Table
Input level Normal operation Currentlimitation Short circuit to GND Overtemperature Short circuit to Vbb Open load Undervoltage Overvoltage Negative output voltage clamp L = "Low" Level H = "High" Level L H L H L H L H L H L H L H L H L Output level L H L H L L16) L L H H L19) H L L L L L Status level H L H H H H H H L17) L H (L20)) L H L H L H Current Sense IIS 0 nominal 0 0 0 0 0 0 0 X = don't care Z = high impedance, potential depends on external circuit Status signal after the time delay shown in the diagrams (see fig 5. page 12...13)
16) 17) 18) 19) 20)
The voltage drop over the power transistor is Vbb-VOUT>typ.3V. Under this condition the sense current IIS is zero An external short of output to Vbb, in the off state, causes an internal current from output to ground. If RGND is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious. Low ohmic short to Vbb may reduce the output current IL and therefore also the sense current IIS. Power Transistor off, high impedance with external resistor between pin 4 and pin 6&7
Semiconductor Group
Page 7
2003-Oct-01
BTS 640 S2
Terms
V 4 3 IN ST Ibb IL VON OUT PROFET OUT GND 2 R GND I GND 7 V 6
Status output
+5V
bb
I IN I ST I IS
Vbb
R ST(ON)
ST
1
V IN
IS VST 5 V IS
OUT
GND
ESDZD
ESD-Zener diode: 6.1 V typ., max 5 mA; RST(ON) < 440 at 1.6 mA, The use of ESD zener
diodes as voltage clamp at DC conditions is not recommended.
Input circuit (ESD protection)
R IN I
Current sense output
V IS
I
ESD-ZD I GND
IS
I
I IS ESD-ZD R GND IS
The use of ESD zener diodes as voltage clamp at DC conditions is not recommended.
ESD-Zener diode: 6.1 V typ., max 14 mA; RIS = 1 k nominal
Inductive and overvoltage output clamp
+ V bb V Z
VON
OUT GND
PROFET
VON clamped to 47 V typ.
Semiconductor Group
Page 8
2003-Oct-01
BTS 640 S2
Overvoltage protection of logic part
+ 5V + V bb
GND disconnect
V bb 3 1 IN ST IS 4 Ibb
R ST
IN ST IS
RI Logic
V
Z2
Vbb OUT PROFET OUT GND 2 V GND
6
7
RV R IS
V Z1 GND
5
VVV IN ST IS
R GND
Signal GND
Any kind of load. In case of Input=high is VOUT VIN - VIN(T+) . Due to VGND >0, no VST = low signal available.
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RI= 4 k typ, RGND= 150 , RST= 15 k, RIS= 1 k, RV= 15 k,
GND disconnect with GND pull up
4 Vbb OUT PROFET OUT IS GND 2 7
Reverse battery protection
+ 5V
3
IN ST
6
- Vbb
R ST
IN ST IS
1 5
RI
Logic VZ1
Power Inverse Diode OUT
RV R IS
GND
V bb
V VSTV IN IS
V GND
Any kind of load. If VGND > VIN - VIN(T+) device stays off Due to VGND >0, no VST = low signal available.
RL
Power GND
RGND
Signal GND
Vbb disconnect with energized inductive load
4 high 3 1 5 IN ST IS Vbb OUT PROFET OUT GND 2 7 6
The load RL is inverse on, temperature protection is not active RGND= 150 , RI= 4 k typ, RST 500 , RIS 200 , RV 500 ,
Open-load detection
OFF-state diagnostic condition: VOUT > 3 V typ.; IN low
V bb
V bb
R
EXT
Normal load current can be handled by the PROFET itself.
OFF Out ST Logic
V OUT
R
O
Signal GND
Semiconductor Group
Page 9
2003-Oct-01
BTS 640 S2
Vbb disconnect with charged external inductive load
4 high 3 1 5 IN ST IS Vbb OUT PROFET OUT GND 2 RL V bb L 7 6 D
If other external inductive loads L are connected to the PROFET, additional elements like D are necessary.
Inductive Load switch-off energy dissipation
E bb E AS ELoad OUT PROFET OUT IS GND 2 ER 6 7 EL
4 3 1 IN ST Vbb
=
Vbb
5
Energy stored in load inductance: EL = 1/2*L*I L While demagnetizing load inductance, the energy dissipated in PROFET is EAS= Ebb + EL - ER= VON(CL)*iL(t) dt, with an approximate solution for RL > 0 : EAS= IL* L IL*RL *(V + |VOUT(CL)|)* ln (1+ ) |VOUT(CL)| 2*RL bb
2
Semiconductor Group
Page 10
2003-Oct-01
BTS 640 S2
Figure 2a: Switching a lamp
Timing diagrams
IN
Figure 1a: Switching a resistive load, change of load current in on-condition:
ST
IN ST
V
t don(ST)
OUT
t doff(ST)
VOUT t on tslc(IS) t off t slc(IS)
IL
IL
I IS t
Load 1 IIS t son(IS)
Load 2
Figure 2b: Switching a lamp with current limit:
IN
t soff(IS)
t
The sense signal is not valid during settling time after turn or change of load current.
ST
Figure 1b: Vbb turn on:
IN VOUT
Vbb IL
I
L
IIS t I IS
ST t
proper turn on under all conditions
Semiconductor Group
Page 11
2003-Oct-01
BTS 640 S2
Figure 2c: Switching an inductive load:
IN IN ST ST VOUT IL
Figure 4a: Overtemperature: Reset if Tj IL
I IS
IIS t
TJ
t
Figure 3a: Short circuit: shut down by overtempertature, reset by cooling Figure 5a: Open load: detection in ON-state, open load occurs in on-state
IN
IL
IL(SCp) I L(SCr)
IN
ST
VOUT I IS IL normal open normal
ST
t IIS t
Heating up may require several milliseconds, depending on external conditions IL(SCp) = 50 A typ. increases with decreasing temperature.
Semiconductor Group
Page 12
2003-Oct-01
BTS 640 S2
Figure 6b: Undervoltage restart of charge pump Figure 5b: Open load: detection in ON- and OFF-state (with REXT), turn on/off to open load
V on VON(CL)
IN
td(ST OL3)
off-state
on-state
V
bb(over)
V
OUT
V
bb(u rst)
V
bb(o rst)
I L open load I IS
V V
bb(under)
bb(u cp)
t
charge pump starts at Vbb(ucp) =4.7 V typ.
Figure 7a: Overvoltage: Figure 6a: Undervoltage:
IN IN ST not defined Vbb
ST
V ON(CL)
V
bb(over)
V
bb(o rst)
V bb V I
bb(under)
Vbb(u cp) Vbb(u rst) IL
L
I IIS t
IS t
Semiconductor Group
Page 13
2003-Oct-01
off-state
V bb
ST
BTS 640 S2
Figure 8b: Current sense ratio21: Figure 8a: Current sense versus load current:
1.3 [mA] 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 IL 5 [A] 6 0 [A] I L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 5000 10000 15000 k ILIS
I IS
Figure 9a: Output voltage drop versus load current:
VON
[V]
0.2 RON
0.1
VON(NL) IL 0 1 2 3 4 5 6 7 [A] 8
0.0
21
This range for the current sense ratio refers to all devices. The accuracy of the kILIS can be raised at least by a factor of two by matching the value of kILIS for every single device.
Semiconductor Group
Page 14
2003-Oct-01
BTS 640 S2
Package and Ordering Code
All dimensions in mm
Standard (=staggered): P-TO220-7-11
Sales code Ordering code
10 0.2 9.8 0.15 8.5 3.7 -0.15
1)
Straight: P-TO220-7-12
Sales Code Ordering code
10 0.2 9.8 0.15 A B 4.4 1.27 0.1
BTS640S2 Q67060-S6307-A5
A 4.4 1.27 0.1
BTS640S2 S Q67060-S6307-A7
8.5 3.7 -0.15
1)
170.3 15.650.3
1)
15.650.3
17 0.3
2.8 0.2
13.4
2.8 0.2
1)
13.4
0.05
9.25 0.2
0.05
8.6 0.3
110.5
10.2 0.3
C 0...0.15 1.27
3.70.3
C
0.5 0.1 3.9 0.4
13 0.5
0...0.15 1.27
7x 0.6 0.1 0.25
M
2.4 8.4 0.4
1)
7x 0.6 0.1 0.25
M
0.5 0.1 2.4 ABC
AC
1)
Typical All metal surfaces tin plated, except area of cut.
Typical All metal surfaces tin plated, except area of cut.
SMD: P-TO263-7-2 (tape&reel)
Sales code Ordering code
10 0.2 9.8 0.15 A 8.5
1)
BTS640S2 G Q67060-S6307-A6
4.4 1.27 0.1 B 0.1 2.4
Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 Munchen (c) Infineon Technologies AG 2001 All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved.
10.3
0.05
9.25 0.2
(15)
1.3 0.3
8 1)
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
0...0.15 7x0.60.1 6x1.27
4.7 0.5
2.7 0.3
0.5 0.1
8 max.
0.25
1) M
AB
0.1
Typical All metal surfaces tin plated, except area of cut.
Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Ordering code
Q67060-S6307-A6
Semiconductor Group
Page 15
2003-Oct-01
9.25 0.2

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