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APA4838
Stereo 2.8W Audio Power Amplifier with DC Volume Control and Selectable Gain
Features * * * * * * *
Operating Voltage : 4.5V to 5V Stereo switchable bridged/single-ended power amplifiers DC Volume Control Interface , 0dB to -78dB with precision scale Supply Current , IDD = 15mA at Stereo BTL Low Shutdown Current , IDD = 0.7A Bridge-Tied Load (BTL) or Single-Ended-(SE) Modes Operation Output Power at 1% THD+N , VDD=5V
General Description
The APA4838 is a monolithic integrated circuit , which provides DC volume control , and a stereo bridged audio power amplifiers capable of producing 2.8W (2.3W) into 3 with less than 10% (1.0%) THD+N. APA4838 includes a DC volume control , stereo bridge-tied and single-ended audio power amplifiers , stereo docking outputs , and a selectable gain control , that makes it optimally fittable for notebook PC , multimedia monitors , and other portable applications. The attenuator range of the volume control in APA4838 is from 0dB (DC_Vol=0.8VDD) to -78dB (DC_Vol=0V) with 31 steps. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated in APA4838 , that reduces pops and clicks noise during power up or shutdown mode operation , and protects the chip from being destroyed by over temperature failure. To simplify the audio system design , APA4838 combines a stereo bridgetied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip , where both modes are easily switched by the HP Sense input control pin signal. Besides the low supply current design to increase the efficiency of the amplifiers , APA4838 also features a shutdown function which keeps the supply current only 0.7A (typ).
*
- 2.3W/Ch (typ) into a 3 Load - 2.0W/Ch (typ) into a 4 Load - 1.2W/Ch (typ) into a 8 Load
Output Power at 10% THD+N , VDD=5V
- 2.8W/Ch (typ) into a 3 Load - 2.3W/Ch (typ) into a 4 Load - 1.5W/Ch (typ) into a 8 Load
* * * * * *
Single-ended mode at 1.0% THD+N
- 95mW/Ch (typ) into 32 Load
Depop Circuitry Integrated Thermal shutdown protection and over current protection circuitry High supply voltage ripple rejection PC99 Compliant 28-pin TSSOP-P (with enhanced thermal pad) power package available
Pin Description
GN D Shutdown G ain Select M ode M ute VDD DC V ol GN D Right Dock Right In 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Right O ut + V DD Right O ut Right G ain 2 Right G ain 1 GN D BY PA SS HP Sense GN D Left G ain 1 Left G ain 2 Left O ut V DD Left O ut +
Applications * * *
Notebook and Desktop Computers Multimedia Monitors Portable Applications
Beep In Left In Left Dock GN D
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003 1 www.anpec.com.tw
APA4838
Ordering and Marking Information
APA4838
H a n d lin g C o d e T em p. R an g e P ac ka ge C od e P ackage C ode R : T S S O P -P Tem p. R ange I : -4 0 to 8 5 C H a n d lin g C o d e TU : Tube
TR : Tape & R eel
A P A 4838 R :
A P A 4838 XXXXX
X X X X X - D a te C o d e
Block Diagram
Gain Select 20K 20K
Left Gain1
Mode Mute HP Sense DC_Vol Left Dock 20K Left Audio Input 200K 200K Right Audio Input 20K 20K
Mode Control
Left Gain2
20K 10K
0.068F
10K
- Left Out + Bias + Bias + + Right Out 20K Power Management 10K 10K 20K Right Gain1 Right Gain2 Click and Pop Suppression Circuitry 20K
2
0.33F Beep In 0.33F Right In Right Dock 20K Shutdown VDD GND Beep Detect
Bypass
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
+ -
+
+ Volume Control 31 steps
Left In
20K
20K
+ Left Out
20K - Right Out
0.068F
20K
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APA4838
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol VDD VIN TA TJ TSTG TS VESD PD Parameter Rating Supply Voltage -0.3 to 6 Input Voltage Range, HP sense, Shutdown, -0.3 to VDD+0.3 Mute, Mode, Gain Select Operating Ambient Temperature Range -40 to 85 Maximum Junction Temperature Internally Limited*1 Storage Temperature Range -65 to +150 Soldering Temperature,10 seconds 260 Electrostatic Discharge -2000 to 2000*2 Power Dissipation Internally Limited Unit V V C C C C V W
Note: 1.APA4838 integrated internal thermal shutdown protection when junction temperature ramp up to 150C 2.Human body model: C=100pF, R=1500, 3 positives pulse plus 3 negative pulses 3.Machine model: C=200pF, L=0.5F, 3 positive pulses plus 3 negative pulses
Recommended Operating Conditions
Min. Supply Voltage, VDD High level threshold voltage, VIH Low level threshold voltage, VIL Common mode input voltage, VICM Shutdown, Mute, Mode, Gain Select HP Sense Shutdown, Mute, Mode, Gain Select HP Sense VDD-1.0 4.5 2 4 1.0 3 Max. 5.5 Unit V V V V
Thermal Characteristics
Symbol R THJA Parameter Thermal Resistance from Junction to Ambient in Free Air TSSOP-P* 45 K/W Value Unit
* 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P package with solder on the printed circuit board.
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APA4838
Electrical Characteristics
Electrical Characteristics for Entire IC
The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25C
Symbol VDD IDD ISD
Parameter Supply Voltage Quiescent Power Supply Current Shutdown Current
Test Conditions
Min. 4.5
APA4838 Typ. Max. 5.5 15 0.7 25 2.0
Unit V mA A
VIN=0V, IO=0A VPIN 2= VDD
Electrical Characteristics for Volume Attenuators
The following specifications apply for VDD= 5V. Limits apply for TA= 25C
Symbol CRANGE AM
Parameter Attenuator Range Mute Attenuation
Test Conditions Gain with VPIN 7=5V Attenuation with VPIN 7=0V VPIN 5=5V, Bridged Mode VPIN 5=5V, Single-Ended Mode
Min.
APA4838 Typ. Max. 0.5 -65 -78 -70 -70
Unit dB dB
Electrical Characteristics for BTL Mode Operation
The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25C
Symbol VOS PO
Parameter Output Offset Voltage Output Power
Test Conditions
THD+N
PSRR XTALK SNR VN
VIN=0V THD=1%, f=1kHz RL=3 RL=4 RL=8 THD=10%, f=1kHz RL=8 Total Harmonic Distortion + Noise AVD=2, f=1kHz RL=4 , PO =1.5W RL=8 , PO=1W VRIPPLE=100mVRms CB=2.2F, Power Supply Rejection Ratio RL=8, f=1kHz CB=2.2F, f=1kHz, RL=8 Channel Separation VDD=5V, PO =1.1W, RL=8,A-Wtd Signal-to-Noise Ratio Filter RL=8,A-Wtd Filter Output Noise Voltage
APA4838 Typ. 5 2.3 2.0 1.2 1.5 0.07 0.07 70 90 95 30
Unit mV W
% dB dB dB V
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APA4838
Electrical Characteristics (Cont.)
Electrical Characteristics for SE Mode Operation (Cont.)
The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25C
Symbol VOS PO THD+N PSRR XTALK SNR VN
Parameter Output Offset Voltage Output Power VIN=0V THD=1%, THD=10%,
Test Conditions f=1kHz, RL=32 f=1kHz, RL=32
APA4838 Typ. 5 95 110 0.05 0.07 52 90 102 20
Unit mV mW % % dB dB dB V
Total Harmonic Distortion AV= 1 , VOUT=1VRMS, RL=10k, f=1kHz plus Noise PO =75mW, RL=32, AV= 1, f=1kHz Power Supply Rejection VRIPPLE=100mVRMS , f=120Hz, CB=2.2F Ratio Channel Separation CB=2.2F, RL=8 , f=1kHz Signal-to-Noise Ratio PO =75mW, RL=32, A-Wtd Filter Output Noise Voltage RL=32, A-Wtd Filter
Pin Description
Pin Name GND Shutdown Gain Select Mode Mute VDD DC_Vol Right Dock Right In Beep In Left In Left Dock Left Out + Left Out Left Gain 2 Left Gain 1 HP Sense No 1, 8, 14, 20, 23 2 3 4 5 6, 16, 27 7 9 10 11 12 13 15 17 18 19 21 I/O Ground connection for circuitry. I Shutdown mode control signal input, place entire IC in shutdown mode when held high, Idd=0.7uA I Gain select input pin, logic high will switch the amplifier to external gain mode, and logic low will switch to internal unity gain. I Mode select input pin, fixed gain when logic L and gain adjustable mode when logic H. I Mute control input pin, active H. Supply voltage input pin I Volume control function input pin. O Right docking output pin I Right channel audio input pin I Beep signal input pin I Left channel audio input pin O Right docking output pin O Left channel positive output pin O Left channel negative output pin Connect pin 2 of the external gain setting resistor for left channel Connect pin 1 of the external gain setting resistor for left channel I Headphone sense control pin
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Description
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
APA4838
Pin Description (Cont.)
Pin Name Bypass Right Gain 1 Right Gain 2 Right Out Right Out + No 22 24 25 26 28 I/O Bypass pin Connect pin 1 of the external gain setting resistor for right channel Connect pin 2 of the external gain setting resistor for right channel O Right channel negative output pin O Right channel positive output pin Description
Truth Table for Logic Inputs
Mute
0 0 0 0 0 0 0 0 1
Gain HP Mode Select Sense
0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 X
Gain Mode of Power Amplifier
Unity Gain Setting Unity Gain Setting Unity Gain Setting Unity Gain Setting External Gain Setting External Gain Setting External Gain Setting External Gain Setting -
DC Vol. Control
Fixed Level Fixed Level Adjustable Adjustable Fixed Level Fixed Level Adjustable Adjustable -
BTL Output
Vol. Fixed Muted Vol. Adjustable Muted Vol. Fixed Muted Vol. Adjustable Muted Muted
SE Output
Vol. Fixed Vol. Adjustable Vol. Fixed Vol. Adjustable Muted
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APA4838
Typical Application Circuit
VDD
1 F
VDD
R_var
DC Vol Control
VDD 100K Internal gain select 3
20K
20K
HP Sense 100K 21 5 Mute Mode 4 13
7
19
18
To Control Pin on Headphone Jack
Mode Control
20K 10K 10K 0.068F
Left Dock Left Audio Input 20K 20K 200K Beep In Right Audio Input 200K Right In Left In + 0.33F
- Left Out
11
Bias
10 20K + 0.33F 20K Right Dock VDD
Bias 28
9 20K
1,8,14,20,23 GND Bypass 22
10K Click and Pop Suppression Circuitry 2 24
0.1F
0.1F
0.1F
2.2F
Shutdown 20K 20K
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-
Power Management
+
6,16,27
10K 20K 0.068F 25
+ -
Beep Detect
+
+ Volume Control 31 steps
12
+ 20K 20K
17
+ 220F 1K Control Pin Pin Ring
15
+ Left Out To HP sense Circuit + Right Out Tip Sleeve
+
Headphone Jack 20K 26 + 220F 1K - Right Out
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APA4838
Application Information
Volume Control Table
Gain (dB) Low 0 -1 -2 -3 -4 -5 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -78 77.5% 75.0% 72.5% 70.0% 67.5% 65.0% 62.5% 60.0% 57.5% 55.0% 52.5% 50.0% 47.5% 45.0% 42.5% 40.0% 37.5% 35.0% 32.5% 30.0% 27.5% 25.0% 22.5% 20.0% 17.5% 15.0% 12.5% 10.0% 7.5% 5.0% 0.0%
Voltage Range (% of Vdd) High 100.00% 78.5% 76.25% 73.75% 71.25% 68.75% 66.25% 63.75% 61.25% 58.75% 56.25% 53.75% 51.25% 48.75% 46.25% 43.75% 41.25% 38.75% 36.25% 33.75% 31.25% 28.75% 26.25% 23.75% 21.25% 18.75% 16.25% 13.75% 11.25% 8.75% 6.25% Recommended 100.000% 76.875% 74.375% 71.875% 69.375% 66.875% 64.375% 61.875% 59.375% 56.875% 54.375% 51.875% 49.375% 46.875% 44.375% 41.875% 39.375% 36.875% 34.375% 31.875% 29.375% 26.875% 24.675% 21.875% 19.375% 16.875% 14.375% 11.875% 9.375% 6.875% 0.000% Low 3.875 3.750 3.625 3.500 3.375 3.250 3.125 3.000 2.875 2.750 2.625 2.500 2.375 2.250 2.125 2.000 1.875 1.750 1.625 1.500 1.375 1.250 1.125 1.000 0.875 0.750 0.625 0.500 0.375 0.250 0.000
Voltage Range (Vdd=5V) High 5.000 3.938 3.813 3.688 3.563 3.438 3.313 3.188 3.063 2.938 2.813 2.688 2.563 2.438 2.313 2.188 2.063 1.938 1.813 1.688 1.563 1.438 1.313 1.188 1.063 0.937 0.812 0.687 0.562 0.437 0.312 Recommended 5.000 3.844 3.719 3.594 3.469 3.344 3.219 3.094 2.969 2.844 2.719 2.594 2.469 2.344 2.219 2.094 1.969 1.844 1.719 1.594 1.469 1.344 1.219 1.094 0.969 0.844 0.719 0.594 0.469 0.344 0.000
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APA4838
Typical Characteristics
THD+N vs. Frequency
10
VDD=5V RL=3 Po=1.8W BTL Av=2 Av=4 Av=8
THD+N vs. Output Power
10
VDD=5V RL=3 Av=2 BTL f=20KHz
THD+N (%)
THD+N (%)
1
1
0.1
0.1
f=20Hz
f=1KHz
0.01 20
100
1k
20k
0.01 10m
100m
1
3
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
10
VDD=5V RL=4 Po=1.5W BTL
THD+N vs. Output Power
10
VDD=5V RL=4 Av=2 BTL
THD+N (%)
1
Av=2 Av=4 Av=8
1
0.1
THD+N (%)
f=20KHz
0.1
f=1KHz
f=20Hz
0.01 20
100
1k
20k
0.01 100m
500m
1
3
Frequency (Hz)
Output Power (W)
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APA4838
Typical Characteristics (Cont.)
THD+N vs. Frequency
10
VDD=5V RL=8 Po=1.0W BTL
THD+N vs. Output Power
10
VDD=5V RL=8 Av=2 BTL
THD+N (%)
THD+N (%)
1
Av=2 Av=4 Av=8
1
f=20KHz
0.1
0.1
f=1KHz f=20Hz
0.01 20
100
1k
20k
0.01 10m
100m
1
2
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
10
VDD=5V RL=8 Po=250mW SE
THD+N vs. Output Power
10
VDD=5V RL=8 Av=1 SE
THD+N (%)
Av=1 Av=2 Av=4
THD+N (%)
1
1
f=20KHz
0.1
0.1
f=1KHz f=20Hz
0.01 20 100 1k 20k
0.01 10m
100m
500m
Frequency (Hz)
Output Power (W)
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APA4838
Typical Characteristics (Cont.)
THD+N vs. Frequency
10
VDD=5V RL=16 Po=150mW SE
THD+N vs. Output Power
10
VDD=5V RL=16 Av=1 SE
THD+N (%)
Av=1 Av=2
THD+N (%)
1
1
f=20KHz
0.1
Av=4
0.1
f=20Hz f=1KHz
0.01 20
100
1k
20k
0.01 10m
100m
300m
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
10
VDD=5V RL=32 Po=75mW SE
THD+N vs. Output Power
10
VDD=5V RL=32 Av=1 SE
THD+N (%)
1
1
THD+N (%)
f=20Hz f=20KHz
0.1
Av=1 Av=2 Av=4
0.1
f=1KHz
0.01 20 100 1k 20k
0.01 10m
50m
100m 200m
Frequency (Hz)
Output Power (W)
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APA4838
Typical Characteristics (Cont.)
THD+N vs. Frequency
10
VDD=5V RL=10K Vo=1VRMS SE
THD+N vs. Output Swing
10
VDD=5V RL=10K Av=1 SE
THD+N (%)
Av=1
THD+N (%)
1
1
0.1
Av=2 Av=4
0.1
f=20Hz f=20KHz f=1KHz
0.01 20
100
1k
20k
0.01 100m
500m
2
3
Frequency (Hz)
Output Swing (VRHS)
Crosstalk vs. Frequency
+0 -20 -40 -60 -80
R-ch to L-ch VDD=5V RL=8 Po=1.0W Av=2 BTL
Crosstalk vs. Frequency
VDD=5V RL=32 -20 Po=75mW Av=2 SE
+0
Crosstalk (dB)
Crosstalk (dB)
-40 -60 -80 -100
R-ch to L-ch L-ch to R-ch
-100
L-ch to R-ch
-120 20 100 1k 20k
-120 20 100 1k 20k
Frequency (Hz)
Frequency (Hz)
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APA4838
Typical Characteristics (Cont.)
Noise Floor vs. Frequency
100
Noise Floor vs. Frequency
100
No Filter
Noise Floor (VRMS)
Noise Floor (VRMS)
No Filter
A-Weight
10
10
A-Weight
VDD=5V RL=8 Av=2 BTL
1 20 100 1k 20k
VDD=5V RL=32 Av=1 SE
1 20 100 1k 20k
Frequency (Hz)
Frequency (Hz)
Supply Current vs. Supply Voltage
25 2 1 .8
Power Dissipation vs. Output Power
Power Dissipation (W)
Supply Current (mA)
20
1 .6 1 .4 1 .2 1 0 .8 0 .6 0 .4 0 .2 0 0 0 .5 1 1 .5
RL=8
RL=3
15
BTL
RL=4
10
SE
5
No Load
VDD=5V Av=2 BTL
0 1 1 .5 2 2 .5 3 3 .5 4 4 .5 5 5 .5
2
2 .5
Supply Voltage (V)
Output Power (W)
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APA4838
Typical Characteristics (Cont.)
Power Dissipation vs. Output Power
0 .2 5
4 0 -4 -8
Gain vs. Voltage, 5V, SE
Power Dissipation (W)
0 .2
RL=8
-1 2
Output Gain (dB)
VDD=5V Av=2 SE
-1 6 -2 0 -2 4 -2 8 -3 2 -3 6 -4 0 -4 4 -4 8 -5 2 -5 6 -6 0 -6 4 -6 8 -7 2 -7 6 -8 0
0 .1 5
0 .1
RL=16
0 .0 5
RL=32
0 0 0 .0 5 0 .1 0 .1 5 0 .2 0 .2 5 0 .3 0 .3 5 0 .4
VDD=5V AV=1 SE
0 0 .5 1 1 .5 2 2 .5 3 3 .5 4 4 .5 5
Output Power (W)
DC Vol Input Voltage (V)
Output Power vs. Supply Voltage
2 .2 5 2 160 140
Output Power vs. Supply Voltage
Output Power (W)
1 .5
THD+N=10%
Output Power (mW)
120 100
THD+N=10%
1
THD+N=1%
80 60 40 20 0
RL=32 Av=1 SE THD+N=1%
0 .5
RL=8 Av=2 BTL
0 2 .5 3 3 .5 4 4 .5 5 5 .5
2 .5
3
3 .5
4
4 .5
5
5 .5
Supply Voltage (V)
Supply Voltage (V)
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APA4838
Typical Characteristics (Cont.)
Output Power vs. Load Resistance
3 2.5
VDD=5V Av=2 BTL
Output Power vs. Load Resistance
800 700
VDD=5V Av=1 SE
2 1.5 1 0.5
THD+N=1%
Output Power (mW)
Output Power (W)
600 500 400 300 200 100 0
THD+N=10% THD+N=1%
THD+N=10%
0 48 16 24 32 40 48 56 64
48
16
24
32
40
48
56
64
Load Resistance ()
Load Resistance ()
PSRR vs. Frequency
+0 6
PSRR vs. Frequency
+0
VDD=5V Vin=100mVRMS RL=8 -20 Cbypass=2.2F Av=1 SE
Ripple Rejection Ratio (dB)
-20
-40
Ripple Rejection Ratio (dB)
VDD=5V Vin=100mVRMS RL=8 Cbypass=2.2F Av=2 BTL
-40
Gain Adjustable
Gain Adjustable
-60
-60
-80
Fixed Gain Mode
-80
Fixed Gain Mode
-100 20
100
1k
20k
-100 20
100
1k
20k
Frequency (Hz)
Frequency (Hz)
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APA4838
Typical Characteristics (Cont.)
Gain vs. Frequency
+12 +10 +8 +6 +4 +2 -0 20 100 1k 20k
VDD=5V RL=8 Av=2V/V BTL Cf=0.068F Cf=0.22F Cf=0.1F
Gain (dB)
Frequency (Hz)
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APA4838
Application Descriptions
BTL Operation The APA4838 output stage (power amplifier) has two pairs of operational amplifiers internally, allowed for different amplifier configurations for each channel.
Gain 1 Gain 2
BTL Operation (Cont.) A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared
-Out
to a SE amplifier under the same conditions. A BTL configuration, such as the one used in APA4838, also
Volum e Control Am plifier output signal
OP1
creates a second advantage over SE amplifiers.
RL +Out
Since the differential outputs, +Right Out, -Right Out, +Left Out, and -Left Out, are biased at half-supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Single-Ended Operation Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33F to 1000F) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described still hold with the addition of the following relationship: 1 1 << 1 Cbypass x 125k RiCi RLCC (1)
Vbias
OP2
Figure 1: APA4838 power amplifier internal configuration (each channel) The power amplifier OP1 gain is setting by internal unity-gain or external gain setting which is selected from Gain Select pin and the audio input signal come from internal volume control block, while the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of with both amplifiers with identical in magnitude, but out of phase 180. Consequently, the differential gain for each channel is 2X (Gain of SE mode). By driving the load differentially through outputs -Out and +Out, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground.
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APA4838
Application Descriptions (Cont.)
Output SE/BTL Operation The ability of the APA4838 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the APA4838, two separate amplifiers drive -Out and +Out for each channel (see Figure 1). The HP Sense input controls the operation of the follower amplifier that drives +Left Out and +Right Out. * When HP Sense is held low, the OP2 is turn on and the APA4838 is in the BTL mode. *When HP Sense is held high, the OP2 is in a high output impedance state, which configures the APA4838 as SE driver from -Out. IDD is reduced by approximately one-half in SE mode. Control of the HP Sense input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit. Docking Output Signal APA4835 internal first amplifier is used as audio signal pre-amplfier and feedback resistor is connected between Dock output pin and audio input pin. However, the internal first amplifier's closed-loop gain can be adjusted using external resistors. Use Equation 2 to determine the input and feedback resistor values for a desired gain.
1k VDD 100k HP sense
Sleeve Control Pin Ring
Output SE/BTL Operation (Cont.) In Figure 2, input HP Sense operates as follows: When the phonejack plug is inserted, the 1k resistor is disconnected and the HP Sense input is pulled high and enables the SE mode. When this input goes high level, the +Out amplifier is shutdown causing the speaker to mute. The -Out amplifier then drives through the output capacitor (CC) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100k and 1k. Resistor 1k then pulls low the HP Sense pin, enabling the BTL function.
AV = -
RF Ri
(2)
The Dock output signal provides low distortion audio quality for light driving output. ex. active speaker, monitors or audio/visual equipment. These two outputs can driving load of >1k with rail-to-rail output and output coupling capacitor is required when using these outputs.
Tip
Headphone Jack
Figure 2: HP Sense input selection by phonejack plug
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APA4838
Application Descriptions (Cont.)
Docking Output Signal (Cont.) Typical values for the output coupling capacitors are 0.33F to 1.0F. If polarized coupling capacitors are used, connect their '+' terminals to the respective output pin. The Right Dock and Left Dock channel outputs signal are also used to driving internal volume control amplifier. Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the follow equation: FC(highpass)= 1 2RiCi (3) As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitors located on the bypass and power supply pins should be as close to the device as possible. The effect of a larger half supply bypass capacitor will improve PSRR due to increased halfsupply stability. Typical application employ a 5V regulator with 1.0F and a 0.1F bypass as supply filtering. This does not eliminate the need for bypassing the (4) supply nodes of the APA4838. The selection of bypass capacitors, especially Cbypass, is thus dependent upon desired PSRR requirements, click and pop performance. To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (5) should be maintained. 1 1 << Cbypass x 125k RiCi
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003 19
Input Capacitor, Ci (Cont.) This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor, Cbypass
The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 100k and the specification calls for a flat bass response down to 40Hz. Equation is reconfigured as follow: Ci= 1 2RifC
Consider to input resistance variation, the Ci is 0.04F so one would likely choose a value in the range of 0.1F to 1.0F. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load.
(5)
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APA4838
Application Descriptions (Cont.)
Effective Bypass Capacitor, Cbypass (Cont.) The bypass capacitor is fed from a 125k resistor inside the amplifier. Bypass capacitor, Cbypass, values of 3.3F to 10F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. The bypass capacitance also effects to the start up time. It is determined in the following equation: Tstart up = 5 x (Cbypass x 125k) Output Coupling Capacitor, Cc In the typical single-supply (SE) configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation. FC(highpass)= 1 2RLCC (7) (6) Power Supply Decoupling, Cs The APA4838 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F placed as close as possible to the device VDD lead works best. For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. Optimizing Depop Circuitry Circuitry has been included in the APA4838 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage rise up should be slower than input bias voltage.
For example, a 330F capacitor with an 8 speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load.
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
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APA4838
Application Descriptions (Cont.)
Optimizing Depop Circuitry (Cont.) Although the bypass pin current source cannot be modified, the size of Cbypass can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cbypass, turnon pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turnon time for this device. There is a linear relationship between the size of Cbypass and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is of particular concern. This capacitor discharges through the internal 10k resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1k resistor can be placed in parallel with the internal 10k resistor. The tradeoff for using this resistor is an increase in quiescent current. In the most cases, choosing a small value of Ci in the range of 0.33F to 1F, Cbypass being equal to 4. 7F and an external 1k resistor should be placed in parallel with the internal 10k resistor should produce a virtually clickless and popless turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. Shutdown and Mute Function In order to reduce power consumption while not in use, the APA4838 contains a Shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic high is placed on the Shutdown pin.
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003 21
Shutdown and Mute Function (Cont.) The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the supply voltage VDD to provide maximum device performance. By switching the Shutdown pin to high level, the amplifier enters a low-current state, IDD<1A. APA4838 is in shutdown mode. On normal operating, Shutdown pin pull to low level to keeping the IC out of the shutdown mode. The Shutdown pin should be tied to a definite voltage to avoid unwanted state changes. The APA4838 mutes the amplifier and DOCK outputs when VDD is applied to the Mute pin. Even while muted, the APA4838 will amplify a system alert (beep) signal whose magnitude satisfies the PCBEEP detect circuitry. Applying 0V to the Mute pin returns the APA4838 to normal operation. Prevent unanticipated mute behavior by connecting the Mute pin to VDD or ground. Do not let the Mute pin float.
PCBEEP Detect Circuitry
APA4838 integrates a PCBEEP detect circuit for notebook and computer used. When Beep In signal is greater than 1/2VDD, the PCBEEP mode is active. APA4838 will force to BTL mode and the internal fixed gain mode. The Beep In signal becomes the amplifier input signal and plays on the system speaker without coupling capacitor. Use input resistor between stereo input pin and Beep In to attenuate Beep In signal. These resistors are shown as 200k devices in Application Circuit. Use higher value resistors to reduce the gain applied to the beep signal.
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APA4838
Application Descriptions (Cont.)
PCBEEP Detect Circuitry (Cont.)
Internal and External Gain Selection (Cont.)
If the amplifier in the mute mode, it will out of mute mode whenever PCBEEP mode enable. The
Gain 1 RI2 Gain 2 CLF RF2 RLF
APA4838's shutdown mode must be deactivated before a system alert signal is applied to Beep In pin. The APA4838 will return to previous setting when it is out of PCBEEP mode. The Beep In pin should be tied to a ground when not used to avoid unwanted state changes. Mode Function The APA4838's Mode function has 2 states controlled by the voltage applied to the Mode pin. By applying 0V to the Mode pin, forces the APA4838 to fixed gain amplifier and internal volume control block will be disable and internal first amplifier output signal (Dock) to power amplifier directly. When Mode pin goes to high level, which uses the internal DC controlled volume control is selected. This mode sets the amplifier's gain according to the DC voltage applied to the DC Vol control pin. Do not let the Mode pin float when it does not used. Internal and External Gain Selection APA4838 provides external gain setting for base boost function or internal feedback gain setting which is decided by Gain Select control input. If Gain Select pin goes high level, the gain setting will be defined by Gain1 and Gain2 pin. When Gain Select pin tied to low level, APA4835 power amplifier gain setting as unit gain by internal resistor.
-Out
Volum e Control Am plifier output signal
OP1
Figure3: Bass Boost gain setting configuration In some cases a designer may want to improve the low frequency response of the bridged amplifier or incorporate a bass boost feature. Refer to the Figure, a resistor, RLF, and a capacitor, CLF, in parallel, can be placed in series with the feedback resistor of the bridged amplifier as seen in Figure. 1 Fc= 2RLFCLF
(8)
The bridged-amplifier low frequency differential gain is: Fc= 2x(RF2+RLF) R12 (9)
Using the component values shown in Figure (RF2 = 20k,RLF = 20k, and CLF = 0.068F), a first-order, 6dB pole is created at 120Hz. Assuming R12 = 20k, the low frequency differential gain is 4. The input (Ci) and output (CO) capacitor values must be selected for a low frequency response that covers the range of frequencies affected by the desired bass-boost operation.
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
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APA4838
Application Descriptions (Cont.)
Internal and External Gain Selection (Cont.) At low frequencies CLF is a virtual open circuit and at high frequencies, its nearly zero ohm impedance shorts RLF. The result is increased bridge-amplifier gain at low frequencies. The combination of RLF and CLF form a -6dB corner frequency at BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. Efficiency = Volume Adjustable and Fixed Gain selection The APA4838 has an internal stereo volume control whose setting is a function of the DC voltage applied to the DC Vol control pin. The APA4838 volume control consists of 31 steps that are individually selected by a variable DC voltage level on the DC Vol control pin. The range of the steps, controlled by the DC voltage, are from 0dB to -78dB. Each gain step corresponds to a specific input voltage range, as shown in table. To minimize the effect of noise on the volume control pin, which can affect the selected gain level, hysteresis and internal clock delay are implemented. The amount of hysteresis corresponds to half of the step width, as shown in volume control graph. For highest accuracy, the voltage shown in the 'recommended voltage' column of the table is used to select a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The gain levels are 1dB/step from 0dB to -6dB, 2dB/ step from -6dB to -52dB, and the last step at -78dB as mute mode.
1.00 1.3 58.82 68.42 0.34 0.38 4.00 4.47 0.7 0.6 Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) 0.2 0.50 26.67 41.67 0.15 0.24 2.00 2.83 0.55 0.7
PO PSUP
(10)
Where : PO = VORMS x VORMS = VPxVP 2RL RL VORMS = VP 2 (11) (12)
PSUP = VDD x IDDRMS = VDD x 2VP RL Efficiency of a BTL configuration : PO VPxVP ) / (VDD x 2VP ) = VP =( 2VDD PSUP 2RL RL
(13)
**High peak voltages cause the THD to increase. Table 1. Efficiency Vs Output Power in 5-V/8 BTL Systems Table 1 calculates efficiencies for four different output power levels when load is 8.
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
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APA4838
Application Descriptions (Cont.)
BTL Amplifier Efficiency (Cont.) The efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 3W. A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation, V DD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation14 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. SE mode : PD,MAX= VDD 2 22RL (14) Power Dissipation (Cont.) BTL mode : PD,MAX= 4VDD2 22RL (15)
Since the APA4838 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA4838 does not require extra heatsink. The power dissipation from equation15, assuming a 5V-power supply and an 8 load, must not be greater than the power dissipation that results from the equation16: PD,MAX= TJ,MAX - TA JA (15)
For TSSOP-28 package with and without thermal pad, the thermal resistance (JA) is equal to 45C/W and 50C/W, respectively. Since the maximum junction temperature (TJ,MAX) of APA4838 is 150C and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation16. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (V DD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced.
In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode.
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APA4838
Application Descriptions (Cont.)
Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the APA4838 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA4838 4 will go into thermal shutdown when driving a 4 load. The thermal pad on the bottom of the APA4838 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25C, a larger copper plane or forced-air cooling will be required to keep the APA4838 junction temperature below the thermal shutdown temperature (150C). In higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the IC out of thermal shutdown.
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
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APA4838
Packaging Information
TS S O P / TS S O P -P ( R eference JE D E C R egistration M O -153)
e N
2x E/2
E1
E
1
2
3
e/2 D A2 A ( 2) GAUGE PLANE S
b D1
A1
EXPOSED THERMAL PAD ZONE E2 0.25 L (L1) ( 3) 1
BOTTOM VIEW (THERMALLY ENHANCED VARIATIONDS ONLY)
D im A A1 A2 b D
M illim eters
Inches
D1 e E E1 E2
L L1 R R1 S 1 2
M ax. 1.2 0.00 0.15 0.80 1.05 0.19 0.3 6.4 (N =20PIN ) 6.6 (N =20PIN ) 7.7 (N =24PIN ) 7.9 (N =24PIN ) 9.6 (N =28PIN ) 9.8 (N =28PIN ) 4.2 B S C (N =20P IN ) 4.7 B S C (N =24P IN ) 3.8 B S C (N =28P IN ) 0.65 B S C 6.40 B S C 4.30 4.50 3.0 B S C (N =20P IN ) 3.2 B S C (N =24P IN ) 2.8 B S C (N =28P IN ) 0.45 0.75 1.0 R E F 0.09 0.09 0.2 0 8 12 R E F
26
M in.
M ax. 0.047 0.000 0.006 0.031 0.041 0.007 0.012 0.252 (N =20P IN ) 0.260 (N =20P IN ) 0.303 (N =24P IN ) 0.311 (N =24P IN ) 0.378 (N =28P IN ) 0.386 (N =28P IN ) 0.165 B S C (N =20P IN ) 0.188 B S C (N =24P IN ) 0.150 B S C (N =28P IN ) 0.026 B S C 0.252 BS C 0.169 0.177 0.118 B S C (N =20P IN ) 0.127 B S C (N =24P IN ) 0.110 B S C (N =28P IN ) 0.018 0.030 0.039R E F 0.004 0.004 0.008 0 8 12 R E F
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M in.
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
APA4838
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
Reference JEDEC Standard J-STD-020A APRIL 1999
temperature Peak temperature
183C Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/ Convection Average ramp-up rate(183C to Peak) 3C/second max. 120 seconds max Preheat temperature 125 25C) 60 - 150 seconds Temperature maintained above 183C Time within 5C of actual peak temperature 10 -20 seconds Peak temperature range 220 +5/-0C or 235 +5/-0C Ramp-down rate 6 C /second max. 6 minutes max. Time 25C to peak temperature VPR 10 C /second max.
60 seconds 215-219C or 235 +5/-0C 10 C /second max.
Package Reflow Conditions
pkg. thickness 2.5mm and all bgas Convection 220 +5/-0 C VPR 215-219 C IR/Convection 220 +5/-0 C pkg. thickness < 2.5mm and pkg. volume 350 mm pkg. thickness < 2.5mm and pkg. volume < 350mm Convection 235 +5/-0 C VPR 235 +5/-0 C IR/Convection 235 +5/-0 C
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Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003
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APA4838
Reliability test program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C , 5 SEC 1000 Hrs Bias @ 125 C 168 Hrs, 100 % RH , 121C -65C ~ 150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
Po E P P1 D
t
F W
Bo
Ao
Ko D1
T2
J C A B
T1
Application
A 330 1
B 100 ref D 1.5 +0.1
C 13 0.5 D1 1.5 min
J 2 0.5 Po 4.0 0.1
T1 16.4 0.2 P1 2.0 0.1
T2 2 0.2 Ao
W 16 0.3 Bo
P 12 0.1 Ko
E 1.750.1 t
TSSOP- 28
F 7.5 0.1
6.9 0.1 10.2 0.1 1.8 0.1 0.30.05
(mm)
Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2003 28 www.anpec.com.tw
APA4838
Cover Tape Dimensions
Application TSSOP- 28 Carrier Width 16 Cover Tape Width 21.3 Devices Per Reel 2000
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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