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PRELIMINARY DATA SHEET
MICRONAS
MAS 3506D WorldSpace Broadcast Channel Audio Decoder
Edition July 25, 2001 6251-433-1PD
MICRONAS
MAS 3506D
Contents Page 4 4 4 7 7 7 7 8 8 8 8 8 9 9 9 9 9 9 10 10 11 12 13 13 13 13 13 14 15 16 16 16 16 18 18 19 19 19 19 20 23 28 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.2.1. 2.2.1.1. 2.2.1.2. 2.2.2. 2.2.3. 2.2.4. 2.3. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.3.5. 3.3.6. 3.3.7. 3.3.8. 3.3.9. 3.3.10. 3.4. 3.5. 3.5.1. Title Introduction Features of the MAS 3506D System Overview Functional Description of the MAS 3506D Overview Firmware (Internal Program ROM) Broadcast Channel Synchronization Broadcast Channel Timing Buffer-Controlled Loop Broadcast Channel Demultiplexing MPEG Audio Decoding Baseband Processing Clock Management Power Supply Concept Internal Voltage Monitor DC/DC Converter Stand-by Functions Start-up Sequence Interfaces Broadcast Channel (BC) Input Interface Parallel Input Output Interface (PIO) Audio Output Interface Controlling I2C-Access Device Address I2C Registers and Subaddresses Conventions for the Command Description I2C Control Register (Subaddress 6Ahex) I2C-Data Register (Subaddresses 68hex and 69hex) and the MAS 3506D DSP-Command Syntax Data Formats Run and Freeze (Codes 0hex to 1hex) Select Service Component (Code 5hex) Read Ancillary MPEG Data (Code 6hex) Read SCH-Data (Code 8hex) Write Register (Code 9hex) Write Memory (Codes Ahex and Bhex) Read Register (Code Dhex) Read Memory (Codes Ehex and Fhex) Default Read Control Registers Control and Status Memory Volume Matrix
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
MAS 3506D
Contents, continued Page 30 30 31 33 33 33 33 33 33 34 34 35 35 35 36 37 37 37 39 40 41 42 43 43 44 46 52 Section 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.3.7. 4.3.8. 4.3.9. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.4. 4.6.5. 5. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins DC/DC Converter Pins Control Lines Parallel Interface Control Lines Parallel Interface Data Lines Voltage Supervision And Other Functions Serial Input Interface Serial Output Interface Miscellaneous Pin Configuration Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics I2C Characteristics Timing of PIO-Signals I2S Bus Characteristics - SDI I2S Characteristics - SDO Firmware Characteristics DC/DC Converter Characteristics Typical Performance Characteristics Data Sheet History
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WorldSpace Broadcast Channel Audio Decoder
PRELIMINARY DATA SHEET
- Low power dissipation (30 mW at fs 12 kHz, 46 mW at fs 24 kHz, 86 mW at fs > 24 kHz at 2.7 V) - Supply voltage range: 2.7 V to 3.6 V - Adjustable built-in DC/DC up-converter for one-cell and two-cell battery operation (typically down to Vbat = 0.9 V) - Adjustable power supply supervision - Power-off function
1. Introduction The WorldSpace system is a satellite-based digital radio service for direct-to-home transmission of digital radio programs. The coverage areas of this service are Africa, South America, and parts of Asia. The MAS 3506D is the source decoder of Micronas' StarMan chip set that is designed for the reception of WorldSpace signals. The MAS 3506D extracts one Service Component (SC) of an incoming digital WorldSpace Broadcast Channel (BC) and decodes MPEG 1/2/2.5 Layer 31) encoded audio data contained in the selected Service Component. The Service Control Header (SCH) information from the Broadcast Channel is accessible via the embedded fast mode serial control interface. The MAS 3506D provides digital audio data output in I2S and similar formats. An embedded digital buffer-controlled loop recovers the sampling frequency of the audio signal and generates a synchronized 24.576 MHz clock signal which is used as an oversampling clock for D/A converters. A block diagram of the MAS 3506D is shown in Figure 1-2 on page 5.
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1.2. System Overview The Micronas StarMan chip set consists of the channel decoder DRD 3515A and the MPEG Layer 3 audio decoder MAS 3506D. All essential analog and digital building blocks for WorldSpace reception are provided by the chip set. Together with an L-band tuner and an appropriate microcontroller this set creates a complete StarMan radio receiver (Figure 1-1)
MPEG 2.5 is a compatible extension of MPEG 2 audio, defined in ISO/IEC 13818-3.2 that covers additionally very low sampling frequencies down to 8 kHz.
Aux1/2 AM/FM (analog) Receiver, Tape Player
MAS 3506D
BC
I2S SC-out
1.1. Features of the MAS 3506D - Single-chip WorldSpace Broadcast Channel bitstream demultiplexer - ISO MPEG 1/2/2.5 Layer 3 decoder - ISO MPEG compliance tests passed - Data processing by a high-performance RISC DSP core (MASC) - Download feature provides additional functionality - Self-synchronized operation - Output audio data delivered (in various formats) via an I2S bus (SDO) - Digital volume control and stereo channel mixer - Automatic soft-mute function - WorldSpace SCH-data output via I2C interface - MPEG ancillary data provided via I2C interface - Status information accessible via PIO pins or I2C - "CRC Error", "MPEG Frame Synchronization" and "BC-Frame-Synchronization" indicators - Power management for reduced power consumption at lower sampling frequencies
WorldSpace Tuner IF input
DRD 3515A
analog out
I2C
System Controller
Fig. 1-1: Standard application of the StarMan chip set
Since the DRD 3515A also contains an audio amplifier for headphone or small loudspeaker operation, only a minimum of external components is necessary. The additional inputs for analog signals (e.g. conventional AM/FM receiver, tape etc.) make the amplifier accessible to these audio sources and thus considerably simplify the design of complete radio receivers. The analog audio output of the WorldSpace signal can be connected to an external stereo amplifier for higher power or quality. Also a digital audio signal in standard I2S format is provided for high-end applications that may require an external D/A converter.
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MAS 3506D
Service Control Header data are available via I2C controller interface from the MAS 3506D. (N.B. The Time Slot Control Channel data are available only from the DRD 3515A.)
The complete WorldSpace Broadcast Channel (BC) is available as a serial output signal from the DRD 3515A and provides full access to all WorldSpace data. The additional Service Component (SC) output of the DRD 3515A may be useful in applications where a data and an audio channel are transmitted simultaneously. In this case, the data component is directed to the SC output. This function is independent from the audio Service Component extraction in the MAS 3506D.
14.725 MHz 24.576 MHz
RCLK OCLK Clock Synthesizer I2C Interface to C
to DRD 3515A
BC in
Serial Input Interface
Service Component Extraction from Broadcast Channel MPEG 1/2/2.5 Layer 3 Audio Decoding
Parallel Interface
Audio Data out
Serial Output Interface
Buffer-Controlled Loop 20-Bit RISC DSP
DC/DC Converter
VDD
Fig. 1-2: Block diagram of the MAS 3506D
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Fig. 1-3: Complete WorldSpace receiver block diagram
MAS 3506D
BCDout To optional BC processing BCC SCDout To optional SC processing SCC SCW BCDin BC data input from ext. processing BCenable Satellite Antenna
14.725 MHz
1 CLKI PUP
Pol.Switch
RClk
2 QPSK Dem. and Timing Recovery
FEC and TDM Demux 4 OClk D/A and Analog Audio
3
Input Buffer
SC Extr. DC/DC Converter DCEN
Double Superhet L-Band Tuner FM/AM Antenna
2nd IF
24.576 MHz
BufferMPEG controlled Layer 3 Clock Decoder Synthesizer
DRD3515A
C B
Digital Audio
Output Buffer
3.0 V
MAS3506D
WSEN Mono
SCI-Control Bus Stereo
Left Right
FM/AM Demod.
regulated Voltage (3 V)
Line
Audio Out
PRELIMINARY DATA SHEET
LCD C Keys
A
WRDY PUP
PRELIMINARY DATA SHEET
MAS 3506D
2.2. Firmware (Internal Program ROM) The firmware of the MAS 3506D operates on the Broadcast Channel signal generated by the DRD 3515A. The MAS 3506D firmware processes the input signal in four steps. - Broadcast Channel synchronization - Broadcast Channel demultiplexing - MPEG audio decoding - Frame synchronization and decoding error signals are provided at output pins of the MAS 3506D.
2. Functional Description of the MAS 3506D 2.1. Overview The hardware of the MAS 3506D consists of a highperformance RISC Digital Signal Processor (DSP) and appropriate interfaces for WorldSpace Broadcast Channel decoding (see Figure 2-1). The internal processor works with a memory word length of 20 bits and an extended range of 32 bits in its accumulators. The instruction set of the DSP is highly optimized for audio data compression and decompression. Thus, only very small areas of internal RAM and ROM are required. All the data input and output actions are based on a 'noncycle-stealing' background DMA that does not cause any computational overhead (except for some initialization). The overall function of the MAS 3506D can be altered by downloading up to 1 kWord of program code into the internal RAM and executing this code instead of the built-in firmware ROM code1). Dedicated clock management hardware supports synchronization on the transmitted data signal. A DC/DC step-up converter has been integrated for efficient battery-based operation. Fig. 2-1 shows the building blocks of the MAS 3506D.
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2.2.1. Broadcast Channel Synchronization The MAS 3506D analyzes the incoming BC bitstream and detects the Service Control Header (SCH) preamble. If the preamble is found, the BC-SYNC signal (available at a MAS 3506D output pin) indicates that the MAS 3506D is in synchronized state. If synchronization is lost, the MAS 3506D automatically resets the BC-SYNC signal and performs an audio soft-mute until the next SC-header is detected.
Detailed information about downloading is provided in combination with the MAS 3506D software development package or together with the MAS 3506D software modules available from Micronas.
OCLK
Clock Synthesizer
SCH buffer
to DRD 3515A
BC input
SCH Synchronization
Service Component Selection
Configuration Registers
Digital Audio output
Volume Matrix
MPEG 1/2/2.5 Layer 3 Decoder
Layer 3 Status Data Buffer Ancillary Data
to C (I2C)
Fig. 2-1: Functional overview of the MAS 3506D
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2.2.1.1. Broadcast Channel Timing The incoming Broadcast Channel bitstream has a framing with a period between Prime Rate Channel Preambles (PRCP) of prcpt = 432 ms During one frame the transmission of the BC is interrupted by a gap prcpgap of: prcpgap = 2.5 ms The data transmission is interrupted by a second gap mfpgap with a duration of mfpgap = 1.2 ms that is synchronous with the Master Frame Preamble (MFP) cycle with a period of: mfpt = 138 ms Both cycles mfpt and prcpt have a least common multiple at 9936 ms. These gaps are independent of the number of Prime Rate Channels (PRC) n that create the considered Broadcast Channel.
PRELIMINARY DATA SHEET
2.2.2. Broadcast Channel Demultiplexing The Service Control Header that directly follows the SCH-preamble in the BC bitstream is made accessible to the controller after it has been detected. Its availability is indicated by the BC-FRAME-SYNC signal. Information about the content of the Broadcast Channel is given in the Service Control Header data. The controller may select the number of the Service Component that is to be passed to the internal MPEG audio decoder. By default, always Service Component "0" is decoded by the MAS 3506D. An implemented autoscan mode can be selected that skips non-audio Service Components.
2.2.3. MPEG Audio Decoding The MPEG 1/2/2.5 Layer 3 decoder performs the audio decoding. The steps for decoding are: - Synchronization - Side information extraction - Huffman decoding - Synthesis filter bank - Ancillary data extraction The bit rates and sampling rates that are supported by the MAS 3506D are listed in Table 2-1. Table 2-1: Sampling frequencies and bit rates Sampling Freq. in kHz 48, 32, 24, 16, 12, 8 Bit rates in kBit/s 128, 112, 96, 80, 64, 56, 48, 40, 32, 24, 16, 8
2.2.1.2. Buffer-Controlled Loop For the recovery of the audio sample clock, a buffercontrolled loop is used that operates on the incoming Broadcast Channel bit stream. The buffer control loop characteristic suppresses the effects of these gaps on the stability of the generated audio sample frequency by more than 40 dB. Thus, no audible jitter is introduced to the derived reference clock for the D/A converter (see section 2.3. "Clock Management"). The step response of the buffer-controlled loop is plotted in Figure 2-2 with respect to different number of PRCs. The settling time for the buffer-controlled loop is about 10 s.
0.12 0.1 0.08 0.06 0.04 0.02 4.3 8.6 13 17 21
Frame synchronization and decoding error signals are provided at output pins of the MAS 3506D.
2.2.4. Baseband Processing A digital volume control matrix is applied to the digital stereo audio data. This matrix may also perform additional balance control and a simple kind of stereo basewidth enhancement. The four factors LL, LR, RL, and, RR are adjustable via the controller with 20 bit resolution (see Fig. 3-2 on page 28).
t/s
Fig. 2-2: buffer-controlled loop step response
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MAS 3506D
current variation and the ESR determines the high-frequency amplitude seen on the output voltage. The Schottky diode should have a low voltage drop VD for a high overall efficiency of the DC/DC converter. The current rating of the diode should also be greater than 2.5 times the DC output current. The VSENS pin has to be always connected to the output voltage.
2.3. Clock Management The complete StarMan chip set is driven by a single crystal with a nominal frequency of 14.725 MHz. The DRD 3515A contains the crystal oscillator and an appropriate clock buffer to generate the clock signal RClk. This RClk signal is used as reference clock for the MAS 3506D by an internal clock synthesizer that generates an internal system clock of 24.576 MHz. This synchronized clock frequency is passed back to the DRD 3515A for use in its embedded audio D/A converter.
2.4.3. Stand-by Functions A high level at pin WSEN enables both, the DSP including the I2C-block and the DC/DC-converter. If the DSP-functions (audio decoding) are not needed, the DC/DC-converter may remain active to supply other parts of the radio. This mode is entered by setting DCEN to "high" and WSEN to "low". No I2C control is possible in this mode.
2.4. Power Supply Concept The MAS 3506D offers an embedded controlled DC/ DC converter for battery based power supply concepts. It works as an up-converter.
2.4.4. Start-up Sequence The DC/DC converter starts from a minimum input voltage of 0.9 V. There should be no output load during startup. WSEN must be "low". The start-up script should be as follows: 1. Start the DC/DC-converter with a high signal (VDD, AVDD) at pin DCEN. 2. Wait until PUP goes "high". 3. It is recommended to wait at least one millisecond to guarantee that the output voltage has settled. 4. The controller may now enable the DSP with a "high" signal at pin "WSEN". Please also refer to Figure 2-3.
2.4.1. Internal Voltage Monitor An internal voltage monitor compares the input voltage at the VSENS pin with an internal reference value that is adjustable via I2C bus. The PUP output pin should be observed by the controller. It becomes inactive when the voltage at the VSENS pin drops below the programmed value of the reference voltage. It is important that the WSEN must not be activated before the PUP signal is generated. The PUP signal thresholds are listed in Table 3-10 on page 20. The internal voltage monitor will be activated with a high level at Pin DCEN.
2.4.2. DC/DC Converter The DC/DC converter of the MAS 3506D is used to generate a fixed power supply voltage even if the chip set is powered by battery cells in portable applications. The DC/DC converter is designed for the application of 1 or 2 batteries or NiCd cells as shown in Fig. 2-5 which shows the standard application circuit. The DC/ DC converter is switched on by activating the DCEN pin. Its output power is sufficient for supplying the complete radio receiver. Note: Connecting DCEN directly to VDD leads to unexpected states of the DCCF register. A 22 H inductor is required for the application. The important specification item is the inductor saturation current rating, which should be greater than 2.5 times the DC load current. The DC resistance of the inductor is important for efficiency. The primary criterion for selecting the output filter capacitor is low equivalent series resistance (ESR), as the product of the inductor
Controller DSP operation WSEN > 2 V
1
> 0.9 V DCEN button Fig. 2-3: DC/DC operation
DC/DC On
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2.5. Interfaces The MAS 3506D uses an I2C control interface, a serial input interface for the Broadcast Channel, and a digital audio output interface for the decoded audio data (I2S or similar). Additionally, a general-purpose parallel I/O interface (PIO) may be used for monitoring and modeselection tasks. The PIO lines are controlled by the internal firmware.
PRELIMINARY DATA SHEET
tSICLK
Vh VlI
BCC(SIC)
Vh
76543210 tbw
2.5.1. Broadcast Channel (BC) Input Interface The BC input interface consists of the three pins SIC, SII, and SID. For WorldSpace operation the SII pin is always to be connected to VSS. The Broadcast Channel input signal format is shown in Figure 2-4. The data values are latched with the falling edge of the SIC signal. The input interface is asynchronous and accepts data streams generated by the DRD 3515A BC output.
VI
BCD(SID)
Fig. 2-4: Schematic timing of the SDI (BC) input
The BC input can be switched to an alternate port. This function is controlled by input pin PI18. For more details please see Section 3.1.3. on page 13
L
CLKI
VDD Start-up oscillator Start-up oscillator
64...94
x2
AVDD DCSO DCSG DC/DC converter
optional filter
22 H
+ -
COUT 330 F Low ESR
+
32...47
+32
DCEN voltage monitor PUP WSEN
16
Power-On Push Button
VIN 0.9 V
CIN 330 F
-
DCCF 8ehex 9 10
0...15
10 k
VSENSE VSS AVSS
47 k 10 nF 47 k
Controller
Fig. 2-5: DC/DC converter connections
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MAS 3506D
2.5.2. Parallel Input Output Interface (PIO) The parallel interface of the MAS 3506D consists of the lines PI0..PI4, PI8, PI12..PI19: Table 2-2: PIO input and output pin assignment during MPEG decoding PIO Pin PI19 (O) PI18 (I) PI13 (O) P12 (O) PI8 (O) Name BC-FRAME-TOGGLE 0 1 BCINENABLE 0 1 BC-FRAME-SYNC 0 1 BC-SYNC 0 1 MPEG-CRC-ERROR 0 1 MPEG-FRAME-SYNC 0 1 AUD-SW sync to a new MPEG frame May be used to monitor a signal indicating switching between Headphone and Loudspeaker mode. The PI-pins may be monitored by reading the PIO register (see Table 3-10) no error CRC-error or sync lost unsynched synched to BC start of new frame enables SI* inputs enables SI inputs Comment Output level toggled each BCFRAME
PI4 (O)
PI3 (I)
PI2, PI1, PI0 (I)
Reserved
These signals are used to indicate the status of the Broadcast Channel and the MPEG Layer 3 decoder. The PIO pin status is also accessible via I2C interface (see Table 3-10).
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2.5.3. Audio Output Interface The audio output interface of the MAS 3506D is a standard serial audio interface. The interface is configurable by software to work in 16-bit/sample and 32-bit/ sample mode. The default setup is a 16-bit mode which is also the default setting for the DRD 3515A. The 32-bit/sample mode is provided for high-resolution D/A converters that expect more than 16-bit/sample input data. The embedded D/A-converter of the
PRELIMINARY DATA SHEET
DRD 3515A is also capable of decoding the 32-bit/ sample format and provides a slightly better S/N performance in this mode1). The audio output interface timing is shown in Figure 2-6 and Figure 2-7.
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If the 32-bit mode is selected and the D/A converter of the DRD 3515A is still connected, it also has to be switched to 32-bit I2S mode.
DAD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAI
left 16-bit audio sample
right 16-bit audio sample
timing detail DAI DAD
Vh Vl Vh Vl
0
15
Fig. 2-6: Schematic timing of the digital audio output interface in 16-bit/sample mode
31
0 31
0
left 32-bit audio sample
right 32-bit audio sample
DAI DAD
Vh Vl Vh Vl
timing detail
1
0
31
Fig. 2-7: Schematic timing of the digital audio output interface in 32-bit/sample mode
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3.1.3. Conventions for the Command Description The description of the various controller commands uses the following formalism: - Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don't care - Memory addresses like D1:89f are always in hexadecimal notation. - A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. - Data values in nibbles are always shown in hexadecimal notation. - A hexadecimal 20-bit number d is written, e.g. as d = 17c63hex, its five nibbles are d0 = 3hex, d1 = 6hex, d2 = chex, d3 = 7hex, and d4 = 1hex. - Variables used in the following descriptions: DW 3ahex I2C-device write I2C-device read DR 3bhex data register write data_write 68hex data register read data_read 69hex control register write control 6ahex - Bus signals S Start P Stop A ACK = Acknowledge N NAK = Not acknowledge W Wait = a wait time ( 4 ms) may occur - Symbols in the telegram examples < Start condition > Stop dd data byte xx ignore All telegram digits are hexadecimal, data originating from the MAS 3506D are grayed. Example: <3a 68 dd dd> write data to DSP <3a 69 <3b dd dd > read data from DSP Figure 3-1 shows I2C bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the I2C-device address with the read command (DR). Fields with signals/data originating from the MAS 3506D are marked by a gray background. Note that in some cases the data reading process must be concluded by a NAK condition. The MAS 3506D firmware scans the I2C interface periodically and checks for pending or new commands.
3. Controlling 3.1. I2C-Access Communication between the MAS 3506D and the external controller is done via an I2C slave interface.
3.1.1. Device Address The device addresses are 3ahex for writing (DW) and 3bhex for reading (DR), respectively. I2C clock synchronization is used to slow down the bus if required. Table 3-1: I2C device address bits A6 0 A5 0 A4 1 A3 1 A2 1 A1 0 A0 1 write/ read 0/1
3.1.2. I2C Registers and Subaddresses The interface uses one level of subaddresses. The MAS 3506D interface has 3 subaddresses allocated for the corresponding I2C-registers. Table 3-2: I2C subaddresses SubI2Caddress Register 68hex 69hex 6ahex data_write data_read control Function Controller writes to MAS 3506D data register Controller reads from MAS 3506D data register Controller writes to MAS 3506D control register
The address 6ahex is used for basic control, i.e. reset and task select. The other addresses are used for data transfer from/to the MAS 3506D. The I2C-control and data registers of the MAS 3506D are 16 bits wide, the MSB is denoted as bit [15]. Transmissions via I2C-bus have to take place in 16-bit words (two byte transfers, MSB sent first); thus for each register access two 8-bit data words must be sent/ received via I2C-bus.
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The commands are then executed by the DSP during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. However, due to some time critical firmware parts, a certain latency time for the response has to be expected at the locations marked with a "W" (= wait). The theoretical worst case response time does not exceed 4 ms. However, the typical response time is less than 0.5 ms.
PRELIMINARY DATA SHEET
3.2. I2C Control Register (Subaddress 6Ahex)
S
DW
W
A
control
A
d3,d2
A
d1,d0
W
A
P
The I2C control register is a write-only register. Its main purpose is the software reset of the MAS 3506D. The software reset is done by writing a 16-bit word to the MAS 3506D with bit 8 set. The 4 least significant bits are reserved for task selection. The task selection is only useful in combination with download software. In the standard application these bits must always be set to 0. Table 3-3: Control register data bit assignment1)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x x x x x x x R 0 0 0 0 T3 T2 T1 T0
1) x = don't care, R = reset, T3...T0 = task selection
Example: I2C write access S DW (3ahex) W A data_write (68hex) A high byte data A low byte data W
A
P
Example: I2C read access S DW (3ahex) W A data_read (69hex) A S DR (3bhex) A W A W N P
high byte data
low byte data
SDA SCL S
1 0
P
W = Wait A = Acknowledge (Ack) N = Not Acknowledge (NAK) S = Start P = Stop
Fig. 3-1: I2C-bus protocol for the MAS 3506D. Signals originating from the MAS 3506D are grayed.
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DSP-commands consist of a "Code" which is sent to to I2C-data register together with additional parameters.
3.3. I2C-Data Register (Subaddresses 68hex and 69hex) and the MAS 3506D DSP-Command Syntax The I2C data register is used to communicate with the internal firmware of the MAS 3506D. It is readable (subaddress "data_read") and writable (subaddress "data_write") and also has a length of 16 bits. The data transfer is done with the most significant bit (m) first.
S
DW
W
A data_write A Code,... A
...,...
A
...
Table 3-5 gives an overview over the different commands which the DSP-core may receive. The "Code" is always the first data nibble transmitted after the "data_write" byte. The control interface is also used for low-bit-rate data transmission, i.e. MPEG-embedded ancillary data and the WorldSpace Service Control Header. These data are available in a specified memory area of the MAS 3506D after successful decoding. The synchronization between controller and the MAS 3506D will be done by observing the BC-FRAME-SYNC and MPEGFRAME-SYNC signals in register c8hex or at the corresponding pins.
Table 3-4: Data register bit assignment
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 m l
A special command language is used that allows the controller to access the DSP-registers and RAM-cells and thus monitor internal states, set the parameters for the DSP-firmware, control the hardware, and even provide a download of alternative software modules. The
Table 3-5: Basic controller command codes for the MAS 3506D Code (hex) 0 1 5 6 8 9 a, b d e, f Command Run Run Config Select SC Read Ancillary Data Read SCH-Data Write Register Write Memory Read Register Read Memory Function Start execution of an internal program. Run with start address 0hex means freeze the operating system Start execution of an internal program and switch config RAM to P-RAM Select the Service Component Read MPEG ancillary data Read Service Control Header An internal register of the MAS 3506D can directly be written to by the controller A block of the DSP memory can be written to by the controller. (This feature may be used to download alternate programs.) The controller can read an internal register of the MAS 3506D A block of the DSP memory can be read by the controller
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3.3.1. Data Formats The internal data word size is 20 bits. All RAMaddresses can be accessed in a 20-bit mode via I2Cbus. Because of the 16-bit width of the I2C-data register the full transfer of all 20 bits requires two 16-bit I2Cwords. Some commands only access the lower 16 bits of a cell. For fast access of internal DSP-states the processor core also has an address space of 256 data registers. The internal data format is a 20 bit two's complement denoted "r". If in some cases a fixed point notation "v" is necessary. The conversion between the two forms of notation is done as follows: r = v*524288.0+0.5; (-1.0 v < 1.0) v = r/524288.0; (-524288 < r < 524287)
PRELIMINARY DATA SHEET
3.3.3. Select Service Component (Code 5hex)
S DW W A data_write A 5,0 0,0 A A 0,0 0,d0 W W A A P
Select the (zero-based) service component with the number d = d0. The number of available service components is to be taken from the SCH information. A maximum of 8 service components are allowed in one Broadcast Channel. SC-selection is also possible by writing to memory cell D1:7ef (see Table 3-11 on page 23).
3.3.4. Read Ancillary MPEG Data (Code 6hex)
1) send command (Read D0)
S DW W A data_write A 6,o2 A o1,o0 W A P
3.3.2. Run and Freeze (Codes 0hex to 1hex)
S DW W A data_write A a3,a2 A a1,a0 W A P
2) get ancillary data values
S DW W A data_read A S d3,d2 DR A W A W A
d1,d0
....repeat for n data values....
The Run command causes the start of a program part at address a = (a3,a2,a1,a0). Note that nibble a3 is also the command code (see Table 3-5) and thus it is restricted to certain values. This command is especially used to start alternate code or downloaded code from a RAM-area that has been configured as program RAM. Example 1: Start program execution at address 345hex: <3a 68 03 45> Freeze is a special run command with start address 0. It suspends all normal program execution. The operating system will enter an idle loop so that all registers and memory cells can be watched. This state is useful for operations like downloading code or contents of memory cells because the internal program cannot overwrite these values. This freezing will be required if alternative software is downloaded into the internal RAM of the MAS 3506D. Freeze has the following I2C protocol: <3a 68 00 00> The entry point of the default software will be accessed automatically after a reset, thus issuing a Run or Freeze command is only necessary for starting downloaded software or special program modules which are not part of the standard set.
d3,d2
A
d1,d0
W
N
P
The availability of new ancillary data is indicated by the MPEG-FRAME-SYNC signal in register c8hex or at the corresponding pin. Ancillary data are available every 24 to 32 ms depending on the sample rate of the MPEG-bitstream. The instruction parameters are embedded in the 3 nibbles o2..o0. The 6 MSBs indicate the address offset counted in 16-bit words where the read-out of the ancillary data shall start. The 6 LSBs indicate the number of 16-bit words that are to be transmitted by MAS 3506D. Table 3-6: Arrangement of o-bits
11 10 9 8 7 6 5 4 3 2 1 0
o2 address offset
o1
o0 number of 16-bit words
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PRELIMINARY DATA SHEET
MAS 3506D
Telegram example: First get the content of 'Number of ancillary bits':
The data values that are returned are organized in the following table: Table 3-7: Content of ancillary data field Offset 0 1 2 3 ... Content Bit 17..32 of MPEG header1) Bit 12..16 of MPEG header
2)
<3a 68 60 81> <3a 69 <3b dd dd >
device write ( I2C-address) data write code 6hex, offset 2, count 1: Get number of ancillary bits initiate reading and read number of bits
Number of ancillary data bits Last 16 bits of ancillary data
Calculate number of words to be read from the number of bits received (e.g. 20 bits require two words). <3a 68 60 c2> <3a 69 <3b dd dd dd dd > device write (I2C-address) data write code 6hex, offset 3, count 2: Read two words from offset 3. initiate reading and read two words
28
First 16 bits of ancillary data
1) see address D1:7f6 in Table 3-11 on page 23 2) see address D1:7f5 in Table 3-11 on page 23
The ancillary data values are copied in the reverse order into this data field where the last bit received is place at bit 0 of the data word at offset 3. The number of data words with content can be calculated as follows: int [(NumberOfAncillaryBits-1)/16] + 1 Limitations: - The maximum number of data words that can be read out are 28. - The upper limit for ancillary data bitrate is 9600 bps. - The ancillary data are only valid for 6 ms after the MPEG-FRAME-SYNC signal. Memory example: The MPEG bitstream contains 20 bits of ancillary data with the content f0f08hex. Then the ancillary data field content will be: Table 3-8: Ancillary data example Offset 0 1 2 3 4 Content Bit 17..32 of MPEG header Bit 12..16 of MPEG header 14hex (number of anc bits) 0f08hex (bit-order reversed) xxxfhex
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MAS 3506D
3.3.5. Read SCH-Data (Code 8hex)
1) send command (Read D0)
S DW W A data_write A 8,o2 A o1,o0 W A P
PRELIMINARY DATA SHEET
Common Parameters with Command-Code 8hex Often the four nibbles defining start address and amount to be transmitted (8hex, o2, o1, o0) may have the following values: - 80 04: Read 16 bytes (= 8 words, 6 LSBs = 4) from the beginning (offset = 0, 6 MSBs = 0) of the SCH (i.e. everything from the beginning up to ADF2)
P
2) get SCH-values
S DW W A data_read A S d3,d2 DR A W A W A
d1,d0
....repeat for n data values....
d3,d2 A d1,d0 W N
- 81 01: Read 4 bytes (= 2 words, 6 LSBs = 1) starting at 16 bytes (= 8 words, 6 MSBs = 4) offset (i.e. one Service Component Control Field SCCF) - 81 05: Read 20 bytes (= 10 words, 6 LSBs = 5) starting at 16 bytes (= 8 words, 6 MSBs = 4) offset (i.e. 5 Service Component Control Fields SCCF)
The availability of Service Control Header data is indicated by the related status registers or the BCFRAME-SYNC. The instruction parameters are embedded in the 3 nibbles o2..o0. The 6 MSBs indicate half of the address offset counted in 16-bit words where the read out of the SCH data shall start. The 6 LSBs indicate half of the number of 16-bit words that are to be transmitted by the MAS 3506D. Example: If 4 words starting with SCH-word 10 shall be read out the command parameters o2..o0 have to be set to: Table 3-9: SCH-command example
11 10 9 8 7 6 5 4 3 2 1 0
3.3.6. Write Register (Code 9hex)
S DW W A data_write A 9,r1 d3,d2 A A r0,d4 d1,d0 W W A A P
The controller writes the 20-bit value (d = d4,d3,d2,d1,d0) into the MAS 3506D register (r = r1,r0). A list of registers needed for control purposes is given in Table 3-10 on page 20. Example: Writing the value 81234hex into the register with the number aahex: <3a 68 9a a8 12 34>
o2 0 5 0 0 1
o1 0 1 0 2 0
o0 0 0 1 0
5 means offset of (10 16-bit-words)/2
2 means amount of (4 16-bit-words)/2
Thus the command sequence that is to be sent to the MAS 3506D is: <3a 68 81 42> device write (MAS 3506D I2C-address) data write code 8hex, 4 words from offset word 10
The data read sequence is then initialized by <3a 69 <3b DW (MAS 3506D write address) data read DR (MAS 3506D read address)
Then the MAS 3506D will send the SCH-values dd dd dd dd dd dd dd dd > SCH10.h, SCH10.l SCH11.h, SCH11.l SCH12.h, SCH12.l SCH13.h, SCH13.l
where SCHx.h/l refers to the high/low part of the xth word of the SCH.
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PRELIMINARY DATA SHEET
MAS 3506D
3.3.9. Read Memory (Codes Ehex and Fhex) The MAS 3506D has 2 memory areas called D0 and D1 using the codes ehex and fhex for their read commands, respectively.
3.3.7. Write Memory (Codes Ahex and Bhex) The memory areas D0 and D1 can be written by using the codes ahex and bhex, respectively.
S
DW
W
A data_write A
a,0 n3,n2 a3,a2
A A A A
0,0 n1,n0 a1,a0 d1,d0
W W W W
A A A A
1) send command (Read D0)
S DW W A data_write A e,0 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P
x,x
A
x,d4
W
A
d3,d2
....repeat for n data values....
x,x A x,d4 W A d3,d2 A d1,d0 W A P
2) get register value
S DW x,x W A A data_read A x,d4 W A S d3,d2 DR A W A W A
With the Write D0/D1 Memory command n 20-bit memory cells in D0 can be initialized with new data. Example: Write 80234hex to D1:456 has the following I2C protocol: <3a 68 b0 00 00 01 04 56 00 08 02 34> write D1 memory 1 word to write start address value = 80234hex
d1,d0
....repeat for n data values....
x,x A x,d4 W A d3,d2 A d1,d0 W N P
The Read D0/D1 Memory command gives the controller access to all 20 bits of the memory cells of the MAS 3506D. The telegram for reading 3 words starting at location D1:100 is <3a 68 f0 00 00 03 01 00> <3a 69 <3b xx xd dd dd xx xd dd dd xx xd dd dd >
3.3.8. Read Register (Code Dhex)
1) send command
S DW W A data_write A d,r1 A r0,0 W A P
3.3.10.Default Read
S DW W A data_read A S DR d3,d2 W A A d1,d0 W N P
2) get register value
S DW x,x W A A data_read A x,d4 W A S d3,d2 DR A W A W N P
d1,d0
The MAS 3506D has an address space of 256 DSPregisters. Some of the registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the internal program flow. In Table 3-10, the registers of interest are described in detail. In contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. Example: Read the content of the register c8hex: <3a 68 dc 80> <3a 69 <3b xx xd dd dd > define register and read
The Default Read command immediately returns the lower 16 bits of the main status cell ("Status") of the MAS 3506D and may be used to poll the processor status. The meaning of the returned bits is given in the description of control memory cell D1:7ee in Table 3- 11 on page 23.
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MAS 3506D
3.4. Control Registers The registers displayed in the following table can be read and written via I2C commands described (see Section 3.3.6. and Section 3.3.8.).
PRELIMINARY DATA SHEET
Note! Registers not given in the tables must not be written.
Table 3-10: Control Registers Address (hex) 8e R/W W Function DC/DC-Converter Frequency and Voltage The I2C protocol is working only if the processor is active (WSEN = 1). However, the setting for the DCCF register will remain active if the WSEN line is deasserted. DC/DC-Converter Frequency The frequency is controlled with bits 13...10 and 8. Setting bit [13:10] 11 11 11 11 10 10 10 10 01 01 01 01 00 00 00 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 Frequency/kHz bit [8] = 0 156 160 163 167 171 175 179 184 188 194 199 204 210 216 223 230 Frequency/kHz bit [8] = 1 128 245 253 263 272 283 295 307 320 335 351 368 387 409 433 460 Default (hex) 08000 Name DCCF
The divider for the CLKI input is determined by the content of the DCCF register. This register allows 32 settings of the DC/DC converter clock frequency fdc: f CKLI f SW = -----------------------2 (m + n)
n {0, 15} , m { 16, 32 }
(EQ 1)
In order to reduce interference noise in AM-reception, the oscillator frequency may be adjusted in 16 steps in order to allow the system controller to select a base frequency that does not interfere with an other application. The following algorithm may be used to select an appropriate value for DCCF:
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PRELIMINARY DATA SHEET
MAS 3506D
Table 3-10: Control Registers, continued Address (hex) 8e continued R/W Function int selectfrequency(double fstation) { double fq,fdiv; double fqmax = 0; int imax = 0; for (int i=0;i<16;i++) { fdiv = 14725000/(2*(32+i)); fq = fstation/fdiv; fq = fabs(fq-floor(fq)-0.5)*fdiv; if (fq > fqmax) imax = i; } return imax; } Modifications to this algorithm are applicable. It may be useful to finish this procedure if fqmax reaches a certain minimum value, or a preprocessed table for all possible AM-carrier frequencies may be stored in ROM for the controller. DC/DC-Converter Voltage The output voltage is selected with bits 16...14 and 9. There is a threshold between the output voltage of the DC/DC converter and the internal voltage monitor. The PUP signal becomes inactive when the output drops below the monitor voltage. Setting bit [16:14] and [9] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DC/DC-Converter Output Voltage/V 3.57 3.46 3.35 3.25 3.14 3.04 2.94 2.83 2.73 2.63 2.52 2.42 2.32 2.22 2.12 2.02 Internal Monitor Voltage/V 3.38 3.27 3.16 3.06 2.95 2.85 2.75 2.64 2.54 2.44 2.33 2.23 2.13 2.03 1.93 1.82 Default (hex) Name DCCF continued
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MAS 3506D
Table 3-10: Control Registers, continued Address (hex) c8 R/W R Function PIO-Register
PRELIMINARY DATA SHEET
Default (hex)
Name PIO
The PIO-register is used to monitor the actual status of the PIOpins for both, PIO-output and PIO-input lines. Bit 0 of the PIO register corresponds to pin PI0, bit 1 to PI1 etc. Due to the latency of the MAS 3506D only slow events (>1 ms) can be monitored. Please also refer to Section 4.6.3.2. bit [19] BC-FRAME-TOGGLE Output level toggles with each BC-frame, tframe = 432 ms BCENABLE 0 use SID*, SII*, SIC* 1 use SID, SII, SIC BC-FRAME-SYNC 0 cleared after SCH-read operation 1 start of new frame BC-SYNC 0 unsynchronized 1 synchronized to BC Decoding-ERROR 0 no error 1 error or sync lost MPEG-FRAME-SYNC 0 cleared after anciliary data were read 1 sync to a new MPEG-frame AUD-SW This bit may be used to monitor a signal from the headphone jack that indicates switching between headphone and loudspeaker mode. bit [2:0] These three free input lines return the state logic level of the respective PIOpins. They may be used as a port expansion of the controller.
bit [18]
bit [13]
bit [12]
bit [8]
bit [4]
bit [3]
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PRELIMINARY DATA SHEET
MAS 3506D
Note! Memory cells not given in the tables must not be written.
3.5. Control and Status Memory The memory cells given in the following sections may be read (Section 3.3.9.) or written (Section 3.3.7.) in order to observe or control the operation of the MAS 3506D.
Table 3-11: Control and status memory cells Address (hex) D1:7ee R/W R Function Main Status Indicator of the BC-Decoder The Status cell returns global status information about the WorldSpace decoder. Its value is also returned by the `Default Read' command as described in Section 3.3.10. bit [15:12] BRI 0 1...8 bit [11:8] NSC 0 ... 7 bit [7:4] bit [3] MCRC 0 1 MFS 0 1 BCS 0 1 Bit Rate Index Reserved n*16 kbit/s Zero-based number of available Service Components 1 SC available ... 8 SCs available reserved MPEG CRC Error no CRC-error in the last BC-frame CRC-error occured in the last BC-frame MPEG frame sync indication no MPEG synchronisation MPEG synchronisation Broadcast Channel frame sync indication no BC synchronisation BC synchronisation Default Name Status
bit [2]
bit [1]
While the signals MPEG-FRAME-SYNC and BC-FRAME-SYNC in the PIO-register c8hex rise with the beginning of each frame, the signals MFS and BFS are stable as long as a valid bitstream is received. bit [0] S 0 1 Synchronized state not in synchronized state (e.g. no bitstream) MAS 3506D is synchronized and decoding
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MAS 3506D
Table 3-11: Control and status memory cells, continued Address (hex) D1:7ef R/W R/W Function Service Component Selection (0..7) and Decoding Control bit [15] OutputMute 0 normal operation 1 mute output AutoScan Autoscan function 0 disable autoscan function 1 enable autoscan function, skip non-audio SCs BCChange Broadcast Channel Change 0 cleared on SCH-rescynchronization 1 clears all previous SCH-information
PRELIMINARY DATA SHEET
Default
Name NumSC
bit [14]
bit [13]
Setting this bit clears all previous SCH-information and thus prepares the MAS 3506D for a BC-change. This ensured the availability of the correct SCH-data for the new BC. bit [12] MPEGResync 0 allows resynchronization only after SCH-detection 1 MPEG-resynchronization enabled reserved, set to 0 SC 0 ... 7 D1:7f0 R/W Zero-based number of audio Service Component to be decoded decode SC 1 decode SC 8 BCFrameCnt
bit [11:3] bit [2:0]
Counter for Broadcast Channel Frames bit [15:0] BCCount Counter for the decoded Broadcast Channel frames
The BCFrameCnt ist incremented by one for each successfully decoded BC-frame (432 ms) since reset. This address is writable, thus the controller may reset/preset the content at any time to an arbitrary value. D1:7f1 R/W Counter for MPEG Frames bit [15:0] MPEGFrameCnt Counter for the decoded MPEG-frames MPEGFrameCnt
The MPEGFrameCnt ist incremented by one for each successfully decoded MPEG-frame (24...72 ms) since reset. This address is writable for a reset/preset.
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PRELIMINARY DATA SHEET
MAS 3506D
Table 3-11: Control and status memory cells, continued Address (hex) D1:7f3 R/W R Function System Error Indication bit [10:0] ErrorCode Last error of WorldSpace decoding 1xxhex 100hex 101hex 102hex 103hex 104hex 105hex 106hex Buffer problem, causes a firmware reset: ErrorInputTimeOut: Input time-out ErrorServicePreambleWrong: Service preamble wrong ErrorBufferOverflow: Input buffer overflow ErrorBufferUnderrun: Buffer underflow ErrorOutputTimeout: Output time-out ErrorBitrateIntexChanged: Bitrate index has changed ErrorNoLayer3SyncNextFram: No synchronization found in input bitstream BC-error, causes a BC-resynchronization: ErrorSCToDecodeOutOfRange: SC to decode is not available ErrorSCTypeWrong: SC has no audio ErrorStartBCSync: The controller has indicated a BC-change (signal BCChange) MPEG-error, causes an MPEGresynchronization: ErrorSCToDecodeUserChange: A new SC was selected Error: Error: Error: Sampling rate changed Default Name ErrorCode
2xxhex 100hex 101hex 1ffhex
3xxhex 300hex 301hex 302hex 303hex
If an error occurs during decoding of the Broadcast Channel bitstream a number describing the error will be copied into this memory cell. The content always keeps a value corresponding to the last detected error. D1:7f4 R/W Counter for All Decoding Errors bit [15:0] ErrorCnt Counter for all decoding errors ErrorCnt
The ErrorCnt is incremented by one for each decoding error since reset. This address is writable for a reset/preset. This counter is valuable for long-time observations. For identification of the last error see D1:7f3
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MAS 3506D
Table 3-11: Control and status memory cells, continued Address (hex) D1:7f5 R/W R Function Bits 12..16 of MPEG-Header
PRELIMINARY DATA SHEET
Default
Name MPEGStatus1
The MPEGStatus1 memory cell provides a direct copy of bits 16...12 of the acual MPEG-header. This cell will be updated immediatley after the MPEG-header has beed read from the bitstream. bit [12:8] bit [12:11] MPEGID 00 01 10 11 bit [10:9] Layer 00 01 10 11 Copy of bits 16...12 of the MPEG-header Bits 13 and 12 of the MPEG-header MPEG 2.5 reserved MPEG 2 MPEG 1 Bits 11 and 10 of the MPEG-header reserved Layer 1* Layer 2* Layer 3
bit [8]
Protection 0 CRC-protected 1 no CRC reserved private bits CRC Error 0 no error 1 a CRC-error has occured 0 1 Invalid Frame normal operation an invalid frame has occured
bit [7] bit [6:2] bit [1]
bit [0]
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PRELIMINARY DATA SHEET
MAS 3506D
Table 3-11: Control and status memory cells, continued Address (hex) D1:7f6 R/W R Function Bit 32...17 of MPEG-Header The MPEGStatus2 memory cell provides a direct copy of bits 32...17 of the acual MPEG-header. This cell will be updated immediately after the MPEG-header has beed read from the bitstream. MPEG 1 Layer 3 bit[15:12] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 bit[11:10] 00 01 10 11 bit[9] bit[8] bit[7:6] Mode 00 01 10 11 Datarate in kbit/s free 32 40 48 56 64 80 96 112 128 160* 192* 224* 256* 320* reserved free 8 16 24 32 40 48 56 64 80 96 112 128 144* 160* reserved free 8 16 24 32 40 48 56 64 80 96 112 128 144* 160* reserved MPEG 2 Layer 3 MPEG 2.5 Layer 3 Default Name MPEGStatus2
Sampling frequency/kHz 44.1* 48 32 reserved 22.05* 24 16 reserved 11.025* 12 8 reserved
padding bit private bit stereo joint stereo dual channel reserved ms_stereo off off on on
bit[5:4]
Joint stereo: Mode extension intensity stereo 00 off 01 on 10 off 11 on Copyright 0 not protected 1 protected Original/Copy 0 copy 1 original
bit[3]
bit[2]
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MAS 3506D
Table 3-11: Control and status memory cells, continued Address (hex) D1:7f6 continued R/W Function bit[1:0] Emphasis 00 01 10 11
PRELIMINARY DATA SHEET
Default
Name
none 50/15 s reserved CCITT J.17 OutputConfig
D1:7f7
R/W
Configures the Serial Audio Output Interface bit [19:0] OutputConfig 0 generate 32-bit audio samples 16 generate 16-bit audio samples 80000 left left gain (please refer to Sections 3.3.1. and 3.5.1.) 00000 left right gain 00000 right left gain 80000 right right gain
D1:7f8
R/W
Left Left Gain bit [19:0] LL
LL
D1:7f9
R/W
Left Right Gain bit [19:0] LR
LR
D1:7fa
R/W
Right Left Gain bit [19:0] RL
RL
D1:7fb
R/W
Right Right Gain bit [19:0] RR
RR
* Modes marked with an asterisk are not used in the WorldSpace system.
3.5.1. Volume Matrix left audio The digital baseband volume matrix is used for controlling the digital gain as shown in Fig. 3-2. Table 3-12 shows the proposed settings for the four volume matrix coefficients for stereo, left, and right mono. The gain factors are given in fixed point notation as desribed in Section 3.3.1. Table 3-12: Settings for the digital volume matrix Memory location (hex) Name Stereo (default) Mono left Mono right D1: 7f8 LL D1: 7f9 LR 0 D1: 7fa RL 0 0 D1: 7fb RR
-1
LL
+
-1
LR
-1
RL
-1.0 -1.0
0
-1.0
0
right audio
-1
RR
+
-1.0
0
Fig. 3-2: Digital volume matrix
-1.0
-1.0
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PRELIMINARY DATA SHEET
MAS 3506D
Table 3-13: Volume matrix conversion (dB into hexadecimal) Volume (in dB) 0 Hexa decimal 80000 8DEB8 9A537 A5621 AF3CD B8053 BFD92 C6D31 CD0AD D2958 D785E DBECC DFD91 E3583 E675F E93CF EBB6A EDEB6 EFE2C F1A36 Volume (in dB) Hexa decimal F3333 F4979 F5D52 F6F03 F7EC8 F8CD5 F995B FA485 FAE78 FB756 FBF3D FC648 FCC8E FD227 FD723 FDB95 FDF8B FE312 FE638 FE905 Volume (in dB) Hexa decimal FEB85 FEDBF FEFBB FF180 FF314 FF47C FF5BC FF6DA FF7D9 FF8BC FF986 FFA3A FFADB FFB6A FFBEA FFC5C FFCC1 FFD1B FFD6C FFDB4 Volume (in dB) Hexa decimal FFDF4 FFE2D FFE60 FFE8D FFEB5 FFED9 FFEF9 FFF16 FFF2F FFF46 FFF5A FFF6C FFF7C FFF8B FFF97 FFFA3 FFFAD FFFB6 FFFBE FFFC5 Volume (in dB) Hexa decimal FFFCC FFFD1 FFFD6 FFFDB FFFDF FFFE3 FFFE6 FFFE9 FFFEB FFFED FFFEF FFFF1 FFFF3 FFFF4 FFFF6 FFFF7 FFFF8 FFFF9 FFFF9 FFFFA
-20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39
-40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59
-60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79
-80 -81 -82 -83 -84 -85 -86 -87 -88 -89 -90 -91 -92 -93 -94 -95 -96 -97 -98 -99
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19
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MAS 3506D
4. Specifications 4.1. Outline Dimensions
PRELIMINARY DATA SHEET
10 x 0.8 = 8 0.1 0.17 0.06 33 34 13.2 0.2 23 22 10 0.1 0.8 10 0.1 0.8
44 1 11 13.2 0.2
12
2.0 0.1 2.15 0.2 0.1
0.34 0.05
SPGS706000-5(P44)/1E
Fig. 4-1: 44-Pin Plastic Metric Quad Flat Package (PMQFP44) Weight approximately 0.4g Dimensions in mm
0.9 0.2
1.1 x 45 6 7 1.6
17.52 0.12
10 x 1.27 = 12.7 0.1 1.27 1.2 x 45
1
40 39
0.48 0.06
10 x 0.8 = 8 0.1
2
0.71 0.05
15.7 0.3
16.5 0.1
6
2
6
8.6
17 18 17.52 0.12 28
29 1.9 0.05 4.05 0.1 4.75 0.15
0.27 0.03
0.1
16.5 0.1
SPGS704000-1(P44/K)/1E
Fig. 4-2: 44-Pin Plastic Leaded Chip Carrier Package (PLCC44) Weight approximately 2.5 g Dimensions in mm Note: The PLCC44-package has limited availability
Caution: Start pin and orientation of pin numbering is different for PLCC and PMQFP-housings.
30
10 x 1.27 = 12.7 0.1
1.27
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PRELIMINARY DATA SHEET
MAS 3506D
4.2. Pin Connections and Short Descriptions NC X not connected, leave vacant obligatory, pin must be connected as described in application informations Pin No.
PMQFP 44-pin PLCC 44-pin
LV VDD VSS
if not used, leave vacant connect to positive supply connect to ground Short Description
Pin Name
Type
Connection
(If not used)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
TE POR I2CC I2CD VDD VSS DCEN EOD RTR RTW DCSG DCSO VSENS PR PCS PI19 PI18 PI17 SIC*/PI16 SII*/PI15 SID*/PI14 PI13 PI12 SOD/PI11 SOI/PI10 SOC/PI9 PI8 XVDD
I I IO IO Supply Supply I O O O Supply O I I I O I I I I I O O O O O O Supply
VSS VDD X X X X VSS LV LV LV VSS VSS VDD VDD VDD LV VSS VSS X VSS X LV LV LV LV LV LV X
Test enable Reset , active low I2C clock line I2C data line Positive supply for digital parts Gound supply for digital parts Start and enable DC/DC converter PIO end of DMA, active low PIO ready to read, active low PIO ready to write, active low DC converter transistor ground DC converter transistor open drain DC converter voltage sense PIO DMA request or Read/Write PIO chip select , active low BC-Frame-Toggle BCINENABLE PIO data [17], reserved PIO data[16] (SIC*) PIO data[15] (SII*) PIO data [14] (SID*) BC-FRAME-SYNC BC-SYNC Serial output data Serial ouput frame identification Serial output clock Decoding-error Positive supply of output buffers
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MAS 3506D
PRELIMINARY DATA SHEET
Pin No.
PMQFP 44-pin PLCC 44-pin
Pin Name
Type
Connection
(If not used)
Short Description
29 30 31 32 33 34 35 36 37 38 39 40 41
22 21 20 19 18 17 16 15 14 13 12 11 10
XVSS SID/PI7 SII/PI6 SIC/PI5 PI4 PI3 PI2 PI1 PI0 CLKO PUP WSEN WRDY
Supply I I I O I I I I O O I O
X X VSS X LV VSS VSS VSS VSS LV LV X LV
Ground of output buffers Serial input data Serial input frame identification Serial input clock MPEG-frame sync AUD-SW, information from headphone jack Reserved Reserved Reserved Clock output (nominal 24.576 MHz) Power Up, i.e. status of voltage supervision Enable DSP and DC/DC converter If WSEN=0: Valid clock input at CLKI If WSEN=1: Clock synthesizer PLL locked Supply for analog circuits Clock input Ground supply for analog circuits
42 43 44
9 8 7
AVDD CLKI AVSS
Supply I Supply
VDD X VSS
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PRELIMINARY DATA SHEET
MAS 3506D
4.3.3. Control Lines I2CC I2CD SCL SDA IN/OUT IN/OUT
4.3. Pin Descriptions 4.3.1. Power Supply Pins Connection of all power supply pins is mandatory for the function of the MAS 3506D. VDD VSS SUPPLY SUPPLY
Standard I2C control lines. Normally there are pull-up resistors from each line to VDD.
4.3.4. Parallel Interface Control Lines The VDD/VSS pair is internally connected with all digital modules of the MAS 3506D. XVDD XVSS SUPPLY SUPPLY PR PCS RTR RTW EOD IN IN OUT OUT OUT
The XVDD/XVSS pins are the supply lines for the pin output buffers. AVDD AVSS SUPPLY SUPPLY
PIO handshake lines. Their use depends on the actual firmware on the MAS 3506D. Usage of these lines in the standard WorldSpace configuration is not planned.
4.3.5. Parallel Interface Data Lines The AVDD/AVSS pair is internally connected with the analog blocks of the MAS 3506D, i.e. clock synthesizer and supply voltage supervision circuits. General purpose Parallel IO pins. The information of the input and output signals may also be read from Register c8hex (please refer to Table 3-10 in Section Section 3.4. on page 20). PI19 BC-FRAME-TOGGLE OUT
4.3.2. DC/DC Converter Pins DCEN DC/DC ENABLE IN
The DCEN input signal starts and enables the DC/DC converter operation. DCSG SUPPLY
The BC-FRAME-TOGGLE output toggles its state after each correctly decoded Broadcast Channel Frame (432 ms). This pin can be used for monitor the proper function of the system. PI18 BCINENABLE IN
The DC converter Signal Ground pin is used as a basepoint for the internal switching transistor of the DC/DC converter. It must always be connected to ground. DCSO OUT
PI18 is used as input pin to sense the status of the BCINENABLE line at the WorldSpace connector. On low input level the alternative BC-input lines SIC*, SII* and SID* are activated and SIC, SII, SID are deactivated. PI17 PI16 PI15 PI14 RESERVED SIC* SII* SID* IN/OUT IN IN IN
DCSO is an open drain output and should be connected with external circuitry (inductor/diode) to start the DC/DC converter. When the DC/DC converter is not used, it has to be connected to VSS. VSENS IN
The VSENS pin is the input for the DC/DC converter feedback loop. It must be connected directly with the Schottky diode and the capacitor as shown in Fig. 2-5 on page 10. When the DC/DC converter is not used, it has to be connected to VDD.
The SIC*, SID*, and SII* may be configured as alternative serial input lines in order to support alternative serial digital sources. SID* (PI14) is used as Broadcast Channel data input from the Broadcast Channel I/O interface.
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MAS 3506D
PI13 BC-FRAME-SYNC OUT
PRELIMINARY DATA SHEET
4.3.6. Voltage Supervision And Other Functions CLKI CLKO IN OUT
The BC-FRAME-SYNC is reset after POR and set to `1' after each correctly decoded SCH. It will only be cleared if the controller reads out SCH information from the MAS 3506D. PI12 BC-SYNC OUT
CLKI and CLKO are the input and output clock lines to be connected to the DRD 3515A. CLKI expects 14.725 MHz, CLKO delivers 24.576 MHz synchronous to the audio data stream. PUP POWER UP OUT
The BC-SYNC is set, if the MAS 3506D is in the state of proper decoding of the Broadcast Channel bitstream. PI8 DECODING-ERROR OUT
The PUP output indicates that the power supply voltage exceeds its minimal level (software adjustable). WSEN DSP ENABLE IN
The Decoding-Error pin is activated, if during decoding of the Broadcast Channel, the MPEG frame an error occurs or if no input bitstream is applied. PI4 MPEG-FRAME-SYNC IN
WSEN enables DSP and DC/DC-converter operation. It must also be set to activate the control interface e.g. to reprogram the DC/DC-converter. WRDY OUT
The MPEG-FRAME-SYNC signal indicates that an MPEG header has been decoded properly and the internal MPEG decoder is in a synchronized state. The MPEG-FRAME-SYNC signal is inactive after PowerOn Reset and will be activated when a valid MPEG Layer 3 header has been recognized. The signal will be cleared if the ancillary data information is read out by the controller via I2C interface. PI3 AUD-SW IN
WRDY has two functionalities depending on the state of the WSEN signal. If WSEN = 0, it indicates that a valid clock has been recognized at the CLKI clock input. If WSEN = 1, the WRDY output will be set to `0' until the internal clock synthesizer has locked to the incoming audio data stream, and thus, the CLKO clock output signal is valid.
The AUD-SW input may sense the headphone jack and deposit its information in Bit 3 of register c8hex (please refer to Table 3-10 on page 20.) This way the controller can get the information weather a loudspeaker or a headphone should be supplied and can set the BAS_INVR bit in DRD 3515A's register GLB_CONFIG accordingly. PI2 PI1 PI0 RESERVED RESERVED RESERVED IN IN IN
4.3.7. Serial Input Interface SID SII SIC IN IN IN
Data, Frame Indication and Clock line of the serial input interface. The SII line should be connected with VSS in the standard WorldSpace mode. The SID and SIC lines are used for the Broadcast Channel input.
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PRELIMINARY DATA SHEET
MAS 3506D
4.3.9. Miscellaneous OUT OUT OUT POR IN
4.3.8. Serial Output Interface SOD SOI SOC
The Power-On Reset pin is used to reset the digital parts of the MAS 3506D. TE IN
Data, Frame Indication and Clock line of the serial audio output interface (I2S). The SOC line can be deactivated, if only the DRD 3515A D/A converter is connected. The SOI indicates, whether the left or the right audio sample is transmitted. In the default setting a left audio sample always corresponds to SOI = low.
The TE pin is for production test only and must be connected with VSS in all applications.
4.4. Pin Configuration
XVDD XVSS SID SII SIC PI4 PI8 SOC SOI SOD PI12 VDD I2CD I2CC POR TE
VSS DCEN EOD RTR RTW DCSG
33 32 31 30 29 28 27 26 25 24 23 PI3 PI2 PI1 PI0 CLKO PUP WSEN WRDY AVDD CLKI AVSS 34 35 36 37 38 39 40 41 42 43 44 1 TE POR I2CC I2CD VDD VSS 2 3 4 5 6 7 8 9 10 11 DCSG RTW RTR EOD DCEN 22 21 20 19 18 PI13 SID SII SIC PI17 PI18 PI19 PCS PR VSENS DCSO AVSS CLKI AVDD WRDY WSEN PUP CLKO PI0 PI1 PI2 PI3 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 DCSO VSENS PR PCS PI19 PI18 PI17 SIC SII SID PI13
MAS 3506D
17 16 15 14 13 12
MAS 3506D
34 33 32 31 30 29
18 19 20 21 22 23 24 25 26 27 28 PI4 SIC SII SID XVSS XVDD PI8 SOI SOC PI12 SOD
Fig. 4-3: PMQFP44 package
Fig. 4-4: PLCC44 package
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MAS 3506D
4.5. Internal Pin Circuits
PRELIMINARY DATA SHEET
DCSO TTLIN VSS Fig. 4-5: Input pins PCS, PR DCSG
Fig. 4-11: Input/Output pins DCSO, DCSG
XVDD P Fig. 4-6: Input pin TE, DCEN N XVSS Fig. 4-12: Output pins WRDY, RTW, EOD, RTR, CLKO, PUP Fig. 4-7: Input pins WSEN, POR VSENS
Fig. 4-8: Input pin CLKI VSS XVDD P N XVSS Fig. 4-9: Input/Output pins PI0...PI4, PI8, SOC, SOI, SOD, PI12...PI19 N XVSS VDD Fig. 4-14: Input/Output pins SIC, SII, SID XVDD P Fig. 4-13: Input pin VSENS
N VSS Fig. 4-10: Input/Output pins I2CC, I2CD
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PRELIMINARY DATA SHEET
MAS 3506D
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS PMAX VSUP VIdig IIdig IOut IOutDC VII2C Parameter Ambient operating temperature Storage temperature Power dissipation Supply voltage Input voltage, all digital inputs Input current, all digital inputs Current, all digital output Current Input voltage, I2C-Pins DCSO I2CC, I2CC VDD, XVDD, AVDD VDD, XVDD, AVDD Pin Name Min. Max. 85 125 600 5.5 Unit C C mW V V mA A A V
-40 -40
-0.3 -20
VSUP +0.3 +20 0.5 1.5
-0.3
5.5
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
4.6.2. Recommended Operating Conditions Symbol TA VSUP Parameter Ambient temperature range Supply voltage VDD, XVDD, AVDD Pin Name Min. Typ. Max. 85 3.0 3.6 Unit C V
-40
2.7
Reference Frequency Generation CLKF CLKI_V CLKAmp Clock frequency Clock input voltage Clock amplitude CLKI 0 0.5 14.725 VSUP MHz V Vpp
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MAS 3506D
PRELIMINARY DATA SHEET
Symbol Levels IIL27 IIH36 IIH33 IIH30 IILD IIHD
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Input low voltage at VSUP = 2.7 V ... 3.6 V Input high voltage at VSUP = 2.7 V ... 3.6 V Input high voltage at VSUP = 2.7 V ... 3.3 V Input high voltage at VSUP = 2.7 V ... 3.0 V Input low voltage Input high voltage
POR I2CC, I2CD, DCEN, WSEN
0.4 1.8 1.7 1.6
V V V V
PI1), SII, SIC, SID, PR, PCS, TE, PI, SII, SIC, SID, PR, PCS, CLKI SIC, CLKI
0.4 VSUP- 0.5
V V
Trf
Rise/fall time of digital inputs
10
ns
Dcycle
Duty cycle of digital clock inputs
40
50
60
%
DC-DC converter external circuitry C1 VF L
1) 2) 3) 4)
Blocking capacitor (< 100 m ESR)2) Schottky diode forward voltage3) Inductance of ferrite ring core coil4)
VSENS, DCSG DCSO, VSENS DCSO
330 0.35 22
F
V
H
i = 0 to 4, 8 , 12 to 19 Sanyo Oscon 6SA330M (distributed by Endrich Bauelemente, D-72202 Nagold-lselshausen) ZETEX ZMCS1000 (distributed by ZETEX, D-81673 Munchen), standard Schottky 1N5817 C8 R/4L, SDS0604 (distributed by Endrich Bauelemente, see above)
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Micronas
PRELIMINARY DATA SHEET
MAS 3506D
4.6.3. Characteristics at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27C, VSUP = 3.5 V, CLKF = 14.725 MHz, duty cycle = 50%
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Supply Voltage ISUP Current consumption VDD, XVDD, AVDD 32 17 11 Digital Outputs and Inputs VDOL VDIH Output low voltage Output high voltage SOI1), SOC1), SOD1), EOD, RTR, RTW, WRDY, PUP, CLKO PI PI, SII, SIC, SID, PR, PCS, CLKI 0.3 VSUP- 0.3 V V Iload = 6mA Iload = 6mA mA mA mA 2.7 V, sampling frequency 32kHz 2.7 V, sampling frequency 24 kHz 2.7 V, sampling frequency 12 kHz
ZDigI IDLeak
Input impedance Digital input leakage current
7 -1 1
pF A 0 V < Vpin < VSUP
1)
in low impedance mode
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MAS 3506D
4.6.3.1. I2C Characteristics
PRELIMINARY DATA SHEET
at T = TA, VSUP =2.7 to 3.6 V, typ. values at TA = 27C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol RON fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2COL II2COH tI2COL1 tI2COL2 tW Parameter Output resistance I2C bus frequency I2C Start condition setup time I2C Stop condition setup time I2C clock low pulse time I C clock high pulse time I2C data hold time before rising edge of clock I2C data hold time after falling edge of clock I2C output low voltage I2C output high leakage current I2C data output hold time after falling edge of clock I2C data output setup time before rising edge of clock Wait time
2
Pin Name I2CC, I2CD I2CC I2CC, I2CD I2CC, I2CD I2CC I2CC I2CC I2CC I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD
Min.
Typ.
Max. 60 400
Unit kHz ns ns ns ns ns ns
Test Conditions Iload = 5 mA, VSUP = 2.7 V
300 300 1250 1250 80 80 0.3 1 20 250 0 0.5 4
V uA ns ns ms
ILOAD = 5 mA VI2CH = 3.6 V
fI2C = 400kHz
1/fI2C tI2C4
H L
tI2C3
I2CC tI2C1 tI2C5 tI2C6 tI2C2
H L
I2CD as input tI2COL2 tIC2OL1
H L
I2CD as output
Fig. 4-15: I2C timing diagram
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PRELIMINARY DATA SHEET
MAS 3506D
4.6.3.2. Timing of PIO-Signals Table 4-1: PIO Characteristics
Symbol tBCTP Parameter BC-frame toggle time Pin Name PI19 Min. Typ. 432 Max. Unit ms Test Conditions
Behavior of the FRAME signals The BC-FRAME-TOGGLE toggles its level from '1' to '0' and vice-versa every 432 ms. The BC-FRAMESYNC signal is set to '1' after the internal decoding process for the Service Control Header has been finished for one frame. The signal could be used as an interrupt input for the controller that triggers the read out of the Service Control Header. As soon as the MAS 3506D has recognized the corresponding read command for the SCH, the BC-FRAME-SYNC is reset
before sending the first data word. The time tread depends on the response time of the controller. This behavior reduces the possibility of not recognizing the BC-FRAME-SYNC active state, if no controller interrupt line is available for this purpose. A similar behavior is implemented for MPEG-FRAMESYNC signal. However the frame period is restricted to the MPEG frame length, the reset is initiated by issuing a 'Read Ancillary MPEG Data' command.
Vh VL
432 ms BC-FRAME-TOGGLE (PI 19)
Vh VL
432 ms tread
BC-FRAME-SYNC (PI13) Fig. 4-16: Schematic timing of BC-FRAME signals
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MAS 3506D
4.6.3.3. I2S Bus Characteristics - SDI
PRELIMINARY DATA SHEET
at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol tSICLK tSIIDS tSIIDH tbw Parameter I2S clock input clock period I2S data setuptime before falling edge of clock I2S data hold time Burst wait time Pin Name SIC SIC, SID SID SIC, SID Min. 480 50 50 480 tSICLK100 Typ. Max. Unit ns ns ns Test Conditions multimedia mode, mean data rate < 150 kbit/s
TSICLK
H
SIC
L
H
(SII)
L
H
SID
L
TSIIDS Fig. 4-17: Serial input
TSIIDH
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Micronas
PRELIMINARY DATA SHEET
MAS 3506D
4.6.3.4. I2S Characteristics - SDO at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol tSOCLK tSOISS tSOODC Parameter I2S clock output period I2S wordstrobe delay time after falling edge of clock I2S data delay time after falling edge of clock Pin Name SOC SOC, SOI SOC, SOD 0 0 Min. Typ. 325 Max. Unit ns ns ns Test Conditions 48 kHz Stereo 32 bit/sample
TSOCLK
H
SOC
L
H
SOI
L
TSOISS
H
TSOISS
SOD
L
TSOODC Fig. 4-18: Serial output
4.6.3.5. Firmware Characteristics at T = TA, VSUP = 2.7 to 3.6 V, typ. values at TA = 27C, VSUP = 3.0 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol Parameter Min. Typ. Max. Unit Test Conditions
Synchronization Times tbcsync tmpgsync Synchronization on Broadcast Channel Synchronization on MPEG bit streams 216 12..36 432 72 ms ms fs = 32 kHz, MPEG 2.5
Time constants tbcloop tanc tSCH Ranges PLLRange Tracking range of sampling clock recovery PLL -200 200 ppm Buffer controlled loop time constant (see Fig. 2- 5 2 on page 8) Validity of ancillary data after rising edge of MPEG-FRAME-SYNC signal Validity of SCH-data after rising edge of BC-FRAME-SYNC signal 6 400 8 10 s ms ms step response
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MAS 3506D
4.6.4. DC/DC Converter Characteristics
PRELIMINARY DATA SHEET
at T = TA, VSUP = 3.0 V, CLKF = 14.725 MHz, fsw = 230 kHz, typ. values at TA = +27 C. Unless otherwise noted: VOUT = 3.0 V, VIN = 1.2 V
Symbol VIN1 Parameter Minimum start-up input voltage Pin Name
1)
Min.
Typ. 0.9
Max. 1.1
Unit V
Test Conditions ILOAD = 0 mA DCCF = $08000 (Reset) ILOAD = 55 mA, DCCF = $08000 (Reset) ILOAD = 250 mA, DCCF = $08000 (Reset)
VIN2
Minimum operating input voltage
1)
0.6
0.9
V
1.3
1.8
V
VOUT
Output voltage range Bits 16..14, Bit 9 of DCCF Register (hex): 1C000 18000 14000 10000 0C000 08000 04000 00000 1C200 18200 14200 10200 0C200 08200 04200 00200
VSENS
3.567 3.460 3.354 3.248 3.144 3.039 2.935 2.831 2.729 2.625 2.524 2.422 2.321 2.219 2.118 2.017 VSENS -3.6 3.6
V
VIN = 1.2 V ILOAD = 50 mA
VOTOL
Output voltage tolerance
%
ILOAD = 50 mA Tj = 27 C VIN = 1.2 V VIN = 0.9...1,5 V VIN = 1.8...3.0 V ILOAD = 50 mA ILOAD = 250 mA, VOUT = 3.5 V, VIN = 2.4 V ILOAD = 50...150 mA ILOAD = 50...250 mA, VOUT = 3.5 V, VIN = 2.4 V
ILOAD1 ILOAD2 dVOUT/dVIN/ VOUT dVOUT/dVIN/ VOUT dVOUT/VOUT dVOUT/VOUT
Output current
VSENS
150 250
mA mA %/V %/V
Line regulation Line regulation
VSENS VSENS
0.35 0.7
Load regulation Load regulation
VSENS VSENS
-0.5 -0.5
% %
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PRELIMINARY DATA SHEET
MAS 3506D
Symbol hmax ISUPPLY IL,MAX RON ILEAK
Parameter Maximum efficiency Supply current Inductor current limit Switch on-resistance Switch leakage current
Pin Name
Min.
Typ. 90
Max.
Unit %
Test Conditions VIN = 3.0 V, VOUT = 3.5 V VIN = 3.0 V, ILOAD = 0, includ. switch current
VSENS DCSO, DCSG DCSO, DCSG DCSO, DCSG DCSO, DCSG DCEN, PUP DCSO 156
1.1 1.0 0.4 0.1
5 1.4
mA A
1
A
Tj = 27 C, converter = off; ILOAD = 0 A Depending on DCCF VIN = 1.0 V, ILOAD = 1 mA, PUPLIM = 010 (Reset) VSENS < 1.9 V
fSW tSTART
Switch frequency Start-up zime asserting to PUP VSENSE
230 8
460
kHz ms
fSTARTUP
1)
250
kHz
All measurements are made with a C8 R/4L 20 H, 25 m ferrite ring-core coil, Zetex ZLMCS1000 Schottky diode, and Sanyo/Oscon 6SA330M 330 F, 25 m ESR capacitors at input and output.
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MAS 3506D
4.6.5. Typical Performance Characteristics
PRELIMINARY DATA SHEET
Efficiency vs. Load Current (Vout=3.5V) 100
3.0 V 1.8 V
Efficiency vs. Load Current (Vout=3.0V) 100
2.4 V
80
Vin
80
Vin
Efficiency (%)
Efficiency (%)
60
60
0.7 V
40 Vin: 3.0V 2.4V 1.8V 10 -4 10-3 10-2 10-1 1
40
20
20
Vin: 2.4V 1.8V 1.5V 1.2V 0.9V 0.7V 10 -4 10-3 10-2 10-1 1
0
0 Load Current (A)
Load Current (A)
Efficiency vs. Load Current (Vout=2.7V) 100
Vin 2.4 V
Efficiency vs. Load Current (Vout=2.2V) 100
Vin 1.5 V
80
1.2 V
80
Efficiency (%)
Efficiency (%)
60
60
0.7 V
40 Vin: 2.4V 1.8V 1.2V 0 10 -4 10-3 10-2 10-1 1 Load Current (A)
40 Vin: 1.5V 1.2V 0.9V 0.7V 10 -4 10-3 10-2 10-1 1
20
20
0 Load Current (A)
Fig. 4-19: Efficiency vs. Load Current
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PRELIMINARY DATA SHEET
MAS 3506D
Output Voltage vs. Input Voltage Iload=250mA 3.6
3.5 V
Output Voltage vs. Input Voltage Iload=50mA 3.2
3.1 V
3.4
3
2.8 Output Voltage (V) Output Voltage (V) 3.2
3.1 V 2.7 V
2.6
3
2.4
2.2 V
2.8
2.7 V
2.2
2.6 1.5 2 2.5 3 3.5 Input Voltage (V)
Fig. 4-20: Output Voltage vs. Input Voltage
2 0.9 1.4 1.9 2.4 2.9 Input Voltage (V)
Output Voltage vs. Load Current 3.6
Vin
Output Voltage vs. Load Current 3.4
3.4
Vin=3V, 2.4V, 1.8V
3.2 3 Vin=1.5V, 0.9V
Vin
Output Voltage (V)
Output Voltage
3.2
2.8 2.6 2.4
Vin
3
2.8 2.2 2.6 0 Vin=2.4V 0.1 0.2 0.3 Vin=1.5V, 0.9V 2 0 0.02 0.04 0.06 0.08 Load Current (A)
Load Current (A)
Fig. 4-21: Output Voltage vs. Load Current
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MAS 3506D
PRELIMINARY DATA SHEET
0.8 Maximum Load Current (A)
Maximum Load Current vs. Input Voltage 6.0
No Load Supply Current vs. Input Voltage
0.6 2.2V 0.4
Vout
3.5V 4.0
Vout = 3 V
0.2
Vout= 3.5V 3.1V 2.7V 2.2V
2.0
0 0 1 2 Input Voltage (V) 3 0 0 1 2 3 Input Voltage (V)
Fig. 4-22: Maximum Load Current vs. Input Voltage Fig. 4-23: No Load Supply Current vs. Input Voltage
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Micronas
PRELIMINARY DATA SHEET
MAS 3506D
3V 3V
3V
3V 0A
0A 0A
500.00 s/Div Vin = 1.2 V; Vout = 3 V 1 Load Current 2 Output Voltage 3 Inductor Current 200.0 mA/Div 100.0 mV/Div / AC-coupled 500.0 mA/Div 1 2 3 4 V (DCEN) V (PUP) Inductor Current Output Voltage
500 s/Div Vin = 1 V; Iload = 0 mA 2.000 V/Div 2.000 V/Div 500.0 mA/Div 2.000 V/Div
Fig. 4-24: Load Transient-Response
Fig. 4-26: Startup Waveform
3V
2V
5.00 ms/Div Iload = 100 mA; Vout = 3 V 2.000 V/Div 1 Vin 2 Output Voltage 50.00 mV/Div / AC-coupled 3 Inductor Current 200.0 mA/Div Fig. 4-25: Line Transient-Response
Micronas
200 mA
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MAS 3506D
PRELIMINARY DATA SHEET
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Micronas
PRELIMINARY DATA SHEET
MAS 3506D
Micronas
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MAS 3506D
5. Data Sheet History 1. Preliminary data sheet: "MAS 3506D WorldSpace Broadcast Channel Audio Decoder, July 25, 2001, 6251-433-1PD. First release of the preliminary data sheet.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-433-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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