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CXP842P24 CMOS 8-bit Single Chip Microcomputer Description The CXP842P24 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, and remote control reception circuit besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP842P24 also provides a power-on reset function and a sleep/stop function that enables lower power consumption. This IC is the PROM-incorporated version of the CXP84224 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 64 pin SDIP (Plastic) Structure Silicon gate CMOS IC Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation * Incorporated PROM capacity 24K bytes * Incorporated RAM capacity 624 bytes * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 32s/10MHz) -- Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronization, 1 channel -- Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter -- Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO -- PWM output 14 bits, 1 channel * Interruption 14 factors, 14 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 64-pin plastic SDIP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E93839A7X-PS Block Diagram AVss XTAL PE3/NMI Vss EXTAL AVREF PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3 RST VDD Vpp PA0/AN0 to PA7/AN7 SPC700 CPU CORE CLOCK GEN./ SYSTEM CONTROL 8 A/D CONVERTER 8 PA0 to PA7 PE4/PWM 14 BIT PWM GENERATOR 7 PB0 to PB6 PB7 8 PC0 to PC7 PE2/RMC FIFO PROM 24K BYTES RAM 624 BYTES REMOCON PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 FIFO INTERRUPT CONTROLLER 8 4 2 PD0 to PD7 PE0 to PE3 PE4 to PE5 PF0 to PF7 8 SERIAL INTERFACE UNIT 0 PE0/EC0 2 8 BIT TIMER/COUNTER 0 8 BIT TIMER 1 PORT I PE5/TO PB0/CINT PE1/EC1 2 16 BIT CAPTURE TIMER/COUNTER 2 PORT G PORT F PORT E PORT D PORT C PORT B PORT A PRESCALER/ TIME BASE TIMER -2- 22 PB6/SI1 PB7/SO1 PB5/SCK1 SERIAL INTERFACE UNIT 1 3 PG0 to PG2 7 PI0 to PI6 CXP842P24 CXP842P24 Pin Assignment (Top View) Vpp PG0 PG1 PG2 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 RST XTAL EXTAL Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD PI6 PI5 PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO PE4/PWM PE3/NMI PE2/RMC PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/CINT PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 AVREF AVss Note) Vpp (Pin 1) is always connected to VDD. -3- CXP842P24 Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) (Port B) Lower 7-bit I/O port in which I/O can be set in a unit of single bits. Also, an uppermost bit (PB7) exclusively for output. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Description PA0/AN0 to PA7/AN7 I/O/Analog input Analog inputs to A/D converter. (8 pins) PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). PC0 to PC7 I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. Incorporation of pull-up resistor can be set through the software. (6 pins) External event inputs for timer/counter. (2 pins) Remote control reception circuit input. Non-maskable interruption request input. 14-bit PWM output. Rectangular wave output for 16-bit timer/counter (duty output 50%). PD0 to PD7 I/O PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI PE4/PWM PE5/TO Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output PF0 to PF7 I/O (Port F) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) -4- CXP842P24 Symbol I/O Description (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (3 pins) (Port I) 7-bit I/O ports. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (7 pins) External interruption request inputs. PG0 to PG2 I/O PI0/INT0 to PI3/INT3 PI4 to PI6 EXTAL XTAL RST AVREF AVss VDD Vpp Vss I/O/Input I/O Input Output I/O Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active, system reset. Reference voltage input for A/D converter. A/D converter GND. Positive power supply. Positive power supply for incorporated PROM writing. Connect to VDD during normal operation. GND -5- CXP842P24 Input/Output Circuit Formats for Pins Pin Port A Pull-up resistance "0" when reset Port A data Circuit format When reset PA0/AN0 to PA7/AN7 Data bus Port A direction "0" when reset IP Input protection circuit Hi-Z RD (Port A) Port A input selection "0" when reset A/D converter Input multiplexer Pull-up transistors approx. 10k 8 pins Port B Pull-up resistance "0" when reset Port B data PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 Data bus Port B direction "0" when reset Schmitt input RD (Port B) IP Hi-Z 4 pins Port B Pull-up resistance "0" when reset SCK OUT Output enable Port B output selection CINT CS0 SI0 SI1 Pull-up transistors approx. 10k PB2/SCK0 PB5/SCK1 "0" when reset Port B data Port B direction "0" when reset Schmitt input RD (Port B) IP Hi-Z Data bus 2 pins SCK in Pull-up transistors approx. 10k -6- CXP842P24 Pin Port B Pull-up resistance SO Output enable Port B output selection "0" when reset Circuit format When reset PB4/SO0 Port B data Port B direction "0" when reset IP Hi-Z Data bus RD (Port B) Pull-up transistors approx. 10k 1 pin Port B SO Output enable Port B output selection "1" when reset Port B data Internal reset signal PB7/SO1 High level Data bus 1 pin Port C RD (Port B) Pull-up transistors approx. 200k Pull-up resistance "0" when reset Port C data 2 PC0 to PC7 Hi-Z Port C direction "0" when reset Data bus RD (Port C) 1 IP 1 High current drive of 12mA possible 2 Pull-up transistors approx. 10k 8 pins PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI 4 pins -7- Port E IP Schmitt input EC0 EC1 RMC/NMI Data bus RD (Port E) Hi-Z CXP842P24 Pin Port E PWM Port E output selection Circuit format When reset PE4/PWM "0" when reset Port E data Data bus "1" when reset RD (Port E) High level 1 pin Port E Ouput enable TO Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data "1" when reset Data bus RD (Port E) PE5/TO High level 1 pin Port D Port F Port G Port I PD0 to PD7 PF0 to PF7 PG0 to PG2 PI4 to PI6 Pull-up resistance "0" when reset Port data Port direction "0" when reset Data bus RD IP Hi-Z Pull-up transistors approx. 10k 22 pins -8- CXP842P24 Pin Port I Circuit format Pull-up resistance "0" when reset Port data When reset PI0/INT0 to PI3/INT3 Port direction "0" when reset Data bus RD INT0 INT1 INT2 INT3 IP Hi-Z 4 pins Pull-up transistors approx. 10k EXTAL XTAL EXTAL IP IP * Diagram shows circuit composition during oscillation. * Feedback resistor is removed during stop. Oscillation 2 pins XTAL Pull-up resistor RST OP Mask option IP Schmitt input Power-on reset function (mask option) Low level 1 pin -9- CXP842P24 Absolute Maximum Ratings Item Symbol VDD Supply voltage Vpp AVSS Input voltage Output voltage High level output current VIN VOUT IOH Ratings -0.3 to +7.0 -0.3 to +13.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -10 to +75 -55 to +150 1000 Unit V V V V V mA mA mA mA mA C C mW Output per pin Total for all output pins Incorporated PROM (Vss = 0V reference) Remarks High level total output current IOH Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL IOLC IOL Topr Tstg PD Value per pin, excluding large current outputs Value per pin2 for large current outputs Total for all output pins 1 VIN and VOUT must not exceed VDD + 0.3V. 2 The high current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. - 10 - CXP842P24 Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.5 Vpp VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr Max. 5.5 5.5 5.5 V V V V V V V C V Unit (Vss = 0V reference) Remarks High-speed mode guaranteed operation range1 Low-speed mode guaranteed operation range1 Guaranteed data hold range during stop 5 2 Hysteresis input3 EXTAL4 2 Hysteresis input3 EXTAL4 Vpp = VDD 0.7VDD 0.8VDD VDD VDD VDD - 0.4 VDD + 0.3 0 0 -0.3 -10 0.3VDD 0.2VDD 0.4 +75 1 High-speed mode is 1/2 frequency demultiplication clock selection; low-speed mode is 1/16 frequency demultiplication clock selection. 2 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF, PG, PI4 to PI6). 3 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2, INT3. 4 Specifies only during external clock input. 5 Vpp and VDD should be set to the same voltage. - 11 - CXP842P24 Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE4, PE5, PF, PG, PI PC IIHE IILE Input current IILR IIL I/O leakage current IIZ EXTAL RST PA to PD1, PF, PG, PI1 PE0 to PE3 Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V VDD = 5.5V, VI = 0, 5.5V High-speed mode operation (1/2 frequency demultiplier clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Power supply current2 IDDS1 VDD Sleep mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Stop mode IDDS3 Pins other than PB7, PE4, PE5, AVREF, VDD, VSS VDD = 5.5V, termination of 10MHz crystal oscillation . 30 A 1.1 8 mA 0.5 -0.5 -1.5 (Ta = -10 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 -400 -2.0 -10 10 Typ. Max. Unit V V V V V A A A mA A A VOL IDD1 18 40 mA Input capacity CIN Clock 1MHz 0V for no-measured pins 10 20 pF 1 Pins PA to PD, and PF, PG, PI specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. (Excludes output PB7) 2 When all pins are open. - 12 - CXP842P24 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time 1 Symbol fC Pin (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms XTAL Fig. 1, Fig. 2 EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 tXL, tXH tCR, tCF tEH, tEL tER, tEF tsys + 501 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") 1/fc EXTAL VDD - 0.4V 0.4V tXH tCF tXL tCR Fig. 1. Clock timing Crystal oscillation Ceramic oscillation External clock EXTAL C1 XTAL C2 EXTAL XTAL 74HC04 Fig. 2. Clock applied condition EC0 EC1 0.8VDD 0.2VDD tEH tEF tEL tER Fig. 3. Event count clock timing - 13 - CXP842P24 (2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High and Low level widths SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0 (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 tsys + 100 8000/fc - 50 100 200 SI0 SI0 tsys + 200 100 SO0 tsys + 200 100 ns ns tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. - 14 - CXP842P24 tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD Fig. 4. Serial transfer CH0 timing - 15 - CXP842P24 Serial transfer (CH1) Item SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Symbol Pin SCK1 (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data Fig. 5. Serial transfer CH1 timing - 16 - CXP842P24 (3) A/D converter characteristics (Ta = -10 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT1 VFT2 Ta = 25C VDD = 5.0V VSS = AVSS = 0V -10 4930 160/fADC3 12/fADC3 AVREF AN0 to AN7 Operation mode AVREF IREFS Sleep mode Stop mode VDD - 0.5 0 0.6 VDD AVREF 1.0 10 70 5050 Symbol Pin Condition Min. Typ. Max. 8 3 150 5120 Unit Bits LSB mV mV s s V V mA A tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current FFH FEH Digital conversion value Linearity error 01H 00H VZT Analog input VFT 1 VZT : Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT : Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the below values due to ADC operation clock selection. During PS2 selection, fADC = fc/2 During PS1 selection, fADC = fc Fig. 6. Definition of A/D converter terms - 17 - CXP842P24 (4) Interruption, reset input Item (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 INT3 NMI RST tIH Condition Min. Max. Unit External interruption High and Low level widths tIH tIL tRSL 1 s Reset input Low level width 32/fc tIL s 0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge.) 0.2VDD tIL tIH Fig 7. Interruption input timing tRSL RST 0.2VDD Fig. 8. RST input timing (5) Power-on reset Item Power supply rising time Power supply cut-off time Symbol (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin VDD Condition Power-on reset Repetitive power-on reset Min. 0.05 1 Max. 50 Unit ms ms tR tOFF VDD 4.5V 0.2V 0.2V tR The power supply shoule rise smoothly. tOFF Fig. 9. Power-on reset - 18 - CXP842P24 Appendix (i) Main clock (ii) Main clock EXTAL XTAL Rd EXTAL XTAL Rd C1 C2 C1 C2 Fig. 10. SPC700 series recommended oscillation circuit Manufacturer Model CSA4.19MG CSA8.00MTZ fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 C1 (pF) C2 (pF) Rd () Circuit example (i) 30 30 0 (ii) MURATA MFG CO., LTD. CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.0MTW RIVER HC-49/U03 ELETEC CORPORATION 12 12 0 (i) KINSEKI LTD. 27 20 27 20 HC-49/U (-S) 8.00 10.00 0 Those marked with an asterisk () signify types with built-in ground capacitance (C1, C2). Product List Optional item Package ROM capacity Reset pin pull-up resistor Power-on reset circuit Mask 64-pin plastic SDIP 20K bytes/24K bytes Existent/non existent Existent/non existent CXP842P24Q-164-pin plastic SDIP PROM 24K bytes Existent Existent - 19 - CXP842P24 Package Outline Unit: mm 64PIN SDIP (PLASTIC) + 0.4 57.6 - 0.1 64 33 19.05 + 0.3 17.1 - 0.1 + 0.1 0.05 0.25 - 0 to 15 32 1.778 0.5 0.1 0.9 0.15 1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g - 20 - 3.0 MIN 0.5 MIN + 0.4 4.75 - 0.1 |
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