View CXP84220_169236.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXP84220/84224
CMOS 8-bit Single Chip Microcomputer
Description The CXP84220/84224 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer counter, remote control reception circuit besides the basic configurations of 8-bit CPU, ROM, RAM, and l/O port. The CXP84220/84224 also provides a power-on reset function and a sleep/stop function that enables lower power consumption. 64 pin SDIP (Plastic)
Features * Wide-range instruction system (213 instructions) to cover various types of data --16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation * Incorporated ROM capacity 20K bytes (CXP84220) 24K bytes (CXP84224) * Incorporated RAM capacity 624 bytes * Peripheral functions --A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32s/10MHz) --Serial interface SIO with 8-bit, 8-stage FIFO incorporated for data use (Auto transfer for 1 to 8 bytes), 1 channel 8-bit standard SIO, 1 channel --Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter --Remote control reception circuit Incorporated noise elimination circuit Incorporated 8-bit, 6-stage FIFO for measurement data --PWM output circuit 14 bits, 1 channel * Interruption 13 factors, 14 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 64-pin plastic SDIP * Piggyback/evaluation chip CXP84200 64-pin ceramic SDIP Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E93236A81-PS
Block Diagram
AVREF
AVss
PE3/NMI
EXTAL XTAL RST VDD Vss
PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3
PA0/AN0 to PA7/AN7 SPC700 CPU CORE CLOCK GEN./ SYSTEM CONTROL
8
A/D CONVERTER
8
PA0 to PA7
7
PB0 to PB6 PB7 8 PC0 to PC7
PE4/PWM
14 BIT PWM GENERATOR
PE2/RMC FIFO ROM 20K/24K BYTES
REMOCON
PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 FIFO 2 2 PRESCALER / TIME BASE TIMER
INTERRUPT CONTROLLER
RAM 624 BYTES
8 4 2
PD0 to PD7 PE0 to PE3 PE4 to PE5
PE0/EC0 2
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PE5/TO PB0/CINT PE1/EC1 2
16 BIT CAPTURE TIMER/COUNTER 2
PORT I
-2-
SERIAL INTERFACE UNIT 0
8
PF0 to PF7
PB6/SI1 PB7/SO1 PB5/SCK1
SERIAL INTERFACE UNIT 1
3
PG0 to PG2
7
PI0 to PI6
CXP84220/84224
CXP84220/84224
Pin Assignment (Top View)
NC PG0 PG1 PG2 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 RST XTAL EXTAL Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD PI6 PI5 PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO PE4/PWM PE3/NMI PE2/RMC PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/CINT PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 AVREF AVss
Note) NC (Pin 1) is always connected to VDD.
-3-
CXP84220/84224
Pin Description Pin code I/O Description (Port A) 8-bit l/O port. l/O can be set in a unit of single bit. Incorporation of the pull- Analog inputs to A/D converter. up resistance can be set (8 pins) through the software in a unit of 4 bits. (8 pins) (Port B) 7-bit l/O port in which l/O can be set in a unit of single bit. Also, an uppermost bit (PB7) exclusively for output. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock l/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock l/O (CH1). Serial data input (CH1). Serial data output (CH1).
PA0/AN0 to PA7/AN7
I/O/Analog input
PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output
PC0 to PC7
I/O
(Port C) 8-bit l/O port. l/O can be set in a unit of single bit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit l/O port. l/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (2 pins) (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) Remote control reception circuit input. Non-maskable interruption request input. 14-bit PWM output. Rectangular wave output for 16-bit timer/counter. (Port F) 8-bit output port. I/O can be set in a unit of single bit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port G) 8-bit I/O port. I/O can be set in a unit of single bit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (3 pins)
PD0 to PD7
I/O
PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI PE4/PWM PE5/TO
Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output
PF0 to PF7
I/O
PG0 to PG2
I/O
-4-
CXP84220/84224
Pin code PI0/INT0 to PI3/INT3 PI4 to PI6 EXTAL XTAL RST NC AVREF AVss VDD Vss Input
I/O I/O/Input I/O Input Output I/O
Description (Port l) External 7-bit output ports. I/O can be set in a unit of single bit. interruption Incorporation of pull-up resistor can be set through request inputs. the software in a unit of 4 bits. (7 pins) Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active, system reset. NC. Under normal operating conditions, connect to VDD. Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND
-5-
CXP84220/84224
Input/Output Circuit Formats for Pins Pin Port A
Pull-up resistance "0" when reset Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A input selection "0" when reset A/D converter
Input multiplexer Pull-up transistors approx. 10k
8 pins Port B
Pull-up resistance "0" when reset
PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1
Data bus
Port B data
Port B direction "0" when reset Schmitt input RD (Port B) CINT CS0 SI0 SI1
IP
Hi-Z
4 pins Port B
Pull-up resistance "0" when reset SCK OUT Output enable Port B output selection
Pull-up transistors approx. 10k
PB2/SCK0 PB5/SCK1
"0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) Schmitt input IP
Hi-Z
2 pins
SCK in
Pull-up transistors approx. 10k
-6-
CXP84220/84224
Pin Port B
Pull-up resistance SO Output enable Port B output selection
Circuit format
When reset
PB4/SO0
"0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) Pull-up transistors approx. 10k IP
Hi-Z
1 pin Port B
SO Output enable
Internal reset signal
PB7/SO1
Port B output selection "1" when reset Port B data Data bus
High level
1 pin Port C
RD (Port B)
Pull-up transistors approx. 200k
Pull-up resistance "0" when reset Port C data
2
PC0 to PC7
Port C direction "0" when reset Data bus RD (Port C) 1 Large current drive of 2 Pull-up transistors 12mA possible approx. 10k 1
Hi-Z
IP
8 pins
-7-
CXP84220/84224
Pin Port E PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI 4 pins Port E
PWM
Circuit format
Schmitt input IP EC0 EC1 RMC/NMI Data bus RD (Port E)
When reset
Hi-Z
PE4/PWM
Port E output selection "0" when reset Port E data
High level
1 pin Port E
Data bus
"1" when reset RD (Port E)
Output enable TO Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data "1" when reset Data bus RD (Pot E)
PE5/TO
High level
1 pin
Port D Port F Port G PD0 to PD7 PF0 to PF7 PG0 to PG2 PI4 to PI6
Port data Pull-up resistance "0" when reset
Port I
Port direction "0" when reset Data bus RD
IP
Hi-Z
22 pins
Pull-up transistors approx. 10k
-8-
CXP84220/84224
Pin Port I
Pull-up resistance "0" when reset Port data
Circuit format
When reset
PI0 to PI3
Port direction "0" when reset Data bus RD INT0 INT1 INT2 INT3 Pull-up transistors approx. 10k IP
Hi-Z
4 pins
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit composition during oscillation * Feedback resistor is removed during stop.
Oscillation
2 pins
XTAL
Pull-up resistor Mask option OP
RST
IP Schmitt input Power-on reset function (Mask option)
Low level
1 pin
-9-
CXP84220/84224
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage High level output current Symbol VDD AVSS VIN VOUT IOH Rating -0.3 to +7.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -20 to +75 -55 to +150 1000 Unit V V V V mA mA mA mA mA C C mW Output per pin Total for all output pins
(VSS = 0V reference) Remarks
High level total output current IOH Low level output current IOL IOLC Low level total output current IOL Operating temperature Storage temperature Allowable power dissipation Topr Tstg PD
Value per pin, excluding large current outputs Value per pin2 for large current outputs Total for all output pins
1 VIN and VOUT must not exceed VDD + 0.3V. 2 The large current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSl. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 0.7VDD 0.8VDD Max. 5.5 V 5.5 5.5 VDD VDD V V V V V V C Unit
(VSS = 0V reference) Remarks High-speed mode guaranteed operation range1 Low-speed mode guaranteed operation range1 Guaranteed data hold range during stop 2 Hysteresis input3 EXTAL4 2 Hysteresis input3 EXTAL4
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
1 High-speed mode is 1/2 frequency demultiplication clock selection; Iow-speed mode is 1/16 frequency demultiplication clock selection. 2 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF, PG, PI4 to PI6). 3 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2, INT3. 4 Specifies only during external clock input. - 10 -
CXP84220/84224
Electrical Characteristics DC Characteristics Item Symbol Pins PA to PD, PE4, PE5, PF, PG, PI PC IIHE IILE Input current IILR IIL EXTAL RST1 Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V VIL = 0.4V 0.5 -0.5 -1.5 (Ta = -20 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 -400 -2.0 -10 Typ. Max. Unit V V V V V A A A mA A
High level VOH output voltage Low level output voltage
VOL
PA to PD2, PF, PG, PI2 VDD = 4.5V, VIL = 4.0V PE0 to PE3, RST1 VDD = 5.5V VI = 0, 5.5V High-speed mode operation (1/2 frequency demultiplier clock)
I/O leakage current
IIZ
10
A
IDD1
VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Sleep mode
18
40
mA
Supply current3
IDDS1
VDD
VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Stop mode
1.1
8
mA
IDDS3 Pins other than PB7, PE4, PE5, AVREF, AVss, VDD, VSS
VDD = 5.5V, termination of 10MHz crystal oscillation
10
A
Input capacity
CIN
Clock 1MHz 0V for all pins excluding measured pins
10
20
pF
1 RST specifies the input current when pull-up resistance has been selected; Ieakage current wnen no resistance has been selected. 2 Pins PA to PD, and PF, PG, Pl specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. (Excludes output PB7) 3 When all pins are open.
- 11 -
CXP84220/84224
AC Characteristics (1) Clook timing Item System clock frequency System clock input pulse width Symbol fC Pins
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms
XTAL EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1
tXL tXH System clock input rise time, tCR fall time tCF Event count input clock pulse tEH width tEL Event count input clock rise time, tER fall time tEF
1
tsys + 501
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation
External clock
EXTAL C1
XTAL C2
EXTAL
XTAL
74HC04
Fig. 2. Clock applied condition
EC0 EC1
0.8VDD 0.2VDD
tEH
tEF
tEL
tER
Fig. 3. Event count clock timing - 12 -
CXP84220/84224
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0
SCK0 High, Low level width SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time
SCK0
tsys + 100
8000/fc - 50 100 200
SI0
SI0
tsys + 200
100
SO0
tsys + 200
100
ns ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
- 13 -
CXP84220/84224
tWHCS
CS0 0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
Fig. 4. Serial transfer CH0 timing
- 14 -
CXP84220/84224
Serial transfer (CH1) Item SCK1 cycle time Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode SCK1 Input mode Output mode SI1 SCK1 input mode SCK1 output mode SI1 SCK1 input mode SCK1 output mode SO1 SCK1 input mode SCK1 output mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
SCK1 High, Low level width SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY tKL tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
Fig. 5. Serial transfer CH1 timing
- 15 -
CXP84220/84224
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage VZT1 VFT2 Ta = 25C VDD = 5.0V VSS = AVSS = 0V -10 4930 160/fADC3 12/fADC3 AVREF AN0 to AN7 Operation mode AVREF IREFS Sleep mode Stop mode VDD - 0.5 0 0.6 VDD AVREF 1.0 10 70 5050 Symbol Pin Condition Min. Typ. Max. 8 3 150 5120 Unit Bits LSB mV mV s s V V mA A
tCONV tSAMP
VREF
Analog input voltage VIAN IREF AVREF current
FFH FEH
Linearity error
01H 00H
1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the below values due to ADC operation clock selection. During PS2 selection, fADC = fc/2 During PS1 selection, fADC = fc
VFT
Digital conversion value
VZT Analog input
Fig. 6. Definition of A/D converter terms
- 16 -
CXP84220/84224
(4) Interruption, reset input (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin INT0 INT1 INT2 INT3 NMI RST
tIH
Condition
Min.
Max.
Unit
External interruption High, Low level width
tIH tIL tRSL
1
s
Reset input Low level width
8/fc
tIL
s
0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge) 0.2VDD tIL tIH
Fig. 7. Interruption input timing
tRSL
RST 0.2VDD
Fig. 8. RST input timing (5) Power-on reset Power-on reset Item Power supply rising time Symbol
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Pin VDD Condition Power-on reset Repetitive power-on reset Min. 0.05 1 Max. 50 Unit ms ms
tR Power supply cut-off time tOFF
Specifies only when power-on reset function is selected.
4.5V 0.2V 0.2V
VDD
tR The power supply should be rise smoothly.
tOFF
Fig. 9. Power-on reset - 17 -
CXP84220/84224
Appendix
(i) Main clock
(ii) Main clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
C1
C2 C1 C2
Fig. 10. SPC700 Series recommended oscillation circuit
Manufacturer
Model CSA4.19MG CSA8.00MTZ
fc (MHz) 4.19 8.00 10.00
C1 (pF)
C2 (pF)
Rd ()
Circuit example
(i) 30 30 0 (ii)
MURATA MFG CO., LTD.
CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.0MTW
4.19 8.00 10.00 4.19
RIVER ELETEC CORPORATIO N
HC-49/U03
8.00 10.00 4.19
12
12
0 (i)
KINSEKI LTD.
HC-49/U (-S)
8.00 10.00
27 20
27 20
0
Those marked with an asterisk () signify types with built-in ground capacitance (C1, C2).
Mask option table Item Reset pin pull-up resistance Power-on reset circuit Content Non-existent Non-existent Existent Existent
- 18 -
CXP84220/84224
Package Outline
Unit: mm
64PIN SDIP (PLASTIC)
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15
1 1.778
32
0.5 0.1 0.9 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g
- 19 -
3.0 MIN
0.5 MIN + 0.4 4.75 - 0.1

▲Up To Search▲

Price & Availability of CXP84220

	To Download CXP84220 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .