 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CXP82700 CMOS 8-bit Single Chip Microcomputer Description The CXP82700 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP82712/82716. Piggyback/ evaluator type 64 pin PSDIP (Ceramic) Features * A wide instruction set (213 instructions) which cover various types of data. -- 16-bit operation/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation 122s at 32kHz operation * Applicable EPROM LCC type 27C128, LCC type 27C256 (Maximum 16Kbytes are available) * Incorporated RAM capacity 448 bytes (LCD display data area included) * Peripheral functions -- A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32s/10MHz) -- Serial interface Incorporated 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 circuit 2channels -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter -- Fluorescent display panel controller/driver Maximum 144 segments display possible 1 to 16-digit dynamic display 24 high voltage drive output port Dimmer function High voltage drive output (40V) On-chip pull-down resistor (Mask option) Hardware key scan function (Maximum 8 x 8 key matrix compatible.) -- Remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO -- PWM output 8bit, 1channel * Interruption 13 factors, 13 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 64-pin ceramic PSDIP Note) Mask option depends on the type of the CXP82700. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E94X11-PP CXP82700 Pin Assigument in Piggyback Mode PH0/TX PH1/TEX NC PE6/ADJ/TO PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTAL XTAL Vss 1 2 3 4 5 6 7 8 A15 9 10 11 12 13 14 15 16 17 A1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A0 D0 D1 D2 GND 9 10 11 12 13 14 20 19 18 17 16 15 CE 47 D7 D6 D5 D4 D3 46 45 44 43 42 41 40 39 38 37 36 35 34 33 T9/S27 T10/S26 T11/S25 T12/S24 T13/S23 T14/S22 T15/S21 S20 S19 S18 S17 S16 PF7/S15 PF6/S14 PF5/S13 A12 A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 VDD 56 A14 A13 A8 A9 A11 OE A10 55 54 53 52 51 50 49 48 T0 T1 T2 T3 T4 T5 T6 T7 T8/S28 64 63 62 61 60 59 58 57 VDD PE5/PWM PE4/RMC PE3/INT3/NMI PE2/INT2 PE1/INT1 PE0/EC/INT0 VFDP Note) 1. NC (Pin 3) is always connected to VDD. 2. PH0/TX (Pin 1) is input port during port selection; oscillation output during oscillation selection. -2- CXP82700 Pin Assigument in Evaluator Mode PH0/TX PH1/TEX NC PE6/ADJ/TO PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTAL XTAL Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A4/D4 16 17 18 19 20 21 22 23 24 GND 25 26 27 28 29 30 31 32 14 A3/D3 A2/D2 A1/D1 A0/D0 RD WR SYNC 6 7 8 9 10 11 12 13 23 22 21 20 19 18 17 16 15 A11 49 HALT A10 E/P I/T MON RST C1 C2 40 39 38 37 36 35 34 33 S20 S19 S18 S17 S16 PF7/S15 PF6/S14 PF5/S13 48 47 46 45 44 43 42 41 T7 T8/S28 T9/S27 T10/S26 T11/S25 T12/S24 T13/S23 T14/S22 T15/S21 A15 A12 A7/D7 A6/D6 A5/D5 1 2 3 4 5 28 27 26 25 24 VDD A14 A13 A8 A9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 VDD PE5/PWM PE4/RMC PE3/INT3/NMI PE2/INT2 PE1/INT1 PE0/EC/INT0 VFDP T0 T1 T2 T3 T4 T5 T6 Note) 1. NC (Pin 3) is always connected to VDD. 2. PH0/TX (Pin 1) is input port during port selection; oscillation output during oscillation selection. -3- CXP82700 EPROM Read Timing (Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Item Address data Input delay time Address data Hold time Symbol Pin A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 120 Unit ns ns tACC tIH 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Products List Products Option item Package ROM capacity Pull-up resistor for reset pin Pull-down resistor for high voltage drive pin Mask product CXP82712 CXP82716 80-pin plastic SDIP 12Kbytes 16Kbytes Piggyback/evaluator product CXP82700-U01S 64-pin ceramic PSDIP EPROM 16Kbytes Existent Only port for display Existent/Non-existent Existent/Non-existent -4- CXP82700 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 index Pin 1 marking DIP type EPROM CPU probe Package Outline Unit: mm 64PIN PSDIP (CERAMIC) 750mil 58.9 0.55 64 33 18.75 0.25 + 0.05 0.25 - 0.02 1.27 0.25 3.43 0.38 9.8 MAX CERAMIC GOLD PLATING 42 ALLOY 16.0g 1 2.54 0.25 32 0.46 0.08 0.9 1.778 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PSDIP-64C-01 ADIP064-C-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT -5- 19.05 0.25 15.24 |
Price & Availability of CXP82700
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |