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OZ968 SMBus Smart Inverter Controller FEATURES * * * * * * * Single-stage power conversion Constant frequency design eliminates interference with LCDs Built-in open-lamp protection and shortcircuit protection Reliable 2-winding transformer design eliminates arcing failures and the need for foldback wiring 32-level dimming and 256-level contrast control via SMBus High efficiency, 90% typical Supports both floating secondary and grounded secondary designs GENERAL DESCRIPTION The OZ968 is a unique single-stage, highefficiency, CCFL backlight controller. It drives a zero-voltage-switching circuit and provides a near sinusoidal output voltage and current waveforms for a CCFL backlight. Typical operating frequency ranges from 30KHz to 100KHz. These advances drive the OZ968 beyond comparable conventional inverter designs with two power conversion stages (one operates at a variable frequency, the other at a constant frequency). Operating in a PWM push-pull drive, the transformer in an OZ968 backlight inverter requires only one primary winding and one secondary winding. The secondary winding requires no foldback treatment. The OZ968 supports a bi-directional, two-wire bus, data transmission protocol to control dimming (32 levels) and contrast (256 levels). Supply current is 1mA in active mode, 150A in standby mode. The OZ968 is available in a 16-pin SOP package. It is specified over the commercial temperature range 0oC to +70oC. ORDERING INFORMATION OZ968G - 16-pin plastic SOP TYPICAL APPLICATION CIRCUIT 20V SMBCLCK SMBDATA ENABLE 5V CONTRAST OZ968 C5 1:40 C6 0.1u 22p/3KV Q4 3904 CCFL Q2 Si4559EY/P D1 C1 47u/ 25v 1 C2 FB VDD 16 R3 3.3k 2 0.1u CMP SCP 15 C3 0.47u 3 SST VSEQ 14 4 ADJ SMBD 13 R6 2.2k R4 200k Q3 3906 C7 1N4148 D2 1N4148 5 CNT SMBC 12 4.7u 6 RT OVP 11 R8 Q1 Si4559EY/ N 7 R2 120k C4 220p CT PDR 10 10k Q5 3904 R5 10k R7 0.1ohm R10 100k R9 1k 8 GND NDR 9 Figure 1. Typical Application Circuit 06/15/00 Copyright 1999 by O2Micro OZ968-SF-1.5 All Rights Reserved Page 1 U.S. Patent #5,619,402 OZ968 FUNCTIONAL BLOCK DIAGRAM IBIAS clki RT CT ramp REF OSC clk set Reset Comparator reset + FB 40K Break Before Make F/F Qp PDR EA Qn 160K NDR - ADJ CMP + + OVP OVP SST CNT lcd_susp csusp Brightness DAC Contrast DAC Slow Start vd iss poff See P.8, Section 9 pofbr Protections pofcnt + SCP SCP 0.5V bsusp - SMBC SMBD VSEQ 5bit data 8bit data xolp_ok xscp_ok SMB INTERFACE CLAMP OVP OVP Figure 2. Functional Block Diagram OZ968-SF-1.5 Page 2 OZ968 PIN CONFIGURATION Pin No. 1 2 3 Name FB CMP SST Description Current sense feedback. Compensation for the current sense feedback. Soft start in two steps. Two-interval current sources of 50A and 0.6A provide 1:26.6 ratio between the two time intervals of soft start. Connect a capacitor between this pin and the ground to adjust the soft-start timing. The output of the brightness D/A converter. The brightness has 32 adjustable levels. The default range is between 0.9V to 2.5V. The output of the contrast D/A converter. The contrast has 256 levels from 0.8V to 2.8 V (8mV per step). This output has a current capability of up to 2mA. Timing resistor. Timing capacitor. CT and RT set the clock frequency. Fs = 1.60 / (RT * CT). Ground. Gate drive output for the N-MOSFET. Gate drive output for the P-MOSFET. Over-voltage protection sense input. SMBus Clock Input/Output SMBus Data Input/Output. Vee power sequence input. Short-circuit protection sense input. Supply voltage input. 4 5 ADJ CNT 6 7 8 9 10 11 12 13 14 15 16 RT CT GND NDR PDR OVP SMBC SMBD VSEQ SCP VDD ABSOLUTE MAXIMUM RATINGS VDD GND Storage temp. Operating temp. Operating junction temp. 7.0 V +/- 0.3 V -55 to 150 oC 0 to 70 oC 150 oC Logic inputs -0.3 V to VDD+0.3 V RECOMMENDED OPERATING RANGE VDD Fosc Rt 4.75 V to 5.25 V 30 KHz to 100 KHz 50 K to 150 K OZ968-SF-1.5 Page 3 OZ968 FUNCTIONAL SPECIFICATIONS Parameter Oscillator Initial accuracy Temp. stability Line regulation Error Amplifier Bias current Input offset voltage Open loop voltage gain Unity gain bandwidth Dimming D/A Output (ADJ - floating) Maximum level Minimum level Power-on reset default Settling time D/A output levels Contrast D/A Output Maximum level Minimum level Power-on reset default Settling time Maximum output current Load regulation D/A output levels Under-voltage Lockout Power-on Voltage Hysteresis Break-before-Make Delay (between NDR and PDR) Supply Supply current - Standby Mode Supply current - Active Mode Output (NDR and PDR) Output high voltage Output low voltage Output resistance VDD = 5.0V VDD = 5.0V VDD = 5.0V 4.75 50 0.25 V V 100KHz, 800pF loading 150 1 2 100KHz, 800pF loading 400 ns 3.8 4.0 0.3 4.2 V V 2.70 0.75 0.75 2.80 0.80 0.80 10 2.0 50 256 2.95 0.90 0.90 2.2 100 V V V 2.40 0.8 2.40 2.50 0.9 2.5 10 32 2.65 1.0 2.65 V V V 60 2.5 2.0 80 2.0 5 5.0 Ct = 270pF, Rt = 100k TA = 0oC to 70oC 4.5 V < VDD <5.5V 54 59 200 2 64 500 3 KHz ppm/ oC % Test Conditions VDD = 5V, Tj =25, Test Circuit Min Limits Typ Max Unit A mV dB MHz s s mA mV/mA A mA OZ968-SF-1.5 Page 4 OZ968 TWO-WIRE BUS REGISTER DESCRIPTION The following register map describes the SMBus interface between SMBus Host and the OZ968 Register Map For Write commands. Function Contrast Brightness Slave Address (7-bit) 0101 000 0101 000 Register Index (Hex) A9 AA Data byte byte Contrast (A9) SMBus Protocol: Read or Write Byte Input/Output: Byte -- bit flags mapped as follows: Bit # 7:0 Name D7-D0 R/W r/w Default 0000 0000 Description Bits D7-D0 contain the contrast level setting. When D7-D0 = FF, the CNT pin of the OZ968 outputs 2.8V. When D7D0 = 00, the CNT pin outputs 0.8V. Brightness (AA) SMBus Protocol: Read or Write Byte Input/Output: Byte -- bit flags mapped as follows: Bit # 7:0 Name D7-D0 R/W r/w Default 0000 0000 Description Bits D7-D0 contain the brightness level setting. When D7D0 = FF, the OZ968 inverter outputs miniimum brightness. When D7-D0 = 00, the OZ968 inverter outputs maximum brightness. OZ968-SF-1.5 Page 5 OZ968 PACKAGE INFORMATION DIM INCHES MIN MAX 0.0532 0.0688 0.0040 0.0098 0.013 0.020 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 0.050 BCS. 0.2284 0.2440 0.016 0.050 0 8 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BCS. 5.80 6.20 0.40 1.27 0 8 SOP-16 PACKAGE EH A A1 B C D E e H L D A B e A1 D L C OZ968-SF-1.5 Page 6 |
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