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TC7109 TC7109A
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
FEATURES
s s s s s s s s s s Zero-Integrator Cycle for Fast Recovery From Input Overloads Eliminates Cross -Talk in Multiplexed Systems 12-Bit Plus Sign Integrating A/D Converter With Overrange Indication Sign Magnitude Coding Format True Differential Signal Input and Differential Reference Input Low Noise ............................................ 15 VP-P Typ Input Current .............................................. 1 pA Typ No Zero Adjustment Needed TTL-Compatible, Byte-Organized Tri-State Outputs UART Handshake Mode for Simple Serial Data Transmission
GENERAL DESCRIPTION
The TC7109A is a 12-bit plus sign, CMOS low-power analog-to-digital converter (ADC). Only eight passive components and a crystal are required to form a complete dual-slope integrating ADC. The improved VOH source current TC7109A has features that make it an attractive per-channel alternative to analog multiplexing for many data acquisition applications. These features include typical input bias current of 1pA drift of less than 1V/C, input noise typically 15VP-P, and auto-zero. True differential input and reference allow measurement of bridge-type transducers such as load cells, strain gauges, and temperature transducers. The TC7109A provides a versatile digital interface. In the direct mode, chip select and HIGH/LOW byte enables control parallel bus interface. In the handshake mode, the TC7109A will operate with industry-standard UARTs in controlling serial data transmission -- ideal for remote data logging. Control and monitoring of conversion timing is provided by the RUN/HOLD input and STATUS output. For applications requiring more resolution, see the TC500, 15-bit plus sign ADC data sheet. The TC7109A has improved overrange recovery performance and higher output drive capability than the original TC7109. All new (or existing) designs should specify the TC7109A wherever possible.
2 3 4 5 6
18 19 20 LBEN HBEN CE/LOAD
ORDERING INFORMATION PART CODE
A or blank* Package Code
CKW CLW CPL IJL
TC7109X
Temperature Range
0C to +70C 0C to +70C 0C to +70C -25C to +85C
Package
44-Pin PQFP 44-Pin PLCC 40-Pin Plastic DIP 40-Pin CerDIP
* The "A" version has a higher IOUT on the digital lines. FUNCTIONAL BLOCK DIAGRAM
REF IN + 36 AZ ZI INPUT 35 HI INT DE (-) AZ DE (+) AZ DE () ZI DE (-) DE (+) ZI AZ REF IN - 39 AZ ZI R CAZ C INT REF INT CAP - INT BUFF AZ 32 30 31 38 BUFFER - + INTEGRATOR - + 16 THREE-STATE OUTPUTS COMPARATOR COMP OUT 14 LATCHES 12-BIT COUNTER LATCH CLOCK
POL
B12 B11
OR
B10 B9
B8 B7
B6 B5
B4 B3
REF CAP + 37
17
3
4
5
6
7
8
9 10 11 12 13 14 15 16
B2 B1
C REF
TEST
HIGH-ORDER BYTE OUTPUTS
LOW-ORDER BYTE OUTPUTS
COMMON
33
7
HANDSHAKE LOGIC 27 SEND 1 GND
TC7109A
10 A - + 6.2V TO ANALOG SECTION
INPUT 34 LO
INT
COMP OUT AZ INT DE () ZI
CONVERSION CONTROL LOGIC
OSCILLATOR AND CLOCK CIRCUITRY
29
28
40 V+
2 STATUS
26
22
23
24
25
21
REF V - OUT
RUN/ OSC OSC OSC BUF MODE HOLD IN OUT SEL OSC OUT
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TC7109/A-7 11/6/96
TELCOM SEMICONDUCTOR, INC.
3-91
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (GND to ..................... +6.2V Negative Supply voltage (GND to V-) ....................... -9V Analog Input Voltage (Low to High) (Note 1) ....... V+ to V- Reference Input Voltage (Low to High (Note 1) .. V + to V- Digital Input Voltage (Pins 2-27) (Note 2) ..... GND -0.3V Power Dissipation, TA < 70C, (Note 3) CerDIP ............................................................. 2.29W Plastic DIP ....................................................... 1.23W PLCC ............................................................... 1.23W PQFP ............................................................... 1.00W Operating Temperature Range Plastic Package (C) ............................... 0C to +70C Ceramic Package (I) ....................... - 25C to +85C (M) ................... - 55C to +125C Storage Temperature Range ............... - 65C to +150C Lead Temperature (Soldering, 10 sec) ................. +300C V+)
*Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. NOTES: 1. Input voltages may exceed supply voltages if input current is limited to 100 A. 2. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be activated first. 3. This limit refers to that of the package and will not occur during normal operation.
ELECTRICAL CHARACTERISTICS: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25C,
unless otherwise indicated. Symbol
Analog Overload Recovery Time (TC7109A) Zero Input Reading Ratio Metric Reading NL Nonlinearity (Max Deviation From Best Straight Line Fit) Roll-Over Error (Difference in Reading for Equal Positive and Negative Inputs Near (Full Scale) Input Common-Mode Rejection Ratio Common-Mode Voltage Range Noise (P-P Value Not Exceeded 95% of Time) Leakage Current at Input -- VIN = 0V Full Scale = 409.6 mV VIN = VREF VREF = 204.8 mV Full Scale = 409.6 mV to 2.048V Over Full Operating Temperature Range Full Scale = 409.6 mV to 2.048V Over Full Operating Temperature Range VCM 1V, VIN = 0V Full Scale = 409.6 mV Input High, Input Low, and Common Pins VIN = 0V Full Scale = 409.6 mV VIN, All Packages: +25C C Device: 0C TA +70C I Device: -25C TA +85C M Device: -55C TA +125C VIN = 0V VIN = 408.9 mV = >77708 Reading, Ext Ref = 0 ppm/C VIN = 0V, Crystal Oscillator 3.58 MHz Test Circuit Pins 2-21, 25, 26, 27, 29 Open - 00008 37778 -1 0 00008 37778 40008 0.2 1 +00008 40008 +1 Measurement Cycle Octal Reading Octal Reading Count
Parameter
Test Conditions
Min
Typ
Max
Unit
-1
0.02
+1
Count
CMRR VCMR eN IIN
-- V-+1.5 -- --
50 -- 15 1 20 100 2 0.2 1 700 700
-- V+-1 -- 10 100 250 5 1 5 1500 1500
V/V V V pA pA pA nA V/C V/C A A
TCZS TCFS I+ IS
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Zero Reading Drift Scale-Factor Temperature Coefficient Supply Current (V+ to GND) Supply Current (V+ to V-)
-- -- -- --
TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
ELECTRICAL CHARACTERISTICS (Cont.)
Symbol
VREF TCREF Digital VOH
1
Parameter
Ref Out Voltage Ref Out Temperature Coefficient Output High Voltage
Test Conditions
Referenced to V+, 25 k Between V+ and Ref Out 25 k Between V+ and Ref Out 0C TA +70C TC7109: IOUT = 100 A TC7109A: IOUT = 700 A Pins 3-16, 18, 19, 20 IOUT = 1.6 mA Pins 3-16 High Impedance Pins 18, 19, 20 VOUT = V+-3V Mode Input at GND HBEN, Pin 19; LBEN, Pin 18 Pins 18-21, 26, 27 Referenced to GND Pins 18-21, 26, 27 Referenced to GND Pins 26, 27; VOUT = V+-3V Pins 17, 24; VOUT = V+-3V Pin 21; VOUT = GND = +3V VOUT = 2.5V VOUT = 2.5V VOUT = 2.5V VOUT = 2.5V
Min
- 2.4 --
Typ
- 2.8 80
Max
- 3.2 --
Unit
V ppm/C
2 3 4 5 6 7
3.5
4.3
--
V
VOL
VIH VIL
Output Low Voltage Output Leakage Current Control I/O Pull-Up Current Control I/O Loading Input High Voltage Input Low Voltage Input Pull-Up Current Input Pull-Down Current Oscillator Output Current, High Oscillator Output Current, Low Buffered Oscillator Output Current, High Buffered Oscillator Output Current, Low Mode Input Pulse Width
-- -- -- -- 2.5 -- -- -- -- -- -- -- 60
0.2 0.01 5 -- -- -- 5 25 1 1 1.5 2 5 --
0.4 1 -- 50 -- 1 -- -- -- -- -- -- --
V A A pF V V A A A mA mA mA mA nsec
tW
HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package and store only in conductive foam, anti-static tubes, or other conducting material. Use proper anti-static handling procedures. Do not connect in circuits under "power-on" conditions, as high transients may cause permanent damage.
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TELCOM SEMICONDUCTOR, INC.
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
PIN CONFIGURATIONS
REF CAP + REF IN + REF CAP - STATUS STATUS REF IN - REF CAP + REF IN + REF CAP - REF IN -
GND
POL
B 12
B 12
GND
POL
OR
OR
NC
NC
V
44 43 42 41 40 39 38 37 36 35 34
6 33 IN HI 32 IN LO 31 COMMON 30 INT 29 AZ
5
4
3
2
1
B 11 1 B 10 2 B9 3 B8 4 B7 5 NC 6 B6 7 B5 8 B4 9 B 3 10 B 2 11
12 13 14 15 16 17 18 19 20 21 22
B1 CE/LOAD MODE OSC OUT OSC SEL BUFF OSC OUT NC OSC IN LBEN TEST HBEN
B 11 7 B 10 8 B9 9 B 8 10 B 7 11 NC 12 B 6 13 B 5 14 B 4 15 B 3 16 B 2 17
18 19 20 21 22 23 24 25 26 27 28
B1 CE/LOAD MODE OSC OUT OSC SEL BUFF OSC OUT NC OSC IN LBEN TEST HBEN
V+
+
44 43 42 41 40
39 IN HI 38 IN LO 37 COMMON 36 INT 35 AZ
TC7109ACKW TC7109CKW
(PQFP)
28 NC 27 BUFF 26 REF OUT 25 V - 24 SEND 23 RUN/HOLD
TC7109ACLW TC7109CLW
(PLCC)
34 NC 33 BUFF 32 REF OUT 31 V - 30 SEND 29 RUN/HOLD
GND STATUS POL OR B 12 B 11 B 10 B9 B8
1 2 3 4 5 6 7 8 9
40 V + 39 REF IN - 38 REF CAP - 37 REF CAP + 36 REF IN + 35 IN HI 34 IN LO 33 COMMON 32 INT 31 AZ
B 7 10 B 6 11 B 5 12 B 4 13 B 3 14 B 2 15 B 1 16 TEST 17 LBEN 18 HBEN 19 CE/LOAD 20
TC7109A TC7109
(CPL, IJL, MJL) (PDIP) (CerDIP)
30 BUFF 29 REF OUT 28 V - 27 SEND 26 RUN/HOLD 25 BUFF OSC OUT 24 OSC SEL 23 OSC OUT 22 OSC IN 21 MODE
NC = NO INTERNAL CONNECTION
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TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
TC7109/A PIN DESCRIPTION
40-Pin PDIP Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1
2
Symbol
GND STATUS POL OR B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 TEST LBEN
Description
Digital ground, 0V, ground return for all digital logic. Output HIGH during integrate and deintegrate until data is latched. Output LOW when analog section is in auto-zero or zero-integrator configuration. Polarity -- High for positive input. Overrange -- High if overranged. Bit 12 (Most Significant Bit) Bit 11 Bit 10 Bit 9 Bit 8 All Three-State Data Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (Least Significant Bit) Input High -- Normal operation. Input LOW -- Forces all bit outputs HIGH. Note: This input is used for test purposes only. Low-Byte Enable -- With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin LOW activates low-order byte outputs, B1-B8. With MODE (Pin 21) HIGH, this pin serves as low-byte flag output used in handshake mode. See Figures 7, 8, and 9. High-Byte Enable -- With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin LOW activates high-order byte outputs, B9-B12, POL, OR. With MODE (Pin 21) HIGH, this pin serves as high-byte flag output used in handshake mode. See Figures 7, 8, and 9. Chip Enable/Load -- With MODE (Pin 21) LOW, CE/LOAD serves as a master output enable. When HIGH, B1-B12, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load strobe is used in handshake mode. See Figure 7, 8, and 9. Input LOW -- Direct output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) act as inputs directly controlling byte outputs. Input Pulsed HIGH -- Causes immediate entry into handshake mode and output of data as in Figure 9. Input HIGH -- Enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs, handshake mode will be entered and data output as in Figures 7 and 8 at conversions completion. Oscillator Input Oscillator Output Oscillator Select -- Input HIGH configures OSC IN, OSC OUT, BUF OSC OUT as RC oscillator -- clock will be same phase and duty cycle as BUF OSC OUT. Input LOW configures OSC IN, OSC OUT for crystal oscillator -- clock frequency will be 1/58 of frequency at BUF OSC OUT. Buffered Oscillator Output Input HIGH -- Conversions continuously performed every 8192 clock pulses. Input LOW -- Conversion in progress completed; converter will stop in auto-zero seven counts before integrate.
3-95
3 4 5 6 7
19
HBEN
20
CE/LOAD
21
MODE
22 23 24
OSC IN OSC OUT OSC SEL
25 26
BUF OSC OUT RUN/HOLD
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TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
TC7109/A PIN DESCRIPTION (Cont.)
40-Pin PDIP Pin Number
27
Symbol
SEND
Description
Input -- Used in handshake mode to indicate ability of an external device to accept data. Connect to V+ if not used. Analog Negative Supply -- Nominally -5V with respect to GND (Pin 1). Reference Voltage Output -- Nominally 2.8V down from V+ (Pin 40). Buffer Amplifier Output Auto-Zero Node -- Inside foil of CAZ. Integrator Output -- Outside foil of CINT. Analog Common -- System is auto-zeroed to COMMON. Differential Input Low Side Differential Input High Side Differential Reference Input Positive Reference Capacitor Positive Reference Capacitor Negative Differential Reference Input Negative Positive Supply Voltage -- Nominally +5V with respect to GND (Pin 1).
28 29 30 31 32 33 34 35 36 37 38 39 40
V- REF OUT BUFFER AUTO-ZERO INTEGRATOR COMMON INPUT LOW INPUT HIGH REF IN + REF CAP + REF CAP - REF IN - V+
NOTE: All digital levels are positive true.
15 Q11 CD4040B RESET CLK 11 10 +5V 1 2 GND +5V 3 4 V OSC CONTROL GND RRD TRC OSC IN EPE CLS1 CLS2 5-12 RBR1-8 SBS PI CRL 40 17 39 38 37 36 35 34 GND +5V 8 6 3-8 19 HBEN +5V GND 1 25 2 GND BUFF OSC OUT STATUS
40 V+ 39 REF IN - 38 REF CAP - REF CAP + 37 REF IN + 36 IN HI IN LO 35 34 33 32 31 30
+5V - 1F 1M 0.01F C INT 0.15F EXTERNAL REFERENCE + + INPUT - ANALOG GND
13 14 15 GND 16 20
6403 CMOS UART
PE FE OE SFD
TC7109A
B9-B12, POL, OR B1-B8 TEST LBEN MODE CE/LOAD SEND
COM INT AZ BUFF
*TBR1-8 TRE DRR
26-33 24 18 19 23 22 21 GND
8
9-16 17 18 21 20 27
CAZ 0.33F
RR1 SERIAL INPUT 25 SERIAL OUTPUT TRO
DR TBRL TBRE MR
29 RINT 20k 0.2VREF REF OUT 100k 1VREF 28 -5V V- 26 RUN/HOLD +5V OR OPEN 24 GND OSC SEL 23 OSC OUT 3.58MHz 22 CRYSTAL OSC IN
*NOTE: For lowest power consumption, TBR1-TBR8 inputs
should have 100k pull-up resistors to +5V.
Figure 1. TC7109A UART Interface (Send Any Word to UART to Transmit Latest Result)
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TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
1
2 XTALI +5V 1 4 5 6 TO RESET SS INT
3 XTAL2 2 21-24, 35-38 8 OTHER I/O 31-34 5 30 29 28 27 26 2 18 19 RUN/HOLD STATUS LBEN HBEN +5V GND 40 1 17 V+ GND TEST 39 REF IN - 38 REF CAP - REF CAP + REF IN + IN HI HI LO 37 36 35 34 33 32 31 30 CAZ 0.33F C INT 0.15F 1M 0.01F 1F - EXTERNAL REFERNCE + + - INPUT
2 3 4 5 6 7
P20-P27
8748/8049 CMOS MICROCOMPUTER
P14-P17
GND
7 8 9 11
TC7109A
COM INT AZ
EA WR PSEN ALE
ANALOG GND
P13 P12 P11 P10
BUFF
+5V 25 PROG +5V 26 V DD +5V 39 TL +5V 40 V CC
6 DB0-DB7 12-19 10 8 8
3-8 B9-B12, POL, OR 9-16 B1-B8 20 CE/LOAD
GND 20 GND
RD
RINT 29 REF OUT 20k 0.2 VREF - 28 -5V V 10 k 1 VREF 27 SEND 25 BUFF OSC OUT 24 GND OSC SEL 23 OSC OUT 3.58MHz 22 CRYSTAL OSC IN 21 MODE
Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP)
Analog Section
The functional diagram shows a block diagram of the analog section of the TC7109A. The circuit will perform conversions at a rate determined by the clock frequency (8192 clock periods per cycle), when the RUN/HOLD input is left open or connected to V+. Each measurement cycle is divided into four phases, as shown in Figure 3. They are: (1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference Deintegrate (DE), and (4) Zero Integrator (ZI). Auto-Zero Phase The buffer and the integrator inputs are disconnected from input high and input low and connected to analog common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the system to charge the auto-zero capacitor, CAZ, to compensate for offset voltage in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. The offset referred to the input is less than 10 V. TELCOM SEMICONDUCTOR, INC.
Signal-Integrate Phase The buffer and integrator inputs are removed from common and connected to input high and input low. The auto-zero loop is opened. The auto-zero capacitor is placed in series in the loop to provide an equal and opposite compensating offset voltage. The differential voltage between input high and input low is integrated for a fixed time of 2048 clock periods. At the end of this phase, the polarity of the integrated signal is determined. If the input signal has no return to the converter's power supply, input low can be tied to analog common to establish the correct commonmode voltage. Deintegrate Phase Input high is connected across the previously-charged reference capacitor and input low is internally connected to analog common. Circuitry within the chip ensures the capacitor will be connected with the correct polarity to cause the integrator output to return to the zero crossing (established by auto-zero) with a fixed slope. The time, represented by the number of clock periods counted for the output to return to zero, is proportional to the input signal.
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
Zero-Integrator Phase The ZI phase only occurs when an input overrange condition exists. The function of the ZI phase is to eliminate residual charge on the integrator capacitor after an overrange measurement. Unless removed, the residual charge will be transferred to the auto-zero capacitor and cause an error in the succeeding conversion. The ZI phase virtually eliminates hysteresis or "cross talk" in multiplexed systems. An overrange input on one channel will not cause an error on the next channel measured. This feature is especially useful in thermocouple measurements, where unused (or broken thermocouple) inputs are pulled to the positive supply rail. During ZI, the reference capacitor is charged to the reference voltage. The signal inputs are disconnected from the buffer and integrator. The comparator output is connected to the buffer input, causing the integrator output to be driven rapidly to 0V (Figure 3). The ZI phase only occurs following an overrange and lasts for a maximum of 1024 clock periods. Differential Input The TC7109A has been optimized for operation with analog common near digital ground. With +5V and -5V power supplies, a full 4V full-scale integrator swing maximizes the analog section's performance. A typical CMRR of 86 dB is achieved for input differential voltages anywhere within the typical common-mode range of 1V below the positive supply to 1.5V above the negative supply. However, for optimum performance, the IN HI and IN LO inputs should not come within 2V of either supply rail. Since the integrator also swings with the common-mode voltage, care must be exercised to ensure the integrator output does not saturate. A worst-case condition is near a full-scale negative differential input voltage with a large positive common-mode voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. In such cases, the integrator swing can be reduced to less than the recommended 4V full-scale value, with some loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. Roll-over voltage is the main source of common-mode error, caused by the reference capacitor losing or gaining charge due to stray capacity on its nodes. With a large common-mode voltage, the reference capacitor can gain charge (increase voltage) when called upon to deintegrate a positive signal and lose charge (decrease voltage) when called upon to deintegrate a negative input signal. This difference in
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reference for (+) or (-) input voltages will cause a roll-over error. This error can be held to less than 0.5 count worst case by using a large reference capacitor in comparison to the stray capacitance. To minimize roll-over error from these sources, keep the reference common-mode voltage near or at analog common.
Digital Section
The digital section is shown in the block diagram (Figure 4) and includes the clock oscillator and scaling circuit, a 12-bit binary counter with output latches and TTL compatible three-state output drivers, UART handshake logic, polarity, overrange, and control logic. Logic levels are referred to as LOW or HIGH. Inputs driven from TTL gates should have 3 k to 5 k pull-up resistors added for maximum noise immunity. For minimum power consumption, all inputs should swing from GND (LOW) to V+ (HIGH). STATUS Output During a conversion cycle, the STATUS output goes HIGH at the beginning of signal integrate and goes LOW one-half clock period after new data from the conversion has been stored in the output latches (see Figure 3). The signal may be used as a "data valid" flag to drive interrupts, or for monitoring the status of the converter. (Data will not change while status is LOW.) MODE Input The output mode of the converter is controlled by the MODE input. The converter is in its "direct" output mode, when the MODE input is LOW or left open. The output data is directly accessible under the control of the chip and byte enable inputs (this input is provided with a pull-down resistor to ensure a LOW Level when the pin is left open). When the MODE input is pulsed high, the converter enters the UART handshake mode and outputs the data in 2 bytes, then returns to "direct" mode. When the MODE input is kept HIGH, the converter will output data in the handshake mode at the end of every conversion cycle. With MODE = 0 (direct bus transfer), the send input should be tied to V+. (See "Handshake Mode.") RUN/HOLD Input With the RUN/HOLD input high, or open, the circuit operates normally as a dual-slope ADC, as shown in Figure 3. Conversion cycles operate continuously with the output latches updated after zero crossing in the deintegrate mode. An internal pull-up resistor is provided to ensure a HIGH level with an open input.
TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
INTEGRATOR SATURATES ZI AZ ZERO INTEGRATOR PHASE FORCES INTEGRATOR OUTPUT TO 0V
1
2 3 4 5
18 LBEN HBEN CE/LOAD 19 20
INTEGRATOR OUTPUT FOR OVERRANGE INPUT
INTEGRATOR OUTPUT FOR NORMAL INPUT INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT
NO ZERO CROSSING ZERO CROSSING OCCURS ZERO CROSSING DETECTED AZ PHASE I INT PHASE II DE PHASE III AZ
2048 FIXED COUNTS 2048 MIN COUNTS NUMBER OF COUNTS TO ZERO CROSSING PROPORTIONAL TO VIN
4096 COUNTS MAX AFTER ZERO CROSSING, ANALOG SECTION WILL BE IN AUTO-ZERO CONFIGURATION
Figure 3. Conversion Timing (RUN/HOLD Pin High)
TEST 17
HIGH-ORDER BYTE OUTPUTS BBB POL OR 12 11 10 3 4 5 6 7
B 9 8
B 8
LOW-ORDER BYTE OUTPUTS BBBBBB 765432
B 1
9 10 11 12 13 14 15 16
14 THREE-STATE OUTPUTS
14 LATCHES
6 7
1 GND
12-BIT COUNTER LATCH CLOCK COMP OUT AZ INT DE () ZI 2 STATUS
TO ANALOG SECTION
CONVERSION CONTROL LOGIC
OSCILLATOR AND CLOCK CIRCUITRY
HANDSHAKE LOGIC
26
22
23
24
25
21
27 SEND
RUN/ OSC OSC OSC BUFF MODE IN OUT SEL OSC HOLD OUT
Figure 4. Digital Section
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TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
AUTO-ZERO PHASE I MIN 1790 COUNTS MAX 2041 COUNTS
DETERMINATED AT ZERO CROSSING DETECTION INTEGRATOR OUTPUT INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT RUN/HOLD INPUT
STATIC IN HOLD STATE INT PHASE II 7 COUNTS
*
*NOTE:
RUN/HOLD input is ignored until end of auto-zero phase.
Figure 5.
TC7109A RUN/HOLD Operation
The RUN/HOLD input may be used to shorten conversion time. If RUN/HOLD goes LOW any time after zero crossing in the deintegrate mode, the circuit will jump to auto-zero and eliminate that portion of time normally spent in deintegrate. If RUN/HOLD stays or goes LOW, the conversion will complete with minimum time in deintegrate. It will stay in auto-zero for the minimum time and wait in auto-zero for a HIGH at the RUN/HOLD input. As shown in Figure 5, the STATUS output will go HIGH 7 clock periods after RUN/ HOLD is changed to HIGH, and the converter will begin the integrate phase of the next conversion. The RUN/HOLD input allows controlled conversion interface. The converter may be held at idle in auto-zero with RUN/HOLD LOW. The conversion is started when RUN/ HOLD goes HIGH, and the new data is valid when the STATUS output goes LOW (or is transferred to the UART; see "Handshake Mode"). RUN/HOLD may now go LOW, terminating deintegrate and ensuring a minimum auto-zero time before stopping to wait for the next conversion. Conversion time can be minimized by ensuring RUN/HOLD goes LOW during deintegrate, after zero crossing, and goes HIGH after the hold point is reached. The required activity on the RUN/HOLD input can be provided by connecting it to the buffered oscillator output. In this mode, the input value measured determines the conversion time. Direct Mode The data outputs (bits 1 through 8, low-order bytes; bits 9 through 12, polarity and overrange high-order bytes) are accessible under control of the byte and chip enable terminals as inputs with the MODE pin at a LOW level. These three inputs are all active LOW. Internal pull-up resistors are provided for an inactive HIGH level when left open. When chip enable is LOW, a byte-enable input LOW will allow the outputs of the byte to become active. A variety of parallel
data accessing techniques may be used, as shown in the "Interfacing" section. (See Figure 6 and Table 1.) The access of data should be synchronized with the conversion cycle by monitoring the STATUS output. This prevents accessing data while it is being updated and eliminates the acquisition of erroneous data.
t CEA
CE/LOAD AS INPUT t BEA HBEN AS INPUT LBEN AS INPUT t DAB HIGH-BYTE DATA LOW-BYTE DATA = HIGH IMPEDANCE
DATA VALID
t DAB
DATA VALID
t DAC
DATA VALID
t DHC
Figure 6.
TC7109A Direct Mode Output Timing
Table 1. TC7109A Direct Mode Timing Requirements Symbol
tBEA tDAB tDHB tCEA tDAC tDHC
Description
Byte Enable Width Data Access Time From Byte Enable Data Hold Time From Byte Enable Chip Enable Width Data Access Time From Chip Enable Data Hold Time From Chip Enable
Min Typ
200 500 150 150 300 500 200 200
Max
300 300
Units
nsec nsec nsec nsec nsec nsec
400 400
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TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
Handshake Mode An alternative means of interfacing the TC7109A to digital systems is provided when the handshake output mode of the TC7109A becomes active in controlling the flow of data instead of passively responding to chip and byte enable inputs. This mode allows a direct interface between the TC7109A and industry-standard UARTs with no external logic required. The TC7109A provides all the control and flag signals necessary to sequence the two bytes of data into the UART and initiate their transmission in serial form when triggered into the handshake mode. The cost of designing remote data acquisition stations is reduced using serial data transmission to minimize the number of lines to the central controlling processor. The MODE input controls the handshake mode. When the MODE input is held HIGH, the TC7109A enters the handshake mode after new data has been stored in the output latches at the end of every conversion performed (see Figures 7 and 8). Entry into the handshake mode may be triggered on demand by the MODE input. At any time during the conversion cycle, the LOW-to-HIGH transition of a short pulse at the MODE input will cause immediate entry into the handshake mode. If this pulse occurs while new data is being stored, the entry into handshake mode is delayed until the data is stable. The MODE input is ignored in the handshake mode, and until the converter completes the output cycle and clears the handshake mode, data updating will be inhibited (see Figure 9). When the MODE input is HIGH or when the converter enters the handshake mode, the chip and byte enable inputs become TTL-compatible outputs which provide the output cycle control signals (see Figures 7, 8 and 9). The SEND input is used by the converter as an indication of the ability of the receiving device (such as a UART) to accept data in the handshake mode. The sequence of the output cycle with SEND held HIGH is shown in Figure 7. The handshake mode (internal MODE HIGH) is entered after the data latch pulse (the CE/LOAD, LBEN and HBEN terminals are active as outputs since MODE remains HIGH). The HIGH level at the SEND input is sensed on the same HIGH-to-LOW internal clock edge. On the next LOWto-HIGH internal clock edge, the high-order byte (bits 9 through 12, POL, and OR) outputs are enabled and the CE/ LOAD and the HBEN outputs assume a LOW level. The CE/LOAD output remains LOW for one full internal clock period only; the data outputs remain active for 1-1/2 internal clock periods; and the high-byte enable remains LOW for 2 clock periods. The CE/LOAD output LOW level or LOW-to-HIGH edge may be used as a synchronizing signal to ensure valid data, and the byte enable as an output may be used as a byte identification flag. With SEND remaining HIGH the converter completes the output cycle using CE/LOAD and LBEN while the low-order byte outputs (bits 1 through 8) are activated. When both bytes are sent, the handshake mode is terminated. The typical UART interfacing timing is shown in Figure 8. The SEND input is used to delay portions of the sequence, or handshake, to ensure correct data transfer. This timing diagram shows an industry-standard HD6403 or CDP1854 CMOS UART to interface to serial data channels. The SEND input to the TC7109A is driven by the TBRE (Transmitter Buffer Register Empty) output of the UART, and the CE/LOAD input of the TC7109A drives the TBRL (Transmitter Buffer Register Load) input to the UART. The eight transmitter buffer register inputs accept the parallel data outputs. With the UART transmitter buffer register empty, the SEND input will be HIGH when the handshake mode is entered after new data is stored. The high-order byte outputs become active and the CE/LOAD and HBEN inputs will go LOW after SEND is sensed. When CE/LOAD goes HIGH at the end of one clock period, the high-order byte data is clocked into the UART transmitter buffer register. The UART TBRE output will go LOW, which halts the output cycle with the HBEN output LOW, and the high-order byte outputs active. When the UART has transferred the data to the transmitter register and cleared the transmitter buffer register, the TBRE returns HIGH. The high-order byte outputs are disabled on the next TC7109A internal clock HIGH-to-LOW edge, and one-half internal clock later, the HBEN output returns HIGH. The CE/LOAD and LBEN outputs go LOW at the same time as the low-order byte outputs become active. When the CE/LOAD returns HIGH at the end of one clock period, the low-order data is clocked into the UART transmitter buffer register, and TBRE again goes LOW. The next TC7109A internal clock HIGH-to-LOW edge will sense when TBRE returns to a HIGH, disabling the data inputs. One-half internal clock later, the handshake mode is cleared, and the CE/LOAD, HBEN and LBEN terminals return HIGH and stay active, if MODE still remains HIGH. Handshake output sequences may be performed on demand by triggering the converter into handshake mode with a LOW-to-HIGH edge on the MODE input. A handshake output sequence triggered is shown in Figure 9. The SEND input is LOW when the converter enters handshake mode. The whole output sequence is controlled by the SEND input, and the sequence for the first (high order) byte is similar to the sequence for the second byte. Figure 9 also shows that the output sequence can take longer than a conversion cycle. New data will not be latched when the handshake mode is still in progress and is therefore lost.
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
ZERO CROSSING OCCURS ZERO CROSSING DETECTED
INTEGRATOR OUTPUT INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT MODE INPUT UART NORM
INTERNAL MODE SEND INPUT CE/LOAD HBEN HIGH-BYTE DATA LBEN
SEND SENSED
SEND SENSED
TERMINATES UART MODE MODE LOW, NOT IN HANDSHAKE MODE DISABLES OUTPUTS CE/LOAD, HBEN, LBEN
DATA VALID MODE HIGH ACTIVATES CE/LOAD, HBEN, LBEN
LOW-BYTE DATA = DON'T CARE
Figure 7.
DATA VALID = THREE-STATE HIGH IMPEDANCE = THREE-STATE WITH PULL-UP
TC7109A Handshake With SEND INPUT Held Positive
ZERO CROSSING OCCURS ZERO CROSSING DETECTED INTEGRATOR OUTPUT INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT MODE INPUT UART NORM SEND SENSED TERMINATES UART MODE
INTERNAL MODE SEND INPUT (UART TBRE) CE/LOAD OUTPUT (UART TBRL) HBEN HIGH-BYTE DATA LBEN LOW-BYTE DATA
SEND SENSED
SEND SENSED
DATA VALID
DATA VALID = DON'T CARE
Figure 8.
= THREE-STATE HIGH IMPEDANCE
TC7109A Handshake -- Typical UART Interface Timing
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TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
1
POSITIVE TRANSITION CAUSES ENTRY INTO UART MODE INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT MODE INPUT INTERNAL MODE SEND INPUT CE/LOAD AS OUTPUT HBEN HIGH-BYTE DATA LBEN LOW-BYTE DATA
ZERO CROSSING OCCURS ZERO CROSSING DETECTED STATUS OUTPUT UNCHANGED IN UART MODE LATCH PULSE INHIBITED IN UART MODE
2 3 4
DE PHASE III
UART NORM
SEND SENSED
SEND SENSED
SEND SENSED
TERMINATES UART MODE
DATA VALID
DATA VALID
= DON'T CARE
= THREE-STATE HIGH IMPEDANCE
= THREE-STATE WITH PULL-UP
5 6 7
Figure 9. TC7109A Handshake Triggered by MODE Input
Oscillator
The oscillator may be overdriven, or may be operated as an RC or crystal oscillator. The OSCILLATOR SELECT input optimizes the internal configuration of the oscillator for RC or crystal operation. The OSCILLATOR SELECT input is provided with a pull-up resistor. When the OSCILLATOR SELECT input is HIGH or left open, the oscillator is configured for RC operation. The internal clock will be the same frequency and phase as the signal at the BUFFERED OSCILLATOR OUTPUT. Connect the resistor and capacitor as in Figure 10. The circuit will oscillate at a frequency given by f = 0.45/RC. A 100 k resistor is recommended for useful ranges of frequency. The capacitor value should be chosen such that 2048 clock periods are close to an integral multiple of the 60 Hz period for optimum 60 Hz line rejection. With OSCILLATOR SELECT input LOW, two on-chip capacitors and a feedback device are added to the oscillator. In this configuration, the oscillator will operate with most crystals in the 1 to 5 MHz range with no external components (Figure 11). The OSCILLATOR SELECT input LOW inserts a fixed 58 divider circuit between the BUFFERED OSCILLATOR OUTPUT and the internal clock. A 3.58 MHz TV crystal gives a division ratio providing an integration time given by: t = (2048 clock periods) 58 = 33.18 ms 3.58 MHz
The error is less than 1% from two 60 Hz periods, or 33.33 ms, which will give better than 40 dB, 60 Hz rejection. The converter will operate reliably at conversion rates up to 30 per second, corresponding to a clock frequency of 245.8 kHz. When the oscillator is to be overdriven, the OSCILLATOR OUTPUT should be left open, and the overdriving signal should be applied at the OSCILLATOR INPUT. The internal clock will be of the same duty cycle, frequency and phase as the input signal. When the OSCILLATOR SELECT is at GND, the clock will be 1/58 of the input frequency.
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
roll-over errors will be slightly worse than in the 4V case. For large common-mode voltage ranges, the integrator output swing must be reduced further. This will increase both noise and roll-over errors. To improve performance, 6V supplies may be used. Integrating Capacitor The integrating capacitor, CINT, should be selected to give the maximum integrator output voltage swing that will not saturate the integrator to within 0.3V from either supply. A 3.5V to 4V integrator output swing is nominal for the TC7109A, with 5V supplies and analog common connected to GND. For 7-1/2 conversions per second (61.72 kHz internal clock frequency), nominal values CINT and CAZ are 0.15 F and 0.33 F, respectively. These values should be changed if different clock frequencies are used to maintain the integrator output voltage swing. The value of CINT is given by: CINT = (2048 Clock Period) (20 A) Integrator Output Voltage Swing
24 OSC SEL
22 OSC IN
23 OSC OUT R C
25 BUFFERED OSC OUT
+ V OR OPEN
f OSC = 0.45/RC
Figure 10. TC7109A RC Oscillator
+ V
CLOCK
/ 58
24 OSC SEL 22 OSC IN 23 OSC OUT 25 BUFFERED OSC OUT
GND
CRYSTAL
Figure 11. TC7109A Crystal Oscillator
The integrating capacitor must have low dielectric absorption to prevent roll-over errors. Polypropylene capacitors give undetectable errors, at reasonable cost, up to +85C. Teflon(R) capacitors are recommended for the military temperature range. While their dielectric absorption characteristics vary somewhat between units, devices may be selected to less than 0.5 count of error due to dielectric absorption. Integrating Resistor The integrator and buffer amplifiers have a class A output stage with 100 A of quiescent current. They supply 20 A of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2.048V full-scale a 100 k resistor is recommended and for 409.6 mV full-scale a 20 k resistor is recommended. RINT may be selected for other values of full scale by: RINT = Full-Scale Voltage 20 A
Test Input
The counter and its outputs may be tested easily. When the TEST input is connected to GND, the internal clock is disabled and the counter outputs are all forced into the HIGH state. When the input returns to the 1/2 (V+-GND) voltage or to V+ and one clock is input, the counter outputs will all be clocked to the LOW state. The counter output latches are enabled when the TEST input is taken to a level halfway between V+ and GND, allowing the counter contents to be examined anytime.
Component Value Selection
The integrator output swing for full-scale should be as large as possible. For example, with 5V supplies and COMMON connected to GND, the nominal integrator output swing at full-scale is 4V. Since the integrator output can go to 0.3V from either supply without significantly effecting linearity, a 4V integrator output swing allows 0.7V for variations in output swing due to component value and oscillator tolerances. With 5V supplies and a common-mode voltage range of 1V required, the component values should be selected to provide 3V integrator output swing. Noise and
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Auto-Zero Capacitor As the auto-zero capacitor is made large, the system noise is reduced. Since the TC7109A incorporates a zero integrator cycle, the size of the auto-zero capacitor does not affect overload recovery. The optimal value of the auto-zero capacitor is between 2 and 4 times CINT. A typical value for CAZ is 0.33 F.
TELCOM SEMICONDUCTOR, INC.
12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
The inner foil of CAZ should be connected to pin 31 and the outer foil to the RC summing junction. The inner foil of CINT should be connected to the RC summing junction and the outer foil to pin 32 for best rejection of stray pickups. For low leakage at temperatures above +85C, use Teflon capacitors. Reference Capacitor A 1 F capacitor is recommended for most circuits. However, where a large common-mode voltage exists, a larger value is required to prevent roll-over error (e.g., the reference low is not analog common), and a 409.6 mV scale is used. The roll-over error will be held to 0.5 count with a 10 F capacitor. For temperatures above +80C use Teflon or equivalent capacitors for their low leakage characteristics. Reference Voltage To generate full-scale output of 4096 counts, the analog input required is VIN = 2 VREF. For 409.6 mV full scale, use a reference of 204.8 mV. In many applications, where the ADC is connected to a transducer, a scale factor will exist between the input voltage and the digital reading. For instance, in a measuring system, the designer might like to have a full-scale reading when the voltage for the transducer is 700 mV. Instead of dividing the input down to 409.6 mV, the designer should use the input voltage directly and select VREF = 350 mV. Suitable values for integrating resistor and capacitor would be 34 k and 0.15 F. This makes the system slightly quieter and also avoids a divider network on the input. Another advantage of this system occurs when temperature and weight measurements with an offset or tare are desired for non-zero input. The offset may be introduced by connecting the voltage output of the transducer between common and analog high, and the offset voltage between common and analog low, observing polarities carefully. In processor-based systems using the TC7109A, it may be more desirable to use software and perform this type of scaling or tare subtraction digitally. Reference Sources A major factor in the absolute accuracy of the ADC is the stability of the reference voltage. The 12-bit resolution of the TC7109A is one part in 4096, or 244 ppm. Thus, for the onboard reference temperature coefficient of 70 ppm/C, a temperature difference of 3C will introduce a one-bit absolute error. Where the ambient temperature is not controlled, or where high-accuracy absolute measurements are being made, it is recommended that an external high-quality reference be used. A reference output (pin 29) is provided which may be used with a resistive divider to generate a suitable reference voltage (20 mA may be sunk without significant variation in output voltage). A pull-up bias device is provided which sources about 10 A. The output voltage is nominally 2.8V below V+. When using the on-board reference, REF OUT (pin 29) should be connected to REF- (pin 39), and REF+ should be connected to the wiper of a precision potentiometer between REF OUT and V+. The test circuit shows the circuit for a 204.8 mV reference, generated by a 2 k precision potentiometer in series with a 24 k fixed resistor.
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Interfacing
Direct Mode Combinations of chip-enable and byte-enable control signals which may be used when interfacing the TC7109A to parallel data lines are shown in Figure 12. The CE/LOAD input may be tied low, allowing either byte to be controlled by its own enable (Figure 12A). Figure 12B shows the HBEN and LBEN as flag inputs, and CE/LOAD as a master enable, which could be the READ strobe available from most microprocessors. Figure 12C shows a configuration where the two byte enables are connected together. The CE/LOAD is a chip enable, and the HBEN and LBEN may be used as a second chip enable, or connected to ground. The 14 data outputs will be enabled at the same time. In the direct MODE, SEND should be tied to V+. Figure 13 shows interfacing several TC7109A's to a bus, ganging the HBEN and LBEN signals to several converters together, and using the CE/LOAD input to select the desired converter. Figures 14-19 give practical circuits utilizing the parallel three-state output capabilities of the TC7109A. Figure 14 shows parallel interface to the Intel MCS-48, -80 and 85 systems via an 8255 PPI, where the TC7109A data outputs are active at all times. The 8155 I/O ports may be used in an identical manner. This interface can be used in a read-after-update sequence, as shown in Figure 15. The data is accessed by the high-to-low transition of the STATUS driving an interrupt to the microprocessor. The RUN/HOLD input is also used to initiate conversions under software control. Figure 16 gives an interface to Motorola MC6800 or MOS Technology MCS650X system. An interrupt is generated through the Control Register B, CB1 line from the high-to-low transition of the STATUS output. The RUN/HOLD pin is controlled by CB2 through Control Register B, allowing software control of conversions.
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
Direct interfacing to most microprocessor busses is easily accomplished through the three-state output of the TC7109A. Figures 1, 17 and 18 are typical connection diagrams. To ensure requirements for setup and hold times, minimum pulse widths, and the drive limitations on long busses are met, it is necessary to carefully consider the system timing in this type of interface. This type of interface is used when the memory peripheral address density is low, providing simple address decoding. Interrupt handling can be simplified by using an interface to reduce the component count.
A.
GND MODE CE/LOAD B9-B12 POL, OR 6
B.
GND MODE
CHIP SELECT 1
C.
GND MODE
CHIP SELECT
CE/LOAD B1-B12 POL, OR 14
CE/LOAD B9-B12 POL, OR 6
TC7109A
B1-B8 ANALOG IN RUN/HOLD HBEN LBEN CONVERT GND OR CHIP SELECT 2 8 ANALOG IN
TC7109A
ANALOG IN RUN/HOLD HBEN LBEN CONVERT
TC7109A
B1-B8 RUN/HOLD HBEN LBEN CONVERT 8
CONTROL
BYTE FLAGS
Figure 12. Direct Mode Chip and Byte Enable Combinations
CONVERTER SELECT
CONVERTER SELECT
CONVERTER SELECT
GND MODE CE/LOAD B9-B12 POL, OR 6
GND MODE CE/LOAD B9-B12 POL, OR 6
GND MODE CE/LOAD B9-B12 POL, OR 6
TC7109A
B1-B8 ANALOG IN RUN/HOLD HBEN LBEN +5V 8 ANALOG IN
TC7109A
B1-B8 RUN/HOLD HBEN LBEN 8 ANALOG IN +5V
TC7109A
B1-B8 RUN/HOLD HBEN LBEN 8 +5V
BYTE SELECT FLAGS
Figure 13. Three-Stating Several TC7109A's to a Small Bus
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
1
ADDRESS BUS
2 3
CONTROL BUS
DATA BUS
GND MODE ANALOG IN CE/LOAD B9-B12 POL, OR RUN/HOLD 6 +5V 8 PB7-PB0 PC5 RD WR PA5-PA0 8255 (MODE 0) 87C48 8008, 8080, 8085, 8048, ETC. D7-D0 A0-A1 CS
TC7109A
B1-B8 STATUS
SEE TEXT
4 5
HBEN GND
LBEN
Figure 14. Full-Time Parallel Interface to MCS-48, -80, -85 Microcomputers
ADDRESS BUS
CONTROL BUS
DATA BUS
6
87C48 8008, 8080, 8085, 8048, ETC.
GND MODE ANALOG IN CE/LOAD B9-B12 POL, OR RUN/HOLD 6 RD WR PA5-PA0 PC6 8 STBA 1F 10k PB7-PB0 PC4 PC6 INTRA INTR 8255 D7-D0 A0-A1 CS
TC7109A
B1-B8 STATUS
7
HBEN GND
LBEN
+5V (SEE TEXT)
Figure 15. Full-Time Parallel Interface to MCS-48, -80, -85 Microcomputers With Interrupt
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
GND
MODE ANALOG IN B9-B12 POL, OR B1-B8 RUN/HOLD STATUS CE/ LOAD HBEN LBEN GND 6 PA-5 CRB - -11R-01 MC6800 OR MCS650X
TC7109A
8
PB-7 CB1 CB2
MC6820
ADDRESS DATA CONTROL BUS BUS BUS
Figure 16. Full-Time Parallel Interface to MC6800 or MCS650X Microprocessor
ADDRESS BUS A14 A15 CONTROL BUS RD * DATA BUS
HBEN ANALOG IN
LBEN B9-B12 POL, OR B1-B8 6 8008, 8080, 8085
TC7109A
8
CE/LOAD MODE RUN/HOLD * MEMR or IOR for 8080/8228 system. GND +5V
Figure 17. TC7109A Direct Interface to 8080/8085
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
GND +5V
1
2
6 MC6800 OR MCS650X 74C42 A0-A2 8
ANALOG IN
MODE RUN/HOLD B9-B12 POL, OR B1-B8 HBEN LBEN CE/LOAD
TC7109A
3
ADDRESS DATA CONTROL BUS BUS BUS
74C30
A15-A10
R/W, VMA
4 5 6
Figure 18. TC7109A Direct Interface to MC6800 Bus
ADDRESS BUS
CONTROL BUS
DATA BUS
B9-B12 POL, OR ANALOG IN B1-B8
RD WR 6
D7-D0
A0-A1 CS 87C48 8008, 8080, 8085, 8048, ETC.
8 STB A IBFA
PA7-PA0 PC4 PC5 PC PC6 PC7
TC7109A
CE/LOAD SEND RUN/HOLD MODE
8255 (MODE 1)
PC3
INTR
7
Figure 19. TC7109A Handshake Interface to MCS-48, -80, -85 Microcomputers
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
Handshake Mode The handshake mode provides an interface to a wide variety of external devices. The byte enables may be used as byte identification flags or as load enables and external latches may be clocked by the rising edge of CE/LOAD. A handshake interface to Intel microprocessors using an 8255 PPI is shown in Figure 19. The handshake operation with the 8255 is controlled by inverting its Input Buffer Full (IBF) flag to drive the SEND input to the TC7109A, and using the CE/LOAD to drive the 8255 strobe. The internal control register of the PPI should be set in MODE 1 for the port used. If the 8255 IBF flag is LOW and the TC7109A is in handshake mode, the next word will be strobed into the port. The strobe will cause IBF to go HIGH (SEND goes LOW), which will keep the enabled byte outputs active. The PPI will generate an interrupt which, when executed, will result in the data being read. The IBF will be reset LOW when the byte is read, causing the TC7109A to sequence into the next byte. The MODE input to the TC7109A is connected to the control line on the PPI. The data from every conversion will be sequenced in two bytes in the system, if this output is left HIGH, or tied HIGH separately. (The data access must take less time than a conversion.) The output sequence can be obtained on demand if this output is made to go from LOW to HIGH and the interrupt may be used to reset the MODE bit. Conversions may be obtained on command under software control by driving the RUN/HOLD input to the TC7109A by a bit of the 8255. Another peripheral device may be serviced by the unused port of the 8255. The 8155 may be used in a similar manner. The MCS650X microprocessors are shown in Figure 20 with MODE and RUN/HOLD tied HIGH to save port outputs. The handshake mode is particularly useful for directly interfacing to industry-standard UARTs (such as Western Digital TR1602), providing a means of serially transmitting converted data with minimum component count. A typical UART connection is shown in Figure 1. In this circuit, any word received by the UART causes the UART DR (Data Ready) output to go HIGH. The MODE input to the TC7109A goes HIGH, triggering the TC7109A into handshake mode. The high-order byte is output to the UART and when the UART has transferred the data to the Transmitter register, TBRE (SEND) goes HIGH again, LBEN will go HIGH, driving the UART DRR (Data Ready Reset) which will signal the end of the transfer of data from the TC7109A to the UART. An extension of the typical connection to several TC7109A's with one UART is shown in Figure 21. In this circuit, the word received by the UART (available at the RBR outputs when DR is HIGH) is used to select which converter will handshake with the UART. Up to eight TC7109A's may interface with one UART, with no external components. Up to 256 converters may be accessed on one serial line with additional components.
+5V MODE RUN/HOLD ANALOG IN CRA - -100-01 MC6820
TC7109A
CE/LOAD SEND LBEN HBEN
PA0-PA7 CA1 CA2
MC6800 OR MCS650X
ADDRESS BUS
DATA CONTROL BUS BUS
Figure 20.
TC7109A Handshake Interface to MCS-6800, MCS650X Microprocessors
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12-BIT P-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS TC7109 TC7109A
1
SERIAL OUTPUT 6402 CMOS UART TBRL DRR TBRE RBR1-RBR8 2 3 SFD GND SERIAL INPUT TBR1-TBR8
2 3
8-BIT DATA BUS
ANALOG IN
MODE CE/ SEND LOAD B9-B12 POL, OR B1-B8
6 ANALOG IN 8
MODE CE/ SEND LOAD B9-B12 POL, OR B1-B8
6 ANALOG IN 8
MODE CE/ SEND LOAD B9-B12 POL, OR B1-B8
6
8
4
+5V
TC7109A
RUN/HOLD HBEN LBEN +5V
TC7109A
RUN/HOLD HBEN LBEN +5V
TC7109A
RUN/HOLD HBEN LBEN
Figure 21.
Handshake Interface for Multiplexed Converters
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Integrating Converter Features
The output of integrating ADCs represents the integral, or average, of an input voltage over a fixed period of time. Compared with techniques in which the input is sampled and held, the integrating converter averages the effects of noise. A second important characteristic is that time is used to quantize the answer, resulting in extremely small nonlinearity errors and no missing output codes. The integrating converter also has very good rejection of frequencies whose periods are an integral multiple of the measurement period. This feature can be used to advantage in reducing line frequency noise (Figure 22).
NORMAL MODE REJECTION PLAN
30 t = MEASUREMENT PERIOD 20
10
0 0.1/t
1/t INPUT FREQUENCY
10/t
7
Figure 22. Normal Mode Rejection of Dual-Slope Converter as a Function of Frequency
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