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Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
DESCRIPTION
The NE568A is a monolithic phase-locked loop (PLL) which operates from 1Hz to frequencies in excess of 150MHz and features an extended supply voltage range and a lower temperature coefficient of the VCO center frequency in comparison with its predecessor, the NE 568. The NE568A is function and pin-compatible with the NE568, requiring only minor changes in peripheral circuitry (see Figure 3). Temperature compensation network is different, no resistor on Pin 12, needs to be grounded and Pin 13 has a 3.9k resistor to ground. Timing cap, C2, is different and for 70MHz operation with temperature compensation network should be 16pF, not 34pF as was used in the NE568. The NE568A has the following improvements: ESD protected; extended VCC range from 4.5V to 5.5V; operating temperature range -55 to 125C (see Signetics Military 568A data sheet); less layout sensitivity; and lower TC of VCO (center frequency). The integrated circuit consists of a limiting amplifier, a current-controlled oscillator (ICO), a phase detector, a level shift circuit, V/I and I/V converters, an output buffer, and bias circuitry with temperature and frequency compensating characteristics. The design of the NE568A is particularly well-suited for demodulation of FM signals with extremely large deviation in systems which require a highly linear output. In satellite receiver applications with a 70MHz IF, the NE568A will demodulate 20% deviations with less than 1.0% typical non-linearity. In addition to high linearity, the circuit has a loop filter which can be configured with series or shunt elements to optimize loop dynamic performance. The NE568A is available in 20-pin dual in-line and 20-pin SO (surface mounted) plastic packages.
PIN CONFIGURATION
D, N Packages
VCC2 1 GND2 2 20 19 18 17 16 LF1 LF2 LF3 LF4 FREQ ADJ
GND1 3 TCAP1 TCAP2 GND1 4 5 6
15 OUT FILT 14 VOUT
VCC1 7 REFBYP PNPBYP 8 9
13 TCADJ2 12 TCADJ1 11 VIN
INPBYP 10
TOP VIEW
SR01037
* Series or shunt loop filter component capability * External loop gain control * Temperature compensated * ESD protected1
APPLICATIONS
Figure 1. Pin Configuration
FEATURES
* Operation to 150MHz * High linearity buffered output
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Small Outline Large (SOL) Package 20-Pin Plastic Dual In-Line Package (DIP) 20-Pin Plastic Small Outline Large (SOL) Package 20-Pin Plastic Dual In-Line Package (DIP)
* Satellite receivers * Fiber optic video links * VHF FSK demodulators * Clock Recovery
TEMPERATURE RANGE 0 to +70C 0 to +70C -40 to +85C -40 to +85C ORDER CODE NE568AD NE568AN SA568AD SA568AN DWG # SOT163-1 SOT146-1 SOT163-1 SOT146-1
BLOCK DIAGRAM
LF1 20 LF2 19 LF3 18 LF4 17 FREQ ADJ 16 OUTFILT 15 VOUT 14 TCADJ2 13 TCADJ1 12 VIN 11
LEVEL SHIFT
OUT BUF
TCADJ
BIAS
LEVEL SHIFT V/I CONVERTER PHASE DETECTOR I/V CONVERTER AMP
NOTE: Pins 4 and 5 can tolerate 1000V only, and all other pins, greater than 2000V for ESD (human body model).
ICO
1 VCC2
2 GND2
3 GND1
4 TCAP1
5 TCAP2
6 GND1
7 VCC1
8 REFBYP
9 PNPBYP
10 INPBYP
SR01038
Figure 2. Block Diagram
1996 Feb 1
1
853-1558 16328
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC TJ TSTG PDMAX JA Supply voltage Junction temperature Storage temperature range Maximum power dissipation Thermal resistance PARAMETER RATING 6 +150 -65 to +150 400 80 UNITS V C C mW C/W
ELECTRICAL CHARACTERISTICS
The elctrical characteristics listed below are actual tests (unless otherwise stated) performed on each device with an automatic IC tester prior to shipment. Performance of the device in automated test set-up is not necessarily optimum. The NE568A is
layout-sensitive. Evaluation of performance for correlation to the data sheet should be done with the circuit and layout of Figures 3, 4, and 5 with the evaluation unit soldered in place. (Do not use a socket!)
DC ELECTRICAL CHARACTERISTICS
VCC = 5V; TA = 25C; fO = 70MHz, Test Circuit Figure 3, fIN = -20dBm, R4 = 3.9k, unless otherwise specified. LIMITS SYMBOL VCC ICC PARAMETER Supply voltage Supply current TEST CONDITIONS MIN 4.5 NE/SA568A TYP 5 54 MAX 5.5 70 V mA UNITS
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN fOSC Maximum oscillator operating frequency3 Input signal level BW Demodulated bandwidth Non-linearity5 Lock range2 range2 Dev = 20%, Input = -20dBm Input = -20dBm Input = -20dBm Figure 3 1 6 Dev = 20% of fO measured at Pin 14 VIN = -20dBm (30% AM) referred to 20% deviation Centered at 70MHz, R2 = 1.2k, C2 = 16pF, R4 = 3.9k (C2 + CSTRAY = 20pF) 4.5V to 5.5V -15 0.40 0.52 50 25 20 150 50 -201 fO/7 1.0 35 30 100 4.0 2000 +10 NE/SA568A TYP MAX MHz mVP-P dBm MHz % % of fO % of fO ppm/C k VP-P dB UNITS
Capture TC of fO RIN
Input resistance4 Output impedance Demodulated VOUT AM rejection Distribution6 Drift with supply
fO fO
0 2
+15
% %/V
NOTE: 1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance. 2. Limits are set symmetrical to fO. Actual characteristics may have asymmetry beyond the specified limits. 3. Not 100% tested, but guaranteed by design. 4. Input impedance depends on package and layout capacitances. See Figures 6 and 5. 5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (VOUT). Non-linearity is then calculated from a straight line over the deviation range specified. 6. Free-running frequency is measured as feedthrough to Pin 14 (VOUT) with no input signal applied.
1996 Feb 1
2
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
1 C1 2
VCC2 GND2
LF1
20
LF2
19 R1 C10
3
GND1
LF3
18 C9
4 RFC1 C2 5
TCAP1
LF4
17 R2
TCAP2
FREQADJ
16
6 C8 7
GND1
OUTFILT
15
C11 VOUT
14 VCC1 VOUT 13 REFBYP TCADJ2 TCADJ1 12
C12
R3
C3 VCC C5 C6 8 RFC2 C4 9 PNPBYP
R4
10 C7
INPBYP
11 VIN
C13 R5
VIN
SR01039
Figure 3. Test Circuit for AC Parameters
FUNCTIONAL DESCRIPTION
The NE568A is a high-performance phase-locked loop (PLL). The circuit consists of conventional PLL elements, with special circuitry for linearized demodulated output, and high-frequency performance. The process used has NPN transistors with fT > 6GHz. The high gain and bandwidth of these transistors make careful attention to layout and bypass critical for optimum performance. The performance of the PLL cannot be evaluated independent of the layout. The use of the application layout in this data sheet and surface-mount capacitors are highly recommended as a starting point. The input to the PLL is through a limiting amplifier with a gain of 200. The input of this amplifier is differential (Pins 10 and 11). For single-ended applications, the input must be coupled through a DC-blocking capacitor with low impedance at the frequency of interest. The single-ended input is normally applied to Pin 11 with Pin 10 AC-bypassed with a low-impedance capacitor. The input impedance is characteristically slightly above 500. Impedance match is not necessary, but loading the signal source should be avoided. When the source is 50 or 75, a DC-blocking capacitor is usually all that is needed. Input amplification is low enough to assure reasonable response time in the case of large signals, but high enough for good AM rejection. After amplification, the input signal drives one port of a multiplier-cell phase detector. The other port is driven by the current-controlled oscillator (ICO). The output of the phase comparator is a voltage proportional to the phase difference of the input and ICO signals. The error signal is filtered with a low-pass filter to provide a DC-correction voltage, and this voltage is converted to a current which is applied to the ICO, shifting the frequency in the direction which causes the input and ICO to have a 90 phase relationship. The oscillator is a current-controlled multivibrator. The current control affects the charge/discharge rate of the timing capacitor. It is common for this type of oscillator to be referred to as a
voltage-controlled oscillator (VCO), because the output of the phase comparator and the loop filter is a voltage. To control the frequency of an integrated ICO multivibrator, the control signal must be conditioned by a voltage-to-current converter. In the NE568A, special circuitry predistorts the control signal to make the change in frequency a linear function over a large control-current range. The free-running frequency of the oscillator depends on the value of the timing capacitor connected between Pins 4 and 5. The value of the timing capacitor depends on internal resistive components and current sources. When R2 = 1.2k and R4 = 0, a very close approximation of the correct capacitor value is: 0.0014 C* + F fO where C * + C 2 ) C STRAY The temperature-compensation resistor, R4, affects the actual value of capacitance. This equation is normalized to 70MHz. See 10 for correction factors. The loop filter determines the dynamic characteristics of the loop. In most PLLs, the phase detector outputs are internally connected to the ICO inputs. The NE568A was designed with filter output to input connections from Pins 20 ( DET) to 17 (ICO), and Pins 19 ( DET) to 18 (ICO) external. This allows the use of both series and shunt loop-filter elements. The loop constratints are: K O + 0.12V Radian (Phase Detector Constant) K O + 4.2 @ 10 9 Radians (ICO Constant) at 70MHz V -sec
The loop filter determines the general characteristics of the loop. Capacitors C9, C10, and resistor R1, control the transient output of the phase detector. Capacitor C9 suppresses 70MHz feedthrough by interaction with 100 load resistors internal to the phase detector.
1996 Feb 1
3
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
C9 +
1 F 2p (50) (f O)
Parts List and Layout 70MHz Application NE568AN
C1 C2 1 C2 2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 R2 100nF 18pF 16pF 100nF 100nF 6.8F 100nF 100nF 100nF 47pF 560pF 47pF 100nF 100nF 27 1.2k 43 3.9k 50 10H 10H 10% 10% 10% 10% 10% 10% 2% 2% 10% 10% 10% 10% 10% 10% 2% 2% 2% 10% 10% 10% Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Tantalum Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic CR32 Trim pot Ceramic CR32 Ceramic CR32 Ceramic CR32 chip chip chip 1/4W 1/4W 1/4W chip 50V 50V 0805 50V 50V 35V 50V 50V 50V 50V 50V 50V 50V 50V 1/4W
At 70MHz, the calculated value is 45pF. Empirical results with the test and application board were improved when a 47pF capacitor was used. The natural frequency for the loop filter is set by C10 and R1. If the center frequency of the loop is 70MHz and the full demodulated bandwidth is desired, i.e., fBW = fO/7 = 10MHz, and a value for R1 is chosen, the value of C10 can be calculated. C 10 + Also, C 11 + 1 2p350Wf BW(Hz) 1 F 2p R 1 f BW
This capacitance determines the signal bandwidth of the output buffer amplifier. (For further inofrmation see Philips application note AN1881 "The NE568A Phase Locked Loop as a Wideband Video Demodulator".
Parts List and Layout 40MHz Application NE568AD
C1 C2 1 C2 2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 R2 R3 3 R4 4 R5 3 RFC1
5
R3 3 R4 4 R5 3 RFC1 RFC2
100nF 18pF 16pF 100nF 100nF 6.8F 100nF 100nF 100nF 47pF 560pF 47pF 100nF 100nF 27 1.2k 43 3.9k 50 10H 10H
10% 2% 2% 10% 10% 10% 10% 10% 10% 2% 2% 2% 10% 10% 10% 10% 10% 10% 10% 10%
Ceramic chip Ceramic chip Ceramic ORChip Ceramic chip Ceramic chip Tantalum Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Ceramic chip Chip CR32 Trim pot Chip CR32 Chip CR32 Chip CR32 Surface mount Surface mount
1206 0805 1206 1206 35V 1206 1206 1206 0805 or 1206 0805 or 1206 0805 or 1206 1206 1206 1/4W 1/4W 1/4W 1/4W
Surface mount Surface mount
NOTES: 1. 18pF with Pin 12 ground and Pin 13 no connect (open). 2. C2 + CSTRAY = 16pF for temperature-compensated configuration with R4 = 3.9k. 3. For 50 setup. R1 = 62, R3 = 75 for 75 application. 4. For test configuration R4 = 0 (GND) and C2 = 18pF.
RFC25
NOTES: 1. 18pF with Pin 12 ground and Pin 13 no connect (open). 2. C2 + CSTRAY = 16pF for temperature-compensated configuration with R4 = 3.9k. 3. For 50 setup. R1 = 62, R3 = 75 for 75 application. 4. For test configuration R4 = 0 (GND) and C2 = 18pF. 5. 0 chip resistors (jumpers) may be substituted with minor degradation of performance.
1996 Feb 1
4
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
NE568A KT10/89
GND
V CC
V OUT V IN
SR01040
Figure 4. N Package Layout (Not Actual Size)
GND V CC SIGNETICS NE568A SO
OUTPUT INPUT
SR01041
Figure 5. D Package Layout (Not Actual Size)
1.25E3
1.25E3
1.0E3
1.0E3 ZIN
Z IN
750.0
ZIN Z IN
750.0
500.0
500.0
RIN
250.0
250.0
0.0 1.0
10.0
100.0
0.0 1.0
10.0
100.0
1.0E3
FREQUENCY (MHz)
SR01042
FREQUENCY (MHz)
SR01043
Figure 6. NE568A Input Impedance With CP = 0.5pF 20-Pin SO Package
Figure 7. NE568A Input Impedance WithCP = 1.49pF 20-Pin Dual In-Line Plastic Package
1996 Feb 1
5
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
4.0
3.5 VOLTS 3.0 2.5 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (MHz)
SR01044
Figure 8. Typical Output Linearity
100 80 78 95
FO MHz
76 74
90
72 70
85
68 66
MHz
ICC
75
62 60 58
70
56 54
65
52 50
60
48 46
55
44 42
50 0.8 0.9 1.0 1.1 1.2 Frequency Adjust (k) 1.3 1.4 1.5 1.6
40
SR01045
Figure 9. NE568: Frequency Adjust vs FO and ICC
1996 Feb 1
6
I CC mA
80
64
FO
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
12.0 11.5 11.0 10.5 10.0 9.5 9.0 (k ) 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 10 20 30 40 50 60 70 80 FO MHz 90 100 110 120 130 140 150 160 C = 150pF C = 16pF C = 6.8pF
R
tc
SR01046
Figure 10. NE568A: Rtc (Pin 13) vs FO; Choosing the Optimum Temperature Compensation Resistor
RFC1 10H 1 C1 0.1F VCC2 LF1 20
+5V VCC + C6 10F C5 0.1F
2
GND2
LF2 19 R1 27 C9 47pF R6 1.5k (Optional. Leave it open if not used) (Output Amp Gain Adj -2dB) J3 VOUT (ZO = 50)* R4 3.9k C10 560pF
GND J1
3
GND1
LF3 18
4 C2 18pF
TCAP1
LF4
17
5
TCAP2
FREQADJ
16 R2 2k C11 47pF R3 43
NE/SA568A
6 RFC2 10H C8 0.1F GND1 OUTFILT 15
7
VCC1
VOUT
14
C12 0.1F
C3 0.1F 8 C4 0.1F
REFBYP
TCADJ2
13
9
PNPBYP
TCADJ1
12 J2 VIN
10 C7 0.1F
INPBYP
VIN
11 C13 0.1F R5 51
*NOTE: For 75 output impedance, use R3 = 68.
SR01113
Figure 11. Phase Locked Loop NE/SA568A
1996 Feb 1
7
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
COMPONENTS LAYOUT
C10
NE568AN
70MHz PLL10569 R2 C11 R6 C12 C9 R4 C13 R3 OUT R1
C6
C5
RFC1 C1 RFC2 C2 C3 C8 C4 C7 R5
+5V
GND
IN
TOP
BOTTOM
SR01114
Figure 12. NE568AN Board Layout (Not Actual Size)
1996 Feb 1
8
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
0.1 F
10 H
10 F
RFC1
+5V GND
J1
R6 1.5k C1 0.1F U1
560pF C10 27 C9 47pF R1 R2 VOUT
C6
C5
2K
NE568AD
10 H
RFC2
18pF
C11 47pF 0.1F 3.9k C12 R4
43 R3 J3
C3 0.1 F
C8 0.1 F
C4 0.1 F C7 0.1F R5 J2
NE568AD
70MHz PLL10570
0.1F 51
C13
VIN
SR01115
Figure 13. NE568AD Board Layout (Not Actual Size)
1996 Feb 1
9

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