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CT1990/1 Series
MIL-STD-1553B Remote Terminal, Bus Controller, or Passive Monitor Hybrid with Status Word Control
Features
* Performs the Complete Dual-Redundant Remote Terminal, Bus Controller Protocol and Passive Monitor Functions of MIL-STD-1553B * Automated Self-Test Functions * Allows setting of the Message Error Bit on illegal commands * Provides programmable control over Terminal Flag and Subsystem Flag Status Bits * MIL-PRF-38534 Compliant Circuits Available * 50 mw Typical Power Consumption * Small Size * Available in Ceramic Plug-in Package Configuration CIRCUIT TECHNOLOGY * Compatible with all ACT Driver/Receiver Units * 5V DC Operation * Full Military (-55C to +125C) Temperature Range * DESC SMD# 5962-94775: Released CT1990, Pending CT1991
1
General Description
The CT1990/1 Series is a monolithic implementation of the MIL-STD-1553B Bus Controller, Remote Terminal and Passive Monitor functions. All protocol functions of MIL-STD-1553B are incorporated and a number of options are included to improve flexibility. These features include programming of the status word, illegalizing specific commands and an independent loop back self-test which is initiated by the subsystem. This unit is directly compatible with all transceivers and microprocessor interfaces such as the CT1611 and CT1800 produced by Aeroflex Incorporated. Block Diagram (With Transformers)
Encoder
Interface Unit
Sub Address & Word Count Outputs
BUS "0"
T/R Hybrid Driver Select & Enable T/R Hybrid
Decoder "O"
Status Word Control
Program Inputs
Discrete Outputs
BUS "1"
Decoder "1"
Internal Highway Control
Control Inputs
Terminal Address Inputs
CT1990/1
eroflex Circuit Technology - Data Bus Modules For The Future (c) SCD1990 REV B 8/21/00
Absolute Maximum Ratings
Parameter
Supply Voltage (VDD) Input or Output Voltage at any Pad Storage Case Temperature
Range
-0.3 to +7.0 -0.3 to (VDD + 0.3) -65 to +150
Units
V V C
Recommended DC Operating Conditions
Parameter
Vcc Power Supply Voltage Vcc VIH High Level Input Voltage, Vcc = 5V VIL Low Level Input Voltage, Vcc = 5V
Min
4.5 2.2
Typ
5.0
Max
5.5
Unit
V V
Notes
1,2 1,2
0.7
V
Electrical Characteristics
(TA = -55C to +125C)
Parameter
VOH High Level Output Voltage VOL Low Level Output Voltage IIH High Level Input Current
Test Conditions
Vcc = 4.5V Vcc = 4.5V Vcc = 5.5V, VIN = 2.4V
Min
2.4
Max
Unit
V
Notes
4 4 2 3 2 3 4
0.4 -200 -25 -700 -400 -900 -400 20
V A A A A mA
IIL Low Level Input Current
Vcc = 5.5V, VIN = 0.4V
-400 -25
ICC Supply Current
Vcc = 5.5V
Notes: 1. RTAD 0/1/2/3/4 and RTADPAR ONLY. 2. ALL Inputs and Bidirectionals other than those in Note 1. 3. lOL max = 3mA / lOH max = -2mA TX INHIBIT 0/1 and TX DATA/DATA ONLY. IOL max = 2mA / lOH max = -1 mA. ALL remaining Outputs and Bidirectionals. 4. Input Clock (running) = 6Mhz, ALL remaining Inputs are Open and ALL Outputs and Bidirectionals have no load.
Clock Requirements
Frequency Stability -55C to +125C Maximum Asymmetry Rise/Fall Time Output Level 6.0 MHz 0.01% (100ppm) 48 - 52% 10ns MAX Logic "0" 0.4V MAX Logic "1" 2.4V MIN
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REMOTE TERMINAL OPERATION
Receive Data Operation
All valid data words associated with a valid receive data command word for the RT are passed to the subsystem. The RT examines all command words from the bus and will respond to valid (i.e. correct Manchester, parity coding etc.) commands which have the correct RT address (or broadcast address if the RT broadcast option is enabled). When the data words are received, they are decoded and checked by the RT and, if valid, passed to the subsystem on a word by word basis at 20 s intervals. This applies to receive data words in both Bus Controller to RT and RT to RT messages. When the RT detects that the message has finished, it checks that the correct number of words have been received and if the message is fully valid, then a Good Block Received signal is sent to the subsystem, which must be used by the subsystem as permission to use the data just received. The subsystem must therefore have a temporary buffer store up to 32 words long into which these data words can be placed. The Good Block Received signal will allow use of the buffer store data once the message has been validated. If a block of data is not validated, then Good Block Received will not be generated. This may be caused by any sort of message error or by a new valid command for the RT being received on another bus to which the RT must switch.
Transmit Data Operation
If the RT receives a valid transmit data command addressed to the RT, then the RT will request the data words from the subsystem for transmission on a word by word basis. To allow maximum time for the subsystem to collect each data word, the next word is requested by the RT as soon as the transmission of the current word has commenced. It is essential that the subsystem should provide all the data words requested by the RT once a transmit sequence has been accepted. Failure to do so will be classed by the RT as a subsystem failure and reported as such to the Bus Controller.
Control of Data Transfers
This section describes the detailed operation of the data transfer mechanism between the RT and subsystems. It covers the operations of the signals DTRQ, DTAK, IUSTB, H/L, GBR, NBGT, TX/RX during receive data and transmit data transfers. Figure 7 shows the operation of the data handshaking signals during a receive command with two data words. When the RT has fully checked the command word, NBGT is pulsed low, which can be used by the subsystem as an initialization signal. TX/RX will be set low indicating a receive command. When the first data word has been fully validated, DTRQ is set low. The subsystem must then reply within approximately 1.5 s by setting DTAK low. This indicates to the RT that the subsystem is ready to accept data. The data word is then passed to the subsystem on the internal highway IH08-IH715 in two bytes using IUSTB as a strobe signal and H/L as the byte indicator (high byte first followed by low byte). Data is valid about both edges of IUSTB. Signal timing for this handshaking is shown in Figure 12. If the subsystem does not declare itself busy, then it must respond to DTRQ going low by setting DTAK low within approximately 1.5 us. Failure to do so will be classed by the RT as a subsystem failure and reported as such to the Bus Controller. It should be noted that IUSTB is also used for internal working in the RT. DTRQ being low should be used as an enable for clocking data to the subsystem with IUSTB. Once the receive data block has finished and been checked by the RT, GBR is pulsed low if the block is entirely correct and valid. This is used by the subsystem as permission to make use of the data block. If no GBR signal is generated, then an error has been detected by the RT and the entire data block is invalid and no data words in it may be used. If the RT is receiving data in an RT to RT transfer, the data handshaking signals will operate in an identical fashion but there will be a delay of approx 70 s between NBGT going low and DTRQ first going low. See Figure 10.
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Figure 6 shows the operation of the data handshaking signals during transmit command with three data words. As with the receive command discussed previously, NBGT is pulsed low if the command is valid and for the RT. TX/RX will be set high indicating a transmit data command. While the RT is transmitting its status word, it requests the first data word from the subsystem by setting DTRQ low. The subsystem must then reply within approximately 13.5 s by setting DTAK low. By setting DTAK low, the subsystem is indicating that it has the data word ready to pass to the RT. Once DTAK is set low by the subsystem, DTRQ should be used together with H/L and TX/RX to enable first the high byte and then the low byte of the data word onto the internal highway IH08-IH715. The RT will latch the data bytes during IUSTB, and will then return DTRQ high. Data for each byte must remain stable until IUSTB has returned low. Signal timing for this handshaking is shown in Figure 11.
Additional Data Information Signals
At the same time as data transfers take place, a number of information signals are made available to the subsystem. These are INCMD, the subaddress lines SA0-SA4, the word count lines WC0-WC4 and current word count lines CWC0-CWC4. Use of these signals is optional. INCMD will go active low while the RT is servicing a valid command for the RT. The subaddress, transmit/receive bit, and word count from the command word are all made available to the subsystem as SA0-SA4, TX/RX and WC0-WC4 respectively. They may be sampled when INCMD goes low and will remain valid while INCMD is low. The subaddress is intended to be used by the subsystem as an address pointer for the data block. Subaddress 0 and 31 are mode commands, and there can be no receive or transmit data blocks associated with these. (Any data word associated with a mode command uses different handshaking operations. If the subsystem does not use all the subaddresses available, then some of the subaddress lines may be ignored. The TX/RX signal indicates the direction of data transfer across the RT - subsystem interface. Its use is described in the previous section. The word count tells the subsystem the number of words to expect to receive or transmit in a message, up to 32 words. A word count of all 0s indicates a count of 32 words. The current word count is set to 0 at the beginning of a new message and is incremented following each data word transfer across the RT - subsystem interface. (It is clocked on the falling edge of the second IUSTB pulse in each word transfer). It should be noted that there is no need for the subsystem to compare the word count and current word count to validate the number of words in a message. This is done by the RT.
Subsystem Use of Status Bits and Mode Commands
General Description
Use of the status bits and the mode commands is one of the most confusing aspects of MIL-STD-1553B. This is because much of their use is optional, and also because some involve only the RT while others involve both the RT and the subsystem. The CT1990/1 allows full use to be made of all the Status Bits, and also implements all the Mode Commands. External programming of the Terminal Flag and Subsystem Flag Bits plus setting of the Message Error Bit on reception of an illegal command when externally decoded is available. The subsystem is given the opportunity to make use of Status Bits, and is only involved in Mode Commands which have a direct impact on the subsystem. The mode commands in which the subsystem may be involved are Synchronize, Sychronize with data word, Transmit Vector Word, Reset and Dynamic Bus Control Acceptance. The Status Bits to which the subsystem has access, or control are Service Request, Busy, Dynamic Bus Control Acceptance, Terminal Flag, Subsystem Flag, and Message Error Bit. Operation of each of these Mode Commands and of the Status Bits is described in the following sections. All other Mode Commands are serviced internally by the RT. The Terminal Flag and Message Error Status Bits and BIT Word contents are controlled by the RT; however the subsystem has the option to set the Message Error Bit and to control the reset conditions for the Terminal Flag and Subsystem Flag Bits in the Status Word, and the Transmitter Timeout, Subsystem Handshake, and Loop Test Fail Bits in the BIT Word.
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Synchronize Mode Commands
Once the RT has validated the command word and checked for the correct address, the SYNC line is set low. The signal WC4 will be set low for a Synchronize mode command (See Figure 16), and high for a Synchronize with data word mode command (See Figure 15). In a Synchronize with data word mode command, SYNC remains low during the time that the data word is received. Once the data word has been validated, it is passed to the subsystem on the internal highway IH08-IH715 in two bytes using IUSTB as a strobe signal and H/L as the byte indicator (high byte first followed by low byte). SYNC being low should be used on the enable to allow IUSTB to clock synchronize mode data to the subsystem. If the subsystem does not need to implement either of these mode commands, the SYNC signal can be ignored, since the RT requires no response from the subsystem.
Transmit Vector Word Mode Command
Figure 14 illustrates the relevant signal timings for an RT receiving a valid Transmit Vector Word mode command. The RT requests data by setting VECTEN low. The subsystem should use H/L to enable first the high byte and then the low byte of the Vector word onto the internal highway IH08-IH715. It should be noted that the RT expects the Vector word contents to be already prepared in a latch ready for enabling onto the internal highway when VECTEN goes low. If the subsystem has not been designed to handle the Vector word mode command, it will be the fault of the Bus Controller if the RT receives such a command. Since the subsystem is not required to acknowledge the mode command, the RT will not be affected in any way by Vector word circuitry not being implemented in the subsystem. It will however transmit a data word as the Vector word, but this word will have no meaning.
Reset Mode Command
Figure 8 shows the relevant signal timings for an RT receiving a valid reset mode command. Once the command word has been fully validated and serviced, the RESET signal is pulsed low. This signal may be used as a reset function for subsystem interface circuitry.
Dynamic Bus Allocation
This mode command is intended for use with a terminal which has the capability of configuring itself into a bus controller on command from the bus. The line DBCREQ cannot go true unless the DBCACC line was true at the time of the valid command, i.e. tied low. For terminals acting only as RTs, the signal DBCACC should be tied high (inactive), and the signal DBCREQ should be ignored and left unconnected.
Use of the Busy Status Bit
The Busy Bit is used by the subsystem to indicate that it is not ready to handle data transfers either to or from the RT. The RT sets the bit to logic one if the BUSY line from the subsystem is active low at the time of the second falling edge of INCLK after INCMD goes low. This is shown in Figure 13. Once the Busy bit is set, the RT will stop all receive and transmit data word transfers to and from the subsystem. The data transfers in the Synchronize with data word and Transmit Vector word mode commands are not affected by the Busy bit and will take place even if it has been set. It should be noted that a minimum of 0.5 s subaddress decoding time is given to the subsystem before setting of status bits. This allows the subsystem to selectively set the Busy bit if for instance one subaddress is busy but others are ready. This option will prove useful when an RT is interfacing with multiple subsystems.
Use of the Service Request Status Bit
The Service Request bit is used by the subsystem to indicate to the Bus Controller that an asynchronous service is requested. The timing of the setting of this bit is the same as the Busy bit and is shown in Figure 13. Use of SERVREQ has no effect on the RT apart from setting the Service Request bit. It should be noted that certain mode commands require that the last status word be transmitted by the RT
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instead of the current one, and therefore a currently set status bit will not be seen by the Bus Controller. Therefore the user is advised to hold SERVREQ low until the requested service takes place.
Use of the Subsystem Status Bit
This status bit is used by the RT to indicate a subsystem fault condition. If the subsystem sets SSERR low at any time, the subsystem fault condition in the RT will be set, and the Subsystem Flag status bit will subsequently be set. The fault condition will also be set if a handshaking failure takes place during a data transfer to or from the subsystem. The fault condition is cleared on power-up or by a Reset mode command.
Dynamic Bus Control Acceptance Status Bit
DBCACC, when set true, enables an RT to configure itself into a Bus Controller, if the subsystem has the capability, by allowing DBCREQ to pulse true and BIT TIME 18 to be set in the status response. If Dynamic Bus Control is not required then DBCACC must be tied high. DBCACC tied high inhibits DBCREQ and clears BIT TIME 18 in the status response.
OPTIONAL STATUS WORD CONTROL
Message Error Bit
The CT1990/1 monitors all receptions for errors and sets the Message Error Bit as prescribed in MIL-STD-1553B. The subsystem designer may, however, exercise the option of monitoring for illegal commands and forcing the Message Error Bit to be set. The word count and subaddress lines for the current command are valid when INCMD goes low. The subsystem must then determine whether or not the word count or subaddress is to be considered illegal by the RT. If either of them is considered illegal, the subsystem must produce a positive-going pulse called MEREQ. The positive-going edge of MEREQ must occur within 500 ns of the falling edge of INCMD .
Subsystem Flag and Terminal Flag Bits
The conditions that cause the Subsystem Flag and Terminal Flag Bits in the Status Word to be reset may be controlled by the subsystem using the ENABLE, BIT DECODE, NEXT STATUS, and STATUS UPDATE inputs. If ENABLE is inactive (high), then the Terminal Flag and Subsystem Flag behavior is the same as described below: (i.e. the other three option lines are disabled). Subsystem Flag Bit This bit is reset to logic zero by a power up initialization or the servicing of a legal mode command to reset the remote terminal (code 01000). This bit shall be set in the current status register if the subsystem error line, SSERR, from the subsystem ever goes active low. This bit shall also be set if an RT/subsystem handshaking failure occurs. This bit, once set, shall be repeatedly set until the detected error condition is known to be no longer present. Terminal Flag Bit This bit is reset to logic zero by a power up initialization or the servicing of a legal mode command to reset the remote terminal (code 01000). This bit can be set to logic one in the current status register in four possible ways: a) If the RX detects any message encoding error in the terminals transmission. A loop test failure, LTFAIL, will be signalled which shall cause the Terminal Flag to be set and the transmission aborted. b) If a transmitter timeout occurs while the terminal is transmitting. c) If a remote terminal self test fails. d) If there is a parity error in the hard wired address to the RX chip. This bit, once set, shall be repeatedly set until the detected error condition is known to be no longer present. The transmission of this bit as a logic one can be inhibited a legal mode command to inhibit terminal flag bit (code 00110). Similarly, this inhibit can be removed by a mode command to override inhibit terminal flag bit (code 00111), a power up initialization or a legal mode command to reset remote terminal (code 01000).
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If ENABLE is held low, then the three options described below are available and are essentially independent. Any, all, or none may be selected. Also, reporting of faults by the subsystem requires that SSERR be latched (not pulsed) low until the fault is cleared.
Resetting SSF and TF on Receipt of Valid Commands
If ENABLE is selected and the other three option lines are held high, then the Status Word Register will be reset on receipt of any valid command with the exception of Transmit Status and Transmit Last Command. Note that in this mode, the TF will never be seen in the Status Word, and the SSF will only be seen if SSERR is latched low. Also note that the SSF will not be seen in response to Transmit Status or Transmit Last Command if the preceding Status Word was clear, regardless of actions taken on the SSERR line after the clear status transmission.
Status Register Update at Fault Occurrence
If STATUS UPDATE is selected (held low), then the TF or SSF will appear in response to a Transmit Status or Transmit Last Command issued as the first command after the fault occurs. Any other command (except as noted in the Preserving the BIT Word section) will reset the TF and SSF. Repeated Transmit Status or Transmit Last Command immediately following the fault will continue to show the TF and/or SSF in the Status Word. Note that this behavior may not meet the "letter-of-the-spec" as described in MIL-STD-1553B, but is considered the "preferred" behavior by some users.
TF and SSF Reporting in the Next Status Word After the Fault
If NEXT STATUS is selected (held low), then the TF or SSF will appear in response to the very next valid command after the fault except for Transmit Status or Transmit Last Command. The flag(s) will be reset on receipt of any valid command following the status transmission with the flag(s) set except for Transmit Status, Transmit Last Command, or as noted in the following section on Preserving the BIT Word.
Preserving the BIT Word
In order to preserve the Transmitter Timeout Flag, Subsystem Handshake Failure, and Loop Test Failure Bits in the BIT Word, it is necessary to select BIT DECODE (hold it low). This will prevent resetting those bits if the Transmit Bit Word Mode Command immediately follows the fault or follows a Transmit Last Command or Transmit Status immediately following the fault. It will also prevent resetting the TF and SSF Bits in the Status Word. Any other valid commands will cause those BIT Word Bits and the Status Word Bits to be reset.
Bus Driver/Receiver Interface
Receive Data
The decoder chip requires two TTL signals, RXDATA and RXDATA, to represent the data coming in from the bus. PDIN should be driven to a logic level `1' when the bus waveform exceeds a specified positive threshold and NDIN should be driven to a logic level `1' when a specified negative threshold is exceeded. During the quiet period on the bus both signals should be at the same logic level. All the bus receivers must be permanently enabled, the selection of the bus in use is controlled within the ASIC.
Transmit Data
The signals generated by the encoder chip, TXDATA and TXDATA, are of the same format as the receive data. The only difference is that the TTL signals are negative logic, e.g. the signal is active when on logic level "0". This means that when the encoder is quiet both TXDATA and TXDATA are at logic level "1". Both the signals should be used in conjunction with TXINHIBIT 0 and TXINHIBIT 1. TX INHIBIT 0 and TX INHIBIT 1 enable the appropriate driver when it should be transmitting. Figure 5 shows an example of a typical interface circuit between the CT1990/1 and a driver/receiver unit.
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BUS CONTROL OPERATION
To enable its use in a bus controller the ASIC has additional logic within it. This logic can be enabled by pulling the pin labelled RT/BC low. Once the ASIC is in bus control mode, all data transfers must be initiated by the bus control processor correctly commanding the ASIC via the subsystem interface. In bus control mode six inputs are activated which in RT mode are inoperative and four signals with dual functions exercise the second function (the first being for the RT operation). To use the CT1990/1 as a 1553B bus control interface, the bus control processor must be able to carry out four basic bus-related functions. Two inputs, BCOPA and BCOPB allow these four options to be selected. The option is then initiated by sending a negative-going strobe on the BCOPSTB input. BCOPSTB must only be strobed low when NDRQ is high. This is particularly important when two options are required during a single transfer. With these options all message types and lengths can be handled. Normal BC/RT exchanges are carried out in ASIC option zero. This is selected by setting BCOPA and BCOPB to a zero and strobing BCOPSTB. On receipt of the strobe, the CT1990/1 loads the command word from an external latch using CWEN and H/L The command word is transmitted down the bus. The TX/RX bit is, however, considered by the ASIC as being its inverse and so if a transmit command is sent to a RT (Figure 17), the ASIC in BC mode believes it has been given a receive command. As the RT returns the requested number of data words plus its status, the BC carries out a full validation check and passes the data into the subsystem using DTRQ, DTAK, H/L, IUSTB and CWC as in RT operation. It also supplies GBR at the end of a valid transmission. Conversely, a receive command sent down the bus is interpreted by the BC as a transmit command, and so the requisite data words are added to the command word. See Figure 18. For mode commands, where a single command word is required, option one is selected by strobing BCOPSTB when BCOPA is high and BCOPB is low. On receiving the strobe, the command word is loaded from the external latch using CWEN and H/L, the correct sync and parity bits are added and the word transmitted (See Figure 20). Mode commands followed by a data word requires option two. Option two, selected by strobing BCOPSTB while BCOPA is low and BCOPB is high, loads a data word via DWEN and H/L, adds sync and parity and transmits them to the bus (See Figure 21). If the mode code transmitted required the RT to return a data word, then selecting option three by strobing BCOPSTB when BCOPA and BCOPB are both high will identify that data word and if validated, output it to the subsystem interface using RMDSTB and H/L. This allows data words resulting from mode codes to be identified differently from ordinary data words and routed accordingly (See Figure 22). All received status words are output to the subsystem interface using STATSTB and H/L. In BC option three, if the signal PASMON is active, then all data appearing on the selected bus is output to the subsystem using STATSTB for command and status words or RMDSTB for data words. RT to RT transfers require the transmission of two command words. A receive command to one RT is contiguously followed by a transmit command to the other RT. This can be achieved by selecting option one followed by option zero for the second command. The strobe (BCOPSTB) for option zero must be delayed until NDRQ has gone low and returned high following the strobe for option one. The RT transmissions are checked and transferred in the subsystem interface to the bus control processor (See Figure 19). Note: For all BC operations, BCOPA and BCOPB must remain valid and stable for a minimum of 1 s following the leading (negative going) edge of BCOPSTB.
PASSIVE MONITOR
The Monitor Mode may be utilized to analyze or collect all activities which occur on a selected bus. This is initiated by selecting a bus, placing the unit in BC option three and setting PASMON low. All data appearing on the selected bus is output to the subsystem using STATSTB for Command and Status Words or RMDSTB for Data Words.
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AUTOMATED SELF-TEST
The CT1991 has been designed to fully support a wrap-around self-test which ensures a high degree of fault coverage. The monolithic circuit includes all circuitry required to perform the self-test. Self-test can be an on-line or off-line function which is initiated by simple subsystem intervention. The DRVINH signal selects on-line or off-line testing. The circuit accomplishes the on-line test without accessing the MIL-STD-1553 data bus by providing an internal data path which connects the encoder circuitry directly to the decoder circuitry. The transceiver is inhibited during this on-line test. The off-line test is designed to include the transceiver as well as the protocol device. This mode will generally be useful as an off-line card test where no live bus is in use. To initiate the self-test a word is placed in the Vector Word Latch, Loop Test Enable (LTEN) is held low, and the Loop Test Trigger (LTTRIG) signal is pulsed low. The primary bus will be tested with the word that resides in the Vector Word Latch, encoded then looped back, decoded and presented to the subsystem as a normal data transfer would be accomplished. The secondary bus is sequentially tested after the primary bus is completed via Request Bus A (REQBUSA) utilizing the same word residing in the Vector Word Latch. Upon completion of each test, pass/fail signals will be asserted reporting the results of the test. This test implementation verifies MIL-STD-1553 protocol compliance; proper sync character, 16 data bits, Manchester II coding, odd parity, contiguous word checking and a bit by bit comparison of the transmitted data. The self-test circuitry increases the fault coverage by insuring that the internal function blocks; encoder, decoder, and internal control circuitry are operating correctly. An effective data pattern to accomplish this is HEX AA55 since each bit is toggled, (8 bit internal highway) on a high/low byte basis. The total time required to complete the self-test cycle is 89 microseconds. The Loop Test Enable signal must remain in the low state throughout the diagnostic cycle.
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Pin Description
Signal
RX DATA 0/1
Direction
INPUT
Signal Description
Positive Data In. This should be a TTL description of the positive, half of the Manchester code data on the bus. It should be driven to a logic level "1" when a predetermined positive threshold is exceeded on the bus. Negative Data In. This should be a TTL description of the negative half of the Manchester code data on the bus. It should be driven to a logic level "1" when a predetermined negative threshold is exceeded on the bus. Transmitter Inhibit Bus 0. Normally high. Goes low when the transmitter is transmitting. Should be used to Inhibit the bus "0" driver. Transmitter Inhibit Bus 1. Normally high. Goes low when the transmitter is transmitting. Should be used to Inhibit the bus "1" driver. Positive Data Out - When this signal goes high the bus should be driven positive. Negative Data Out - When this signal goes high the bus should be driven negative. RT address lines - These should be hardwired by the user. RTAD4 is the most significant bit. RT address parity line - This must be hardwired by the user to give odd parity. Built-ln Test Decode - When held low, prevents resetting TXTO Bit, HSFAIL Bit, and LTFAIL Bit in the BIT Word (as well as TF and SSF Bits in the Status Word) upon receipt of a Transmit Bit Word Mode Command. Broadcast command enable Bus 0/1 - When low the recognition of broadcast command is prevented on both Bus 0 and 1. CT1991 only. Broadcast command enable Bus 0 - When low the recognition of broadcast command is prevented on Bus 0. CT1990 only. Broadcast command enable Bus 1 - When low the recognition of broadcast command is prevented on Bus 1. CT1990 only. 6 Megahertz master clock. Internal Highway - Bi-directional 8 bit highway on which 16 bit words are passed in two bytes. IH 715 is the most significant bit of each byte, the most significant byte being transferred first. The highway should only be driven by the subsystem when data is to be transferred to the RT.
RX DATA 0/1
INPUT
TX INHIBIT 0 TX INHIBIT 1 TX DATA TX DATA RTAD 0-4 RTADPAR BIT DECODE
OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT
BCSTEN 0/1 BCSTEN 0 BCSTEN 1 6MCK IH 08 (LSB) IH 19 IH 210 IH 311 IH 412 IH 513 IH614 IH715 (MSB) DTRQ DTAK IUSTB H/L GBR
INPUT INPUT INPUT INPUT BI-DIRECTIONAL
OUTPUT INPUT OUTPUT OUTPUT OUTPUT
Data Transfer Request - Goes low to request a data transfer between the ASIC and subsystem. Goes high at the end of the transfer. Data Transfer Acknowledge - Goes low to indicate that the subsystem is ready for the data transfer. Interface Unit Strobe - This is a double pulse strobe used to transfer the two bytes of data High/Low - Indicates which byte of data is on the internal highway. Logic level "0" for least significant byte. Good Block Received - Pulses low for 500ns when a block of data has been received by the ASIC and has passed all the validity and error checks.
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Pin Description (Cont.)
Signal
NBGT MEREQ TX/RX INCMD WC0-WC4 SA0-SA4 CWC0-CWC4 SYNC VECTEN/DWEN
Direction
OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
Signal Description
New Bus Grant - Pulses low whenever a new command is accepted by the ASIC. Message Error Request - Positive-going edge will cause Message Error Bit in Status Word to be set. Transmit/Receive - The state of this line informs the subsystem whether it is to transmit or receive data The signal is valid while INCMD is low. In Command - Goes low when the RT is servicing a valid command. The subaddress and word count lines are valid while the signal is low. Word Count - These five lines specify the requested number of data words to be received or transmitted. Valid when INCMD is low. Sub Address - These five lines are a label for the data being transferred. Valid when INCMD is low. Current Word Count - These five lines define which data word in the message is currently being transferred. Synchronize - Goes low when a synchronize mode code is being serviced. Vector Word Enable/DataWord Enable - In the RT mode, this signal is provided to enable the contents of the vector word latch (which is situated in the subsystem) onto the ASIC's internal highway. This signal, when in the Bus Controller mode, is used to enable mode code data from the subsystem onto the internal highway. Reset - This line pulses low for 500ns on completion of the servicing of a valid and legal mode command to reset remote terminal. Subsystem Error - By taking this line low, the subsystem can set the Subsystem Flag in the Status Word. Busy - This signal should be driven low if the subsystem is not ready to perform a data transfer to or from the ASIC. Service Request - This signal should be driven low to request an asynchronous transfer and left low until the transfer has taken place. Internal Clock (2 MHz) - This is made available for synchronization use by the subsystem if required. However, many of the outputs to the subsystem are asynchronous. End of Transmission - Goes low if a valid sync plus two data bits do not appear in time to be contiguous with preceding word. Remote Terminal Address Error - This line goes low if an error is detected in the RT address parity of the selected receiver. Any receiver detecting an error in the RT address will turn itself off. Handshake Failure - This line pulses low if the allowable time for DTAK response has been exceeded during the ASIC/subsystem data transfer handshaking. Last Command/Command Word Enable - This line pulses low when servicing a valid and legal mode command to transmit last command. When in RT mode this line must not be used to enable data from the subsystem. This line also pulses low, when in the Bus Control mode, when a command word is required for transmission.
RESET SSERR BUSY SERVREQ INCLK
OUTPUT INPUT INPUT INPUT OUTPUT
EOT RTADER
OUTPUT OUTPUT
HSFAIL
OUTPUT
LSTCMD/CWEN
OUTPUT
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Pin Description (Cont.)
Signal
STATEN/ STATSTB
Direction
OUTPUT
Signal Description
Status Enable/Status Strobe - This line pulses low to enable the status word onto the internal highway for transmission. When in RT mode this line must not be used to enable data from the subsystem. This line also pulses high, when in the Bus Control mode, to strobe received status words into the subsystem. When PASMON is true this line pulses high for Command and Status words. Status Update - When held low, causes TF or SSF to appear in Status Word response to Transmit Status or Transmit Last Command issued immediately after fault occurrence Built In Test Enable/Receive Mode Data Strobe - This line pulses low when servicing a valid and legal mode command to transmit the internal BIT word. This signal is for information only and must not be used to enable data from the subsystem. This line also pulses high when in the Bus Control mode when mode data is received to be passed to the subsystem and when data is passed to the subsystem during PASMON. Data Word Sync - This line goes low if a data word sync and two Manchester biphase bits are valid. CT1990 only. Enable - When held low, enables Bit Decode, Next Status, and Status Update program lines. Command Word Sync - This line goes low if a command word sync and two Manchester biphase bits are valid. CT1990 only. No Data Required - This line goes low if the encoder transmit buffer is full i.e. another word is going to be transmitted. This signal is for information only and must not be used to enable data from the subsystem. Next Status - When held low, causes TF or SSF to appear in very next Status Word after fault occurrence (except for Transmit Status or Transmit Last Command). Passive Monitor - When functioning as a Bus Controller this line acts as a passive monitor select. The active going edge of this line will cause the REQBUS lines to be latched and that bus, now selected will be monitored so long as PASMON remains low. All traffic on the bus will be handed, after validation, to the subsystem via STATSTB for status and commands words, and RMDSTB for data words. Bus Controller Operation Strobe - When functioning as a Bus Controller a low going pulse on this line will initiate the selected bus controller operation on the requested bus, using BCOPA&B and REQBUSA&B. See BITEN/RMDSTB.
STAT UPDATE
INPUT
BITEN/ RMDSTB
OUTPUT
DWSYNC ENABLE CMSYNC NDRQ
OUTPUT INPUT OUTPUT OUTPUT
NEXT STAT
INPUT
PASMON
INPUT
BCOPSTB
INPUT
RMDSTB BCOPA BCOPB REQBUS A INPUT INPUT BI-DIRECTIONAL
Bus Control Operation A - Least significant bit of the bus controller operation select lines. Bus Control Operation B - Most significant bit of the bus controller operation select lines. Request Bus A - This line, when in RT mode, is the least significant bit of the bus request lines which specify the origin of the command, i.e. they are sources. When in BC mode these lines are sinks and specify which bus is to be used for the next command. Request Bus B - Most significant bit of the bus request lines. (See above for description.)
REQBUS B
BI-DIRECTIONAL
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Pin Description (Cont.)
Signal
RT/BC
Direction
INPUT
Signal Description
Remote Terminal/Bus Control - This line when high causes the ASIC to function as a remote terminal. When low the ASIC functions as a bus controller or passive monitor. Dynamic Bus Control Accept - This line should be permanently tied low if a subsystem is able to accept control of the bus if offered. Loop Test Fail - This line goes low if any error in the transmitted waveform is detected or if any parity error in the hardwired RT address is detected. Error - This line latches low if a Manchester or parity error is detected. It is reset by the next CMSYNC (RT mode) and also by RTO in the BC mode. Reply Time Out - This signal will pulse low whenever the reply time for a transmitting terminal has been exceeded. This line is intended for the bus controller use. Transmitter Time Out - This line goes true if the transmitter time out limits are exceeded. Parity Error - This line will pulse low if a parity error is detected by the decoder. Manchester Error - This line will pulse low if a Manchester error is detected by the decoder. Dynamic Bus Control Request - This line will pulse low when the status reply for a mode code Dynamic Bus Control has finished where the accept bit was set. Valid Data - This line will pulse low when a valid data word is received. Driver Inhibit - Selects on-line or off-line testing during automated self test. When high self test is on-line. Must be high when LTEN is high. CT1991 only. Loop Test Enable - Enables automated self-test when low. Normally high. CT1991 only. Loop Test Trigger - When pulsed low while LTEN is low automated self-test is initiated. LTEN pulse width should be 100ns < PW < 5s. CT1991 only.
DBCACC LTFAIL ERROR RTO
INPUT OUTPUT OUTPUT OUTPUT
TXTO PARER MANER DBCREQ
OUTPUT OUTPUT OUTPUT OUTPUT
VALD DRVINH LTEN LTTRIG
OUTPUT INPUT INPUT INPUT
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
NEXT
Controller to RT Transfer RT to Controller Transfer RT to RT Transfer Mode Command Without Data Word Mode Command With Data Word (Transmit)
Receive Command
Data Word
Data Word
....
Data Word Status Word
Data Word
.. ....
Data Word
Status Word
Command Word
NEXT
Transmit Command
..
Status Word
Data Word Data Word
NEXT
Data Word
Command Word
NEXT
Receive Transmit Command Command
..
Status Word
....
Data Word
..
Status Word
Command Word
Mode Command
.. ..
Command Word
NEXT
Mode Command
Status Word
Data Word
Command Word
Mode Command With Data Word (Receive)
NEXT
Mode Command
Data Word
..
Status Word
Command Word
NOTE:
. . = Response Time
= Intermessage Gap
Figure 1 - Typical Message Formats
T/R Bit
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 or 0 1 or 0
Mode Code
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001
Function
Dynamic Bus Control Synchronize Transmit Status Word Initiate Self Test Transmitter Shutdown Override Transmitter Shutdown Inhibit Terminal Flag Bit Override lnhibit Terminal Flag Bit Reset Remote Terminal Reserved
Associated Data Word
No No No No No No No No No No
Broadcast Command Allowed
No Yes No Yes Yes Yes Yes Yes Yes TBD
01111 10000 10001 10010 10011 10100 10101 10110
Reserved Transmit Vector Word Synchronize Transmit Last Command Transmit BlTWord Selected Transmitter Shutdown Override Selected Transmitter Shutdown Reserved
No Yes Yes Yes Yes Yes Yes Yes
TBD No Yes No No Yes Yes TBD
11111
Reserved
Yes
TBD
Figure 2 - Assigned Mode Codes
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
BIT TIMES
COMMAND WORD
BIT WORD DATA WORD
STATUS WORD 1 1
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2
SYNC
SYNC
SYNC 15
3 4
Transmitter Timeout on Bus 3
14
5
Note: T/R - Transmit/Receive P - Parity
Transmitter Timeout on Bus 2
13 5 12
6
5
Transmitter Timeout on Bus 1 Transmitter Timeout on Bus 0
11
7
REMOTE TERMINAL ADDRESS
T/R
10
Message Error
1 9 1
REMOTE TERMINAL ADDRESS
8
Bus 3 Shutdown Bus 2 Shutdown Bus 1 Shutdown Bus 0 Shutdown Broadcast Transmit Data Received
3
9
1
Figure 3 - Word Count
8 1 DATA 7 6 RESERVED
15
10
Instrumentation
11
Service Request
16
12
5
13
SUBADDRESS/MODE
Word Count High Word Count Low
14
5 4
1
15
Broadcast Command Received
1
Illegal Mode Command Mode T/R Bit Wrong Loop Test Failure Subsystem Handshake Failure Transmitter Timeout Flag
3
16
Busy
1
5
2
17
Subsystem Flag
1
18
1
DATA WORD COUNT/MODE CODE
Dynamic Bus Control Acceptance
1
0
19
LSB
Terminal Flag
1
1
1
P
P
P
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Parity
20
One Bit Time
1MHz Clock
(+) (0) -
NRZ Data
(+) (0) -
(+) -
Manchester
=
Bi-Phase
(0) (-) -
Figure 4 - Data Encoding
CT1990/1
+ 1553B BUS "A" TX DATA OUT RX DATA IN ACT4453 Driver/ Receiver 0 XFR0 TX DATA OUT RX DATA IN TX DATA RX DATA OUT RX DATA OUT TX DATA IN TX DATA IN TX DATA RX DATA 0 RX DATA 0
TX INHIBIT "0"
+ 1553B BUS "B"
TX DATA OUT RX DATA IN ACT4453 Driver/ Receiver 1 XFR1 TX DATA OUT RX DATA IN
RX DATA OUT RX DATA OUT TX DATA IN TX DATA IN
RX DATA 1 RX DATA 1
TX INHIBIT "0"
TX INHIBIT "1"
TX INHIBIT "1"
Figure 5 - Example of an Interface between the CT1990/1 and Driver/Receiver
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PDIN NBGT INCMD DTRQ IUSTB H/L GBR EOT
Figure 6 - Transfer of three Data Words from RT 03 to BC
PDIN NBGT INCMD DTRQ IUSTB H/L GBR EOT
Figure 7 - Transfer of two Data Words from BC to RT 03
PDIN NBGT INCMD DTRQ IUSTB H/L RESET EOT
Figure 8 - Mode Command Reset Remote Terminal
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
PDIN NBGT INCMD DTRQ IUSTB H/L GBR EOT
Figure 9 - RT to RT transfer of four data words (This RT sending the data)
PDIN NBGT INCMD DTRQ IUSTB H/L GBR EOT
Figure 10 - RT to RT transfer of four data words (This RT receiving the data)
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
DTRQ
Subsystem Reply Time < 13.5s
DTAK
Don't Care
250 nsec
250 nsec 500 nsec
IUSTB
H/L
CWC0-CWC4
Valid
Incremented
Enable High Byte of TX Data on Internal Highway
Enable Low Byte of TX Data on Internal Highway
Figure 11 - Handshaking for Tx Data Transfers
DTRQ
Subsystem Reply Time < 1.5s
DTAK
Don't Care
250 nsec
250 nsec 500 nsec
IUSTB
H/L
Internal Highway
High Byte Valid
Low Byte Valid
CWC0-CWC4
Valid
Incremented
Figure 12 - Handshaking for Rx Data Transfers
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
NBGT
1.0s Minimum
TX/RX
Previous command value
Valid
SA4-SA0
Previous command value
Valid
WC4-WC0
Previous command value
Valid
CWC4-CWC0
INCMD
INCLK
BUSY Latch here
Figure 13 - New Command Initialization
NBGT
INCMD
VECTEN
1.5s approx.
H/L
} }
Enable high byte of vector word onto internal highway Enable low byte of vector word onto internal highway
Figure 14 - Transmit Vector Word Command
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
1 00 1 NBGT 0 1 INCMD 0 1 SYNC 0 1 ILUSTB 0 1 EOT 0 1 WC4 0 1 H/L 0 PDIN
Figure 15 - Synchronize (with data) mode command
1 00 1 NBGT 0 1 INCMD 0 1 SYNC 0 1 IUSTB 0 1 EOT 0 1 WC0 0 PDIN
Figure 16 - Synchronize (no data) mode command
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
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BCOPSTB
PDIN
NDRG CWEN
DTRG
H/L
IUSTB
22
C/D
EOT
VALC
VALD STATSTB
RTO
INCMD
GBR
NBGT
SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Figure 17 - BUS Controller sending command to RT 10001 to transmit two data words
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BCOPSTB
PDIN
NDRG CWEN
DTRG
H/L
IUSTB
C/D
23
EOT
VALC
VALD STATSTB
RTO
INCMD
GBR
NBGT
SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Figure 18 - BUS Controller sending command to RT 10001 to receive two data words
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BCOPSTB BCOPA BCOPB NDRG PDIN CWEN
24
H/L IUSTB C/D TxSTB NBGT INCMD VALC VALD STATSTB DTRG CWC0 CWC1 TREQ GBR EOT TXEN PDOUT RTO IH715 IH614 IH613
IH412 IH311 IH210 IH19 IH06
SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Figure 19 - BUS Controller commanding RT 10001 to transmit two data words at RT 00001
BCOPSTB BCOPA BCOPB PDIN TXSTB CWEN H/L STATSTB
Figure 20 - BUS Controller sending mode command transmit status word mode code 00010
BCOPSTB BCOPA BCOPB PDIN NDRQ CWEN DWEN H/L
Figure 21 - BUS Controller sending mode command synchronize mode code 10001
BCOPSTB BCOPA BCOPB PDIN DWEN H/L STATSTB RMDSTB
Figure 22 - BUS Controller sending mode command transmit vector mode code 10000
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Pin Out Description - CT1990
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Function
BIT DECODE CWC0 (LSB) SA4 (MSB) SA3 SA2 CWC4 (MSB) CWC3 CWC2 CWC1 GBR H/L STATEN/STATSTB EOT SA1 SA0 (LSB) INCMD TX/RX DTRQ VECTEN/DWEN NBGT SYNC INCLK IUSTB NEXT STAT DTAK BCOPA BCOPSTB BCOPB PASMON NDRQ
Pin #
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Function
REQBUSB REQBUSA COMMON & CASE ENABLE STAT UPDATE MEREQ IH 08 (LSB) IH19 IH210 IH311 IH412 IH513 IH614 IH715 (MSB) NC NC RTADPAR RTAD0 (LSB) RTAD1 RTAD2 RTAD3 RTAD4 (MSB) CMSYNC DWSYNC BCSTEN 0 RX DATA 0 RX DATA 0 BCSTEN 1 RTO 6 MCK
Pin #
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Function
ERROR LTFAIL MANER PARER VALD RTADER RX DATA 1 RX DATA 1 +5 VIN TX INHIBIT 1 TX INHIBIT 0 TX DATA TX DATA SERVREQ TXTO DBCACC RESET RT/BC DBCREQ HSFAIL LSTCMD/CWEN BITEN/RMDSTB BUSY WC4 (MSB) WC3 WC0 (LSB) SSERR WC2 WC1 NC
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Pin Out Description - CT1991
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Function
BIT DECODE CWC0 (LSB) SA4 (MSB) SA3 SA2 CWC4 (MSB) CWC3 CWC2 CWC1 GBR H/L STATEN/STATSTB EOT SA1 SA0 (LSB) INCMD TX/RX DTRQ VECTEN/DWEN NBGT SYNC INCLK IUSTB NEXT STAT DTAK BCOPA BCOPSTB BCOPB PASMON NDRQ
Pin #
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Function
REQBUSB REQBUSA COMMON & CASE ENABLE STAT UPDATE MEREQ IH 08 (LSB) IH19 IH210 IH311 IH412 IH513 IH614 IH715 (MSB) NC NC RTADPAR RTAD0 (LSB) RTAD1 RTAD2 RTAD3 RTAD4 (MSB) LTEN LTTRIG BCSTEN 0/1 RX DATA 0 RX DATA 0 DRVINH RTO 6 MCK
Pin #
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Function
ERROR LTFAIL MANER PARER VALD RTADER RX DATA 1 RX DATA 1 +5 VIN TX INHIBIT 1 TX INHIBIT 0 TX DATA TX DATA SERVREQ TXTO DBCACC RESET RT/BC DBCREQ HSFAIL LSTCMD/CWEN BITEN/RMDSTB BUSY WC4 (MSB) WC3 WC0 (LSB) SSERR WC2 WC1 NC
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
Ceramic CoFired Plug In Package Outline
2.400 MAX
.225 MAX
1.600 MAX Lead 1 & ESD Designator
.200 MIN .135 .090
Pin 1 Pin 3
2.200
.050 TYP Pin 43 Pin 45 Pin 44 Pin 2 .018 DIA TYP
1.300 1.100
Pin 89 Pin 47 Pin 90 Pin 88 .100 TYP Pin 48 Pin 46
.135
2.100
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
CT1990-1-20 CT1991-1-20
DESC Part Number
5962-9477501 Pending
Package
1.6" x 2.4" Ceramic Plug In 1.6" x 2.4" Ceramic Plug In
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830
Specifications subject to change without notice.
Aeroflex Circuit Technology
Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800)THE-1553
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SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700

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