View V53C8258H_145485.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOSEL VITELIC
V53C8258H HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM
V53C8258H PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
35
35 ns 18 ns 14 ns 70 ns
40
40 ns 20 ns 15 ns 75 ns
45
45 ns 22 ns 17 ns 80 ns
50
50 ns 24 ns 19 ns 90 ns
Features
s 256K x 8-bit organization s EDO Page Mode for a sustained data rate of 71 MHz s RAS access time: 35, 40, 45, 50 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability s Refresh Interval: 512 cycles/8 ms s Available in 24 pin 300 mil Plastic DIP, 26/24 pin 300 mil SOJ and 28-pin 300 mil TSOP-I packages s Single 5V10% Power Supply s TTL Interface
Description
The V53C8258H is a high speed 262,144 x 8 bit CMOS dynamic random access memory. The V53C8258H offers a combination of features: Page Mode with Extended Data Output for high data bandwidth, and Low CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Page Mode with Extended Data Output operation allows random access of up to 512 (x8) bits within a row with cycle times as fast as 14 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relaxing many critical system timing requirements. The V53C8258H is ideally suited for graphics, digital signal processing and high-performance computing systems.
Device Usage Chart
Operating Temperature Range 0C to 70 C Package Outline P K T 35 Access Time (ns) 40 45 50 Power Std. Temperature Mark Blank
*
*
*
*
*
1
*
*
*
V53C8258H Rev. 1.4 February 1997
MOSEL VITELIC
V 5 3 C 8 2 5 8 H
V53C8258H
FAMILY
DEVICE P (PLASTIC DIP) K (SOJ) T (TSOP-I)
PKG
Description
Plastic DIP SOJ TSOP-I
Pkg.
P K T
Pin Count
24 26/24 28
SPEED ( t RAC)
TEMP. PWR. BLANK (0C to 70C) BLANK (NORMAL) 35ns 40ns 45ns 50ns
8258H-01
26/24 Lead SOJ PIN CONFIGURATION Top View
VSS I/O1 I/O2 I/O3 I/O4 WE RAS A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 16 16 15 14 VSS I/O8 I/O7 I/O6 I/O5 CAS OE A8 A7 A6 A5 A4
24 Lead Plastic DIP PIN CONFIGURATION Top View
VSS I/O1 I/O2 I/O3 I/O4 WE RAS A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VSS I/O8 I/O7 I/O6 I/O5 CAS OE A8 A7 A6 A5 A4
300 mil
8258H-02
28 Lead TSOP-I PIN CONFIGURATION Top View
CAS I/O5 I/O6 I/O7 I/O8 VSS VSS NC I/O1 I/O2 I/O3 I/O4 NC WE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
8258H-04
Pin Names
A0-A8 RAS
OE A8 A7 A6 A5 A4 NC VCC NC A3 A2 A1 A0 RAS
Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect
CAS WE OE I/O1-I/O8 VCC VSS NC
Absolute Maximum Ratings*
Ambient Temperature Under Bias ............................. -10C to +80C Storage Temperature (plastic) ... -55C to +125C Voltage Relative to VSS .................... -1.0 V to +7.0 V Data Output Current .................................... 50 mA Power Dissipation ........................................ 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
Capacitance*
TA = 25C, VCC = 5 V 10%, VSS = 0 V Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, OE, WE Data Input/Output Typ. Max. 3 4 5 4 5 7 Unit pF pF pF
* Note: Capacitance is sampled and not 100% tested
V53C8258H Rev. 1.4 February 1997
2
300 mil
8258H-03
MOSEL VITELIC
Block Diagram
256K x 8
OE WE CAS RAS
V53C8258H
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS
DATA I/O BUS COLUMN DECODERS
Y0-Y8
I/O 1 I/O2 I/O3
I/O BUFFER
SENSE AMPLIFIERS REFRESH COUNTER
512 x 8 9 A0 A1 * * * A7 A8
I/O4 I/O 5 I/O6 I/O7 I/O8
ADDRESS BUFFERS AND PREDECODERS
X0-X8
ROW DECODERS
512
MEMORY ARRAY
8258H-05
V53C8258H Rev. 1.4 February 1997
3
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified. Symbol Parameter V53C8258H Access Time Min. Typ. Max..
-10 10
V53C8258H
Unit
A
Test Conditions
VSS VIN VCC
Notes
ILI
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) 35
ILO
-10
10
A
VSS VOUT VCC RAS, CAS at VIH
160 150 145 135 RAS, CAS at VIH other inputs VSS mA tRC = tRC (min.) 1, 2
ICC1
VCC Supply Current, Operating
40 45 50
ICC2
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 35 40 45 50
2 160 150 145 135 95 90 85 80 2.0
mA
ICC3
mA
tRC = tRC (min.)
2
ICC4
VCC Supply Current, EDO Page Mode Operation
35 40 45 50
mA
Minimum cycle
1, 2
ICC5
VCC Supply Current, Standby, Output Enabled VCC Supply Current, CMOS Standby
mA
RAS=VIH, CAS=VIL other inputs VSS RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS
1
ICC6
1.0
mA
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1 2.0
0.8 VCC+1 0.4
V V V V IOL = 4.2 mA IOH = -5 mA
3 3
2.4
V53C8258H Rev. 1.4 February 1997
4
MOSEL VITELIC
AC Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V
JEDEC Symbol tRL1RH1 tRL2RL2 tRH2RL2 tRL1CH1 tCL1CH1 tRL1CL1 tWH2CL2 tAVRL2 tRL1AX tAVCL2 tCL1AX 35 Symbol tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH Parameter RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS (EDO) Access Time from RAS Access Time from Column Address CAS to Low-Z Output Output buffer turn-off delay time Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time 0 0 28 6 40 45 50
V53C8258H
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Min. Max. Min. Max. Min. Max. Min. Max. Unit 35 70 25 35 7 16 0 0 6 0 4 12 5 0 23 75K 40 75 25 40 8 17 0 0 7 0 5 12 5 0 28 75K 45 80 25 45 9 18 0 0 8 0 6 13 5 0 32 75K 50 90 30 50 9 19 0 0 9 0 7 14 5 0 36 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
4
tCL1RH1(R) tRSH (R) tCH2RL2 tCH2WX tCRP tRCH
5
15
tRH2WX
tRRH
0
0
0
0
ns
5
16
tOEL1RH2
tROH
8
8
9
10
ns
17 18 19 20
tGL1QV tCL1QV tRL1QV tAVQV
tOAC tCAC tRAC tCAA
12 12 35 18
12 12 40 20
13 13 45 22
14 14 50 24
ns ns ns ns 6, 7 6, 8, 9 6, 7, 10
21 22 23
tCL1QX tCH2QZ tRL1AX
tLZ tHZ tAR
0 0 30 6
0 0 35 7
0 0 40 8
ns ns ns
16 16
24
tRL1AV
tRAD
11
17
12
20
13
23
14
26
ns
11
25
tCL1RH1(W) tRSH (W)
12
12
13
14
ns
26
tWL1CH1
tCWL
12
12
13
14
ns
V53C8258H Rev. 1.4 February 1997
5
MOSEL VITELIC
AC Characteristics (Cont'd)
JEDEC Symbol tWL1CL2 tCL1WH1 tWL1WH1 tRL1WH1 35 Symbol tWCS tWCH tWP tWCR Parameter Write Command Setup Time Write Command Hold Time Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in Read-Modify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay EDO Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh EDO Page Mode ReadModify-Write Cycle Time 28 40 45 50
V53C8258H
# 27 28 29 30
Min. Max. Min. Max. Min. Max. Min. Max. Unit 0 5 5 28 0 5 5 30 0 6 6 35 0 7 7 40 ns ns ns ns
Notes 12, 13
31
tWL1RH1
tRWL
12
12
13
14
ns
32 33 34 35 36
tDVWL2 tWL1DX tWL1GL2 tGH2DX tRL2RL2 (RMW)
tDS tDH tWOH tOED tRWC
0 4 5 5 105
0 5 6 6 110
0 6 7 7 115
0 7 8 8 130
ns ns ns ns ns
14 14 14 14
37
tRL1RH1 (RMW)
tRRW
70
75
80
87
ns
38 39
tCL1WL2 tRL1WL2
tCWD tRWD
28 54
30 58
32 62
34 68
ns ns
12 12
40 41 42
tCL1CH1 tAVWL2 tCL2CL2
tCRW tAWD tPC
46 35 14
48 38 15
50 41 17
52 42 19
ns ns ns 12
43 44
tCH2CL2 tAVRH1
tCP tCAR
4 18
5 20
6 22
7 24
ns ns
45
tCH2QV
tCAP
20
22
24
27
ns
7
46
tRL1DX
tDHR
30
35
40
ns
47
tCL1RL2
tCSR
10
10
10
10
ns
48 49
tRH2CL2 tRL1CH1
tRPC tCHR
0 8
0 8
0 10
0 12
ns ns
50
tCL2CL2 (RMW)
tPCM
58
60
65
70
ns
V53C8258H Rev. 1.4 February 1997
6
MOSEL VITELIC
AC Characteristics (Cont'd)
JEDEC Symbol tT 35 Symbol tT tREF Parameter Transition Time (Rise and Fall) Refresh Interval (512 Cycles) Output Hold After CAS Low 5 40 45 50
V53C8258H
# 57 58
Min. Max. Min. Max. Min. Max. Min. Max. Unit 3 50 8 3 50 8 3 50 8 3 50 8 ns ms
Notes 15
59
tCOH
5
5
5
ns
V53C8258H Rev. 1.4 February 1997
7
MOSEL VITELIC
Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9.
V53C8258H
ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in EDO Page Mode. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. Either tRRH or tRCH must be satisified for a Read Cycle to occur. Measured with a load equivalent to one TTL input and 50 pF. Access time is determined by the longest of tCAA, tCAC and tCAP. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.).
10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns . 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C8258H Rev. 1.4 February 1997
8
MOSEL VITELIC
Waveforms of Read Cycle
VIH VIL t CRP (13) CAS VIH VIL t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RAH (9) t ASC (10) t CAH (11) t RCD (6) t CSH (4) t RSH (R)(12) t CAS (5) t AR (23) t RAS (1) t RC (2) t RP (3)
V53C8258H
RAS
t CRP (13)
COLUMN ADDRESS t CAR (44) t RCH (14) t RRH (15)
t RCS (7) WB/WE VIH VIL
t ROH (16) t CAA (20) t HZ (22) t OAC (17) t CAC (18) t HZ (22) VALID DATA-OUT t LZ (21)
2736 05
OE
VIH VIL t RAC (19)
t HZ (22)
I/O
VOH VOL
Waveforms of Early Write Cycle
V IH V IL t CRP (13) CAS V IH V IL t RAH (9) t CAR (44) t CAH (11) t RCD (6) t CSH (4) t RSH (W)(25) t CAS (5) t CRP (13) t AR (23) t RAS (1) t RC (2) t RP (3)
RAS
t ASR (8) ADDRESS V IH V IL ROW ADDRESS
t ASC (10)
COLUMN ADDRESS t WCH (28)
t RAD (24) t WSR WB/WE V IH V IL t WCR (30) V IH V IL t DS (32) I/O V IH V IL t DHR (46) t RWH
t WP (29) t WCS (27)
t CWL (26)
t RWL (31)
OE
t DH (33) HIGH-Z
2736 06
VALID DATA-IN
Don't Care
Undefined
V53C8258H Rev. 1.4 February 1997
9
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RAS (1) t RC (2) t RP (3)
V53C8258H
RAS
V IH V IL t CRP (13)
t AR (23)
t RCD (6)
t CSH (4)
CAS
V IH V IL t RAD (24) t RAH (9)
t RSH (W)(12) t CAS (5)
t CRP (13)
t CAR (44) t CAH (11) t ASC (10)
t ASR (8) ADDRESS V IH V IL
ROW ADDRESS
COLUMN ADDRESS t CWL (26) t RWL (31)
t WP (29) WE V IH V IL
t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN
2736 07
I/O
Waveforms of Read-Modify-Write Cycle
t AR (23) tRRW (37) t RWC (36) t RP (3)
RAS
VIH VIL t CRP (13)
t RCD (6)
t CSH (4)
CAS
VIH VIL t RAH (9) t ASR (8) VIH VIL ROW ADDRESS t RAD (24) VIH VIL t WSR t RWH t CAA (20) t OAC (17) t t ASC (10) COLUMN ADDRESS
t RSH (W)(25) t CRW (40)
t CRP (13)
CAH (11)
ADDRESS
t RWD (39) t RCS (17)
t AWD (41) t CWD (38)
t RWL (31)
t CWL (26)
t WP (29)
WE
OE
VIH VIL t OED (35) t CAC (18) t RAC (19) t HZ (22) VALID DATA-OUT t LZ (21) t DS (32) VALID DATA-IN
2736 08
t DH (33)
I/O
VIH VOH VIL VOL
Don't Care
Undefined
V53C8258H Rev. 1.4 February 1997
10
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
RAS V IH V IL t AR (23) t RCD (6) t CRP (13) CAS V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t RAC (19) t CAC (18) t LZ (21) t CAC (18) t CAR (44) t CAH (11) COLUMN ADDRESS t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t CRP (13) t CAS (5) t RAS (1) t
RP (3)
V53C8258H
t CAS (5)
t ASR (8) ADDRESS V IH V IL
t ASC (10) ROW ADDRESS t RCS (7)
COLUMN ADDRESS
t RCH (14)
WE
V IH V IL t CAP (45) t CAA (20) t OAC (17) t RRH (15)
t CAC (18)
t HZ (22) t HZ (22) t HZ (22) VALID DATA OUT
t COH I/O V OH V OL VALID DATA OUT VALID DATA OUT
t HZ (22)
t LZ
2736 09
Waveforms of EDO Page Mode Write Cycle
t AR (23) RAS V IH V IL t CRP (13) t RCD (6) CAS V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL t WSR VIH V IL t DS (32) I/O V IH V IL
VALID DATA IN ROW ADD COLUMN ADDRESS
t RP (3) t RAS (1)
t PC (42) t CP (43) t CAS (5)
t RSH (W)(25) t CAS (5) t CAS (5)
t CRP (13)
t CSH (4) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
t CWL (26)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28) t WP (29)
t WCS (27)
t CWL (26) t RWL (31) t WCH (28) t WP (29)
t RWH
OE
t DH (33)
t DS (32)
t DH (33)
VALID DATA IN
t DS (32)
t DH (33)
VALID DATA IN
OPEN
OPEN 2736 10
Don't Care
Undefined
V53C8258H Rev. 1.4 February 1997
11
MOSEL VITELIC
Waveforms of EDO Page Mode Read-Write Cycle
RAS VIH V
IL
V53C8258H
t RAS (1)
t RCD (6)
t CSH (4) t PCM (50) t CAS (5)
t RP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CP (43) t CAS (5)
V CAS V
IH IL
t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10)
COLUMN ADDRESS
t CAH (11)
COLUMN ADDRESS
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
V ADDRESS V
IH IL
ROW ADD
t RWD (39) t RCS (7) V WE V
IH IL
t CWD (38)
t CWL (26)
t CWD (38) t CWL (26)
t CWD (38) t RWL (31) t CWL (26)
t CAA (20) t OAC (17) V OE V
IH IL
t AWD (41)
t AWD (41) t WP (29) t OAC (17)
t AWD (41) t OAC (17) t WP (29) t WP (29)
t OED (35) t CAC (18) t RAC (19)
t CAA (20)
t CAP (43)
t OED (35) t CAC (18) t DH (33)
t CAP (43) t CAA (20)
t HZ (22)
t HZ (22)
t DS (32) I/O V I/OH V I/OL t LZ (21)
OUT IN OUT
t DH (33) t DS (32)
t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32)
OUT IN 2736 11
IN
t LZ
t LZ
Waveforms of RAS-Only Refresh Cycle
t RC (2) V IH V IL t CRP (13) CAS V IH V IL t ASR (8) ADDRESS V IH V IL NOTE: ROW ADD
2736 12
t RAS (1)
t RP (3)
RAS
t RAH (9)
WE, OE = Don't care
Don't Care
Undefined
V53C8258H Rev. 1.4 February 1997
12
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1) RAS V IH V IL t CSR (47) CAS V IH V IL V IH V IL READ CYCLE V IH V IL t ROH (16) t OAC (17) OE V IH V IL t LZ (21) I/O V IH V IL WRITE CYCLE t WSR WB/WE V IH V IL V IH V IL t I/O V IH V IL
DS (32)
V53C8258H
t RP (3)
t CHR (49)
t CP (43)
t RSH (W)(25) t CAS (5)
ADDRESS
t RCS (7)
t RRH (15) t RCH (14)
WE
t HZ (22) t HZ (22) DOUT t RWL (31) t CWL (26) t HZ (22)
t RWH
t WCS (27)
t WCH (28)
BE/OE
t DH (33) D IN
2736 13
Waveforms of CAS-before-RAS Refresh Cycle
t RP (3) RAS V IH V IL t CP (43) V IH V IL t HZ (22) I/O V OH V OL NOTE: WE, OE, A 0 -A 8 = Don't care
2736 14
t RC (2) t RAS (1) t RP (3)
t RPC (48) t CSR (47)
t CHR (49)
CAS
Don't Care
Undefined
V53C8258H Rev. 1.4 February 1997
13
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t CAA (20) V IH V IL t CAC (18) t LZ (21) t RAC (19) I/O V OH V OL VALID DATA t HZ (22) t OAC (17)
ROW ADD
V53C8258H
t RAS (1) t AR (23)
tRP (3)
t RC (2) t RAS (1)
t RP (3)
RAS
t RSH (R)(12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t RCS (7) WB/WE
t RRH (15)
t HZ (22)
OE
t HZ (22)
2736 15
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t WSR V IH OE V IL t DS (32) I/O V IH V IL t MS t MH t DHR (46) t DH (33)
VALID DATA-IN 2736 16 ROW ADD
t RAS (1) t AR (23)
t RP (3)
t RC (2) t RAS (1)
t RP (3)
RAS
t RSH (12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t WCS (27) WE
t WCH (28)
t RWH
Don't Care
Undefined
V53C8258H Rev. 1.4 February 1997
14
MOSEL VITELIC
Functional Description
The V53C8258H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C8258H reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
V53C8258H
controlled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Extended Data Output Page Mode
EDO Page operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer. During EDO operation, Read, Write, Read-Modify-Write or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Hyper Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. EDO provides a sustained data rate of 71 MHz for applications that require high bandwidth such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 512 Data Rate = tRC + 511 x tPC
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAS-
V53C8258H Rev. 1.4 February 1997
15
MOSEL VITELIC
Data Output Operation
The V53C8258H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied.
V53C8258H
Table 1. V53C8258H Data Output
Operation for Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles EDO Read Cycle EDO Write Cycle (Early Write) EDO Read-ModifyWrite Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
I/O State
Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C8258H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
V53C8258H Rev. 1.4 February 1997
16
MOSEL VITELIC
Package Outlines 24-pin 300 mil PDIP
0.300/0.330 1.310 Max. 0.005/0.050
V53C8258H
.180 Max.
0.250/0.300
0.110/0.140 .100 Typ, 0.018./0.024 0.048/0.065 0.320/0.390
.008/.013
2736 19
26/24-pin 300 mil SOJ
0.332/0.342 0.296/0.304 0.665/0.698 0.125/0.135
0.082/0.093 0.018 Typ. 0.025 Min. 0.255/0.275 2736 20
0.028 Typ.
0.05 Typ.
28-pin TSOP-I
Units in inches
.035 .043 .039 DIA. .520 .535 .461 .469 0.10 .311 .319 .047
Detail "A"
0.10 (.004) .002 .006 .079 DIA. x .000 Deep .0004 Fixed Pin (1 Plcs.)
.035 .043 .55
.055 .063
0.25
Top View
0.10 D
See Detail "B"
.055 .063 Bottom View .055 .063 .008 .20 Gage Plane 0.25 BSC .020 .028 Detail "B" .012 MAX
.037 .041
See Detail "A" D .007 .011 0 6
With Plating
.007 .009
.004 .008 Base Metal .004 .006 Section "D-D"
Detail "A"
V53C8258H Rev. 1.4 February 1997
17
MOSEL VITELIC
V53C8258H
2/97 (c) Copyright 1997, Mosel-Vitelic Corporation Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
3910 MOSEL VITELIC1997 N. First Street, San Jose, CA 95134-1501 V53C8258H Rev. 1.4 February 18
Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

▲Up To Search▲

Price & Availability of V53C8258H

	To Download V53C8258H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .