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SM1126 Series
NIPPON PRECISION CIRCUITS INC.
Melody IC with Built-in SRAM
OVERVIEW
The SM1126 Series are melody ICs for use in mobile telecommunications equipment. A maximum of 15 melodies can be stored in programmable ROM and one in built-in read/write SRAM.
PINOUT
(Top View)
8-pin VSOP
FEATURES
s s
OSC SIO SC ST
1 2 3 4
8 7
VSS VDD MTO TEST
s s
s
s
s s s
2.0 to 3.6 V supply voltage Maximum of 16 melody selections (15 in ROM + 1 in SRAM) Level hold playback mode External reference clock input versions and builtin RC oscillator versions available, set by masterslice option (RC oscillator versions require an external resistor and capacitor). Selectable clock frequencies (fixed for all melodies) * External clock input versions (6 frequencies) - 32.768 kHz system: 32.768, 65.536 and 131.072 kHz - 38.4 kHz system: 38.4, 76.8 and 153.6 kHz * Built-in RC oscillator versions (1 frequency) - 131.072 kHz 2-pin serial data melody selection and 1-pin melody playback control Parity check function Delivery pattern alarm Power save function * External clock input versions Clock gating in non-play modes * Built-in RC oscillator versions Oscillator stopped in non-play modes
1126xx
6 5
PACKAGE DIMENSIONS
(Unit: mm)
4.4 0.2
6.4 0.3
0.575 TYP 3.1 0.3
1.15 0.05
0.15- 0.05
+ 0.1
0.10
D e vice SM1126xxV
P ackag e 8-pin VSOP
0.1 0.05
ORDERING INFORMATION
0.65
0.22 0.1
+ 0.12 M
NIPPON PRECISION CIRCUITS--1
0.5 0.2
SM1126 Series
BLOCK DIAGRAM
OSC
OSC
Master slice SW1
Frequency Multiplier
Master slice SW2
VSS VDD
Gate
Divider
Divider
Scale Counter Scale ROM
MTO
SIO SC ST Control Circuit Main RAM
Main ROM
MultiPlexer
TEST
(Pull-down resistance built-in)
Tempo Latch
Tempo Counter
Rhythm Counter
Address Counter Start Address Latch
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 Name OSC SIO SC ST TEST MTO VDD VSS Function Built-in RC oscillator option: External resistor and capacitor connection pins External clock input option: External reference clock input (gate circuit built-in) Playback control serial interface data input. During parity check, the G flag is output while ST is HIGH. Playback control serial interface clock input Play mode: Playback start/stop control signal input Write mode: Serial interface data write control signal input Test input. Pull-down resistor built-in. Leave open or connect to VSS. Playback melody signal output Supply Ground
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SM1126 Series
SPECIFICATIONS
Absolute Maximum Ratings
P arameter Supply voltage range Input voltage range Power dissipation Storage temperature range Soldering temperature Soldering time Symbol V DD - V SS V IN PD Tstg Tsld tsld Condition Rating -0.3 to 5.0 V SS - 0.2 to V DD + 0.2 100 -40 to 125 255 10 Unit V V mW C C s
Recommended Operating Conditions
VSS = 0 V
P arameter Supply voltage Operating temperature Symbol V DD Topr Condition Rating 2.0 to 3.6 -20 to 70 Unit V C
DC Characteristics
Ta = -20 to 70 C, VSS = 0 V, VDD = 2.0 to 3.6 V
P arameter Supply voltage Current consumption (1) Current consumption (2) Current consumption (3) Symbol V DD IDD1 IDD2 IDD3 V IH Input voltage V IL Non-playback mode, Ta = 25C External clock input option: Playback mode, MTO pin open Built-in RC oscillator option: Playback mode, MTO pin open External clock input option: ST, SIO, SC and OSC pins, Built-in RC oscillator option: ST, SIO and SC pins V IH = V DD, Ta = 25C External clock input option: ST, SIO, SC and OSC pins, Built-in RC oscillator option: ST, SIO and SC pins V IL = 0 V, Ta = 25C External clock input option: ST, SIO, SC and OSC pins, Built-in RC oscillator option: ST, SIO and SC pins TEST pin, V IH = V DD TEST pin SIO pin, IOH1 = 1 mA, V DD = 2.4 V SIO pin, IOL1 = 1 mA, V DD = 2.4 V MTO pin, IOH2 = 1 mA MTO pin, IOL2 = 1 mA Built-in RC oscillator option: NPC test board measurement, V DD = 3.0 V, RO = 82 k, C O = 130 pF Built-in RC oscillator option Built-in RC oscillator option Built-in RC oscillator option Condition Rating min 2.0 - - - V DD - 0.2 V SS typ 3.0 - 25 215 - - max 3.6 0.5 200 600 V DD V SS + 0.2 Unit V A A A V V
IIH1 Input current (1) IIL1 Input current (2) Start voltage Output voltage (1) IIH2 VOPN VOH1 VOL1 VOH2 VOL2 fOSC f/f VDOB V DOS
-
-
0.5
A
-
-
0.5
A
- - V DD - 0.4 V SS V DD - 0.4 V SS 117.965 - - -
- - - - - - 131.072 0.2 - -
200 0.1 V DD V SS + 0.4 V DD V SS + 0.4 144.179 - 1.6 1.6
A V V V V V kHz %/0.1V V V
Output voltage (2)
Oscillator frequency Frequency stability Oscillator start voltage Oscillator stop voltage
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SM1126 Series
AC Characteristics
Ta = -20 to 70 C, VSS = 0 V, VDD = 2.0 to 3.6 V
Rating P arameter OSC pulse cycle OSC HIGH-level pulsewidth OSC LOW-level pulsewidth OSC pulse rise time OSC pulse fall time SC pulsewidth SC HIGH-level pulsewidth SC LOW-level pulsewidth SC pulse rise time SC pulse fall time SIO-SC setup time SIO-SC hold time ST input write pulsewidth ST input write pulse rise time ST input write pulse fall time SIO output enable delay SIO output disable delay Symbol tOSC tOWH tOWL tOr tOf tSC tSWH tSWL tSr tSf tDS tDH tWP tWr tWf tOE tOD "SIO parity check G-flag output data" timing "SC-SIO-ST serial input pulse" timing "SC input pulse" timing "OSC input pulse (external clock input version)" timing Condition min 4.0 2.0 2.0 - - 4.0 2.0 2.0 - - 2.0 2.0 2.0 - - - - typ - - - - - - - - - - - - - - - - - max - - - 200 200 - - - 200 200 - - - 200 200 600 600 s s s ns ns s s s ns ns s s s ns ns ns ns Unit
OSC input pulse (external clock input version)
0.9VDD 0.1VDD
t OWH t OSC
t OWL
VDD 0.5VDD VSS t Or
tOf
SC input pulse
0.9VDD 0.1VDD
t SWH t SC
t OWL SWL
VDD 0.5VDD VSS t Sr
t Sf
NIPPON PRECISION CIRCUITS--4
SM1126 Series SC-SIO-ST serial input pulse
VDD 0.5VDD VSS t DS
SIO
SC
t DH VDD 0.5VDD VSS t WP
0.9VDD 0.1VDD
ST
VDD 0.5VDD VSS t Wf
t Wr
ST must be set to LOW when switching ST
SIO parity check G-flag output data
SC
VDD 0.5VDD VSS
INPUT MODE OUTPUT MODE (G FLAG OUTPUT) 0.1VDD 0.9VDD INPUT MODE
SIO
t OE
ST 0.9VDD 0.1VDD
t OD
VDD 0.5VDD VSS VDD 0.5VDD VSS
ST must be set to LOW when switching ST
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SM1126 Series
FUNCTIONAL DESCRIPTION
Control Functions
External reference clock SM1126 Series devices are available in external clock input versions and built-in RC oscillator versions, set by master-slice option. In the case of the built-in RC oscillator option, an external resistor and capacitor is required for the oscillator function. SM1126 Series devices can operate at 6 selectable reference clock frequencies. All melodies playback at the fixed speed set by the reference clock frequency. External clock input versions operate at one of 6 selectable clock frequencies, as shown in table 1. Built-in RC oscillator versions operate at only one oscillator frequencies--131.072 kHz.
Table 1. Reference clock frequencies (external clock)
F r e q u e n cy system 32.768 kHz 38.4 kHz Selectable frequencies 32.768 kHz 38.4 kHz 65.536 kHz 76.8 kHz 131.072 kHz 153.6 kHz
Power-save function In external clock input versions, the external reference clock input is used during playback mode only and is otherwise ignored. If a clock signal is input when not in playback mode (when ST is LOW), the gate circuit switches to cutoff the external reference clock signal from entering the device, preventing unwanted current flow. In built-in RC oscillator versions, the oscillator is stopped when not in playback mode (when ST is LOW), preventing unwanted current flow.
ST OSC
Figure 1. External clock input version: OSC input during playback mode only
ST OSC
Figure 2. External clock input version: Continuous OSC input
ST OSC CR Oscillation
Figure 3. Built-in RC oscillator version
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SM1126 Series Serial inputs Serial data is input on SIO in sync with the SC clock in 8-bit units when ST is LOW. Data is not accepted when ST is HIGH. When ST goes HIGH, the 8-bit data is latched. Note that if the input data exceeds 8 bits in length, the most recent 8 bits are used and any preceding bits are ignored. Data is in MSB first format. Input data is interpreted as a command or as a data word (in write mode), depending on the current operating mode of the device. There are 3 types of commands:
s s s
Playback start command SRAM write command End-of-write command
The SRAM write command is used to invoke write mode operation, and end-of-write command is used to return to play mode operation. In write mode, however, data is interpreted as data words to be written to SRAM. Note that pin SIO is an output pin only when the parity check command is executed. At all other times, SIO is an input pin. Invalid Data Valid Data ? ? ? ? Invalid Data ? ? ? ? ? ?
SIO SC ST
?
? B7 B6 B5 B4 B3 B2 B1 B0
Pin SC should be LOW when either a LOW-to-HIGH or HIGH-to-LOW transition occurs on pin ST.
Figure 4. Serial input timing Playback control The ST pin controls the start of playback. While ST is HIGH, the melody is played repeatedly, and when ST goes LOW, playback stops. Melodies are selected by input serial data on pins SIO and SC, as shown in table 2. The melody select command comprises a fixed code (1000) followed by 4 melody select data bits (B3 to B0). The 8 bits of data are retained even after playback. If serial data is input during playback, the data is ignored and playback continues. Invalid Data Valid Data ? ? ? ? Invalid Data ? ? ? ? ? ?
SIO SC ST MTO
?
? H L L L B3 B2 B1 B0
Pin SC should be LOW when either a LOW-to-HIGH or HIGH-to-LOW transition occurs on pin ST.
Figure 5. Serial data input timing
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SM1126 Series
Table 2. Serial data melody select
B3 L L L L L L L L B2 L L L L H H H H B1 L L H H L L H H B0 L H L H L H L H ST LH LH LH LH LH LH LH LH M e l o dy 1st melody 2nd melody 3rd melody 4th melody 5th melody 6th melody 7th melody 8th melody B3 H H H H H H H H B2 L L L L H H H H B1 L L H H L L H H B0 L H L H L H L H ST LH LH LH LH LH LH LH LH M e l o dy 9th melody 10th melody 11th melody 12th melody 13th melody 14th melody 15th melody SRAM melody
SIO SC ST MTO
#n1 Data
#n2 Data
#n1 Play
#n1 Play
#n1 Play
#n2 Play
Melody plays repeatedly when ST is HIGH, and stops immediately when ST goes LOW.
Figure 6. Melody repetition timing
NIPPON PRECISION CIRCUITS--8
SM1126 Series Playback timing diagrams
Playback start
Playback starts after an interval tST after ST goes HIGH. When the reference clock frequency is 32.768 kHz, tST = (256 1 oscillator cycles) + 1/128 seconds. When the reference clock frequency is 38.4 kHz, tST = (300 1 oscillator cycles) + 1/128 seconds.
Play Start Command SIO SC ST OSC
*Internal Clock
MSB LSB
256(300)
1 Clock
1/128 sec
MTO
,,,,, ,,,,, ,,,,,
Figure 7. Playback start timing
Playback stop
Playback stops immediately when ST goes LOW. In external clock input versions, the IC internal clock also stops when ST goes LOW, regardless of whether or not there is a clock input signal on pin OSC. In built-in RC oscillator versions, the oscillator also stops when ST goes LOW.
ST OSC
*Internal Clock
MTO
,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,
Figure 8. Stop timing
NIPPON PRECISION CIRCUITS--9
SM1126 Series
Write Mode Control
Write sequence The SM1126 Series devices can accept data words written to the built-in SRAM to play any melody. The SRAM write sequence is described below. 1. 2. 3. 4. 5. 6. 7. Write the SRAM write command (11011111) to invoke write mode. Write the tempo word (parity check ON/OFF selectable). Write all necessary melody data words (parity check ON/OFF selectable). Write the melody end word (parity check ON/OFF selectable). Optionally, write extra data words (these are ignored). Write the end-of-write command (10111111) to return to play mode. If parity check was ON, write the parity check command (01111111) to perform an error check.
The built-in SRAM can store 64 words, so all melody and end words must fit within this limit. Note that the tempo word is not stored in SRAM, but in a separate register. Playback of melodies stored in SRAM begins from the SRAM leading address and continues until the end word is detected, at which point playback continues again from the SRAM leading address. All data in SRAM after the end word is ignored.
Input write command (11011111)
Play mode
Input write command (11011111)
Write tempo word
Write tempo word
Write melody word (s)
Write melody word (s)
Write end word
Write mode
Write end word
Write optional invalid data
Write optional invalid data
Input end-of-write command (10111111)
Input end-of-write command (10111111)
Input parity check command (01111111)
Play mode
Example 1. Parity check selected
Example 2. Parity check not selected
Figure 9. Write control sequence
NIPPON PRECISION CIRCUITS--10
SM1126 Series Write command The SRAM write command (11011111), shown below, is used to invoke write mode.
PLAY mode changed to WRITE mode Address set to tempo-word register SIO 1 1 0 1 1 1 1 1
SC
ST
Figure 10. Write command timing
Tempo word The tempo word controls the melody playback speed. The tempo word comprises a fixed code (000) followed by the tempo code (T4 to T0), as shown below. The tempo word is always the first word written after invoking write mode, and all subsequent words are melody data words.
SIO
WRITE command
0
0
0
T4
T3
T2
T1
T0
SC Changed to WRITE mode ST write Tempo-word
ADDRESS
No Address
Tempo Register Address
RAM Address
Figure 11. Tempo word timing
NIPPON PRECISION CIRCUITS--11
SM1126 Series Melody words Melody words contain all the information needed for playback of a single note, including the note duration and type (name or rest). Each melody word comprises a 3-bit length code (R2 to R0) followed by a 5-bit type code (S4 to S0).
SIO
(n-1)th data
(n)th data
SC write (n-1)th Data ST write (n)th data
ADDRESS
n-1
n
n+1
Figure 12. Melody word timing End word The end word (01011111) indicates the end of the melody. When the end word is detected during melody playback, operation returns to the SRAM leading address. All data in SRAM after the end word is ignored.
SIO
0
1
0
1
1
1
1
1
next word
SC write END-WORD ST write next word
ADDRESS
m
m+1
m+2
Figure 13. End word timing End-of-write command The end-of-write command (10111111) is used to return to play mode from write mode. This command should be executed when power is first applied to set play mode.
WRITE mode changed to PLAY mode
SIO
1
0
1
1
1
1
1
1
SC
ST
Figure 14. End-of-write command timing
NIPPON PRECISION CIRCUITS--12
SM1126 Series Parity check command Data words (tempo word, melody words, end word) can have an optional parity bit added, forming 9-bit data words, for a parity check function. The parity check command is executed in play mode, immediately after the end-of-write command is executed. The parity bit is added at the beginning of the data word. Note that the last 8 bits are always the valid data bits. The parity check function performs an odd parity check (an odd number of 1s within the 9-bit data). If the parity check command is not executed, play mode operation continues using the valid 8 bits of data in each data word. The parity check sequence is described below. 1. 2. 3. 4. 5. 6. 7. The internal G flag (Good flag) is set to 1 when the write command is executed. When writing data words, the G flag remains set to 1 for odd parity, but is set to 0 if even parity is detected. The G flag remains set to 1 only if all data words have odd parity. Write the end-of-write command to return to play mode. Write the parity check command. When ST is HIGH, the SIO pin functions as the G flag output. When ST goes LOW, the G flag output is released.
END-WRITE mode command
Parity Check Command
When G Flag = 1 When G Flag = 0
SIO
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
SC
ST
MODE
WRITE mode
PLAY mode
SIO Condition
Input
Output
Input
G Flag
Figure 15. Parity check timing
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SM1126 Series Command summary
Command Melody start command Write command Tempo word Melody word End word End-of-write command Parity check command MSB 1 1 0 R2 0 1 0 Bit 6 0 1 0 R1 1 0 1 Bit 5 0 0 0 R0 0 1 1 Bit 4 0 1 T4 S4 1 1 1 Bit 3 B3 1 T3 S3 1 1 1 Bit 2 B2 1 T2 S2 1 1 1 Bit 1 B1 1 T1 S1 1 1 1 LSB B0 1 T0 S0 1 1 1
Musical Specifications
Maximum program steps A maximum of 256 steps can be programmed into mask-programmable ROM, and a maximum of 64 steps (including one end word) can be stored in built-in SRAM. Each step represents either a note (sound pitch and length) a rest, or a tie. Note length (including rests) Eight rhythm values for notes and rests can be programmed. Also, 2 or more notes can be musically tied.
Table 3. Rhythm values
Code Ty p e 0 Note Rest 1 2 3 4 5 6 7
Pitch and scale SM1126 Series devices support 27 pitches from F4 to G6. The pitch varies with the clock frequency, as shown in the frequency listing in table 4. The reference clock selected at master-slice does not affect the pitch range. Also, two pitches higher than G6 can be set as alarm pitches in mask ROM. Note that an alarm pitch option cannot be specified in SRAM. The frequency error calculation for a given pitch is shown below. Error calculation: (A4 pitch with 32.768 kHz clock) Output frequency log 10 ------------------------------------------------Output frequency Reference frequency 1200 x log 2 ------------------------------------------------- = 1200 x -------------------------------------------------------------Reference frequency log 10 2 Output frequency 3986.3 x log 10 ------------------------------------------------Reference frequency 439.839 3986.3 x log 10 -----------------440.000 - 0.63 cent
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SM1126 Series
Table 4. Frequency range
Note code S4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 System clock Pitch Rest F4 F#4 G4 G#4 A4 A#4 B4 C5 C#5 D5 D#5 E5 F5 F#5 G5 G#5 A5 A#5 B5 C6 C#6 D6 D#6 E6 F6 F#6 G6 AL1 AL2 Tie End word Reference frequency - 349.228 369.994 391.995 415.305 440.000 466.164 493.883 523.251 554.365 587.330 622.254 659.255 698.456 739.989 783.991 830.609 880.000 932.328 987.767 1046.502 1108.731 1174.659 1244.508 1318.510 1396.913 1479.978 1567.982 - - - - 32.768 kHz system F r e q u e n cy divider - 188 177 167 158 149 141 133 125 118 112 105 99 94 89 84 79 74 70 66 63 59 56 53 50 47 44 42 - - - - F r e q u e n cy (Hz) - 348.596 370.260 392.431 414.785 439.839 464.794 492.752 524.288 555.390 585.143 624.152 661.980 697.191 736.360 780.190 829.570 885.622 936.229 992.970 1040.254 1110.780 1170.286 1236.528 1310.720 1394.383 1489.455 1560.381 - - - - Relative F r e q u e n cy error (cent) divider - -3.14 1.24 1.92 -2.17 -0.63 -5.09 -3.97 3.43 3.20 -6.46 5.27 7.14 -3.14 -8.51 -8.41 -2.17 11.02 7.23 9.10 -10.37 3.20 -6.46 -11.14 -10.26 -3.14 11.05 -8.41 - - - - - 220 208 196 185 175 165 156 147 139 131 123 116 110 104 98 92 87 82 78 73 69 65 62 58 55 52 49 - - - - 38.4 kHz system F r e q u e n cy (Hz) - 349.091 369.231 391.837 415.135 438.857 465.455 492.308 522.449 552.518 586.260 624.390 662.069 698.182 738.462 783.673 834.783 882.759 936.585 984.615 1052.055 1113.043 1181.538 1238.710 1324.138 1396.364 1476.923 1567.347 - - - - Relative error (cent) - -0.68 -3.58 -0.70 -0.71 -4.50 -2.64 -5.53 -2.66 -5.78 -3.16 5.93 7.37 -0.68 -3.58 -0.70 8.68 5.42 7.89 -5.53 9.16 6.72 10.11 -8.08 7.37 -0.68 -3.58 -0.70 - - - -
(Note) A4 is the following note.
A4 (440Hz)
Pitches AL1 and AL2 are optional alarm pitches which can take any value higher than G6, set in mask ROM. This option is not supported in SRAM.
NIPPON PRECISION CIRCUITS--15
SM1126 Series Tempo There are 29 tempos that can be selected for each melody. The tempo does not vary with the clock frequency.
Table 5. Tempo range
Code 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F F r e q u e n cy divider 4 5 6 7 8 9 10 11 Moderato 12 13 14 Andante 15 16 17 18 19 20 Larghetto 21 22 23 24 25 26 27 28 29 30 31 32 Largo 61.0 58.2 55.7 53.3 51.2 49.2 47.4 45.7 44.1 42.7 41.3 40.0 Adagio 85.3 80.0 75.3 71.1 67.4 64.0 106.7 98.5 91.4 Allegro Presto Prestissimo Te m p o = 320.0 256.0 213.3 182.9 160.0 142.2 128.0 116.4
Quarter note ( ) length = {1536 (32.768 kHz system) or 1800 (38.4 kHz system)} x tempo counter frequency divider / clock frequency (Ex. 1) Tempo code = 1F (divider = 32), clock frequency = 32.768 kHz (32.768 kHz system) 1536 x 32 / 32768 = 1.5 (seconds) (Ex. 2) Tempo code = 18 (divider = 25), CLK frequency = 153.6 kHz (38.4 kHz system) 1800 x 25 / 38400 = 1.17 (seconds)
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SM1126 Series
TYPICAL APPLICATION
External Clock Input Versions
2.0V to 3.6V B+
CONTROLLER
OSC SIO SC ST
VSS VDD MTO TEST
Built-in RC Oscillator Versions
2.0 to 3.6V B+
RO OSC CONTROLLER SIO SC ST CO VSS VDD MTO TEST
NIPPON PRECISION CIRCUITS--17
SM1126 Series
OSCILLATOR FREQUENCY MEASUREMENT
The measurement circuit below shows a SM1126xxV with built-in RC oscillator circuit and external RC oscillator components capacitor CO and resistor RO. When ST is switched to VDD, the oscillator starts and outputs a pulse on MTO with a frequency double that of the RC oscillator. The output pulse is counted using a frequency counter.
RO
SM1126 OSC
V VSS VDD MTO TEST Frequency Counter
CO
SIO SC
Switch
ST
Note that the board mounting and wiring will marginally affect the output frequency, even for equivalent values for RO and CO.
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9722BE 1998.12
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS--18

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