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M616Z08
128 Kbit (8 Kbit x 16) SRAM WITH OUTPUT ENABLE
FEATURES SUMMARY s OPERATION VOLTAGE: 2.34V to 3.6V
s s
Figure 1. 44-pin, Hatless SOIC Package
8 Kbit x 16 SRAM EQUAL CYCLE and ACCESS TIMES: AS FAST AS 20ns TRI-STATE COMMON I/O TWO WRITE ENABLE PINS ALLOW WRITING TO UPPER AND LOWER BYTES
44 1
s s
SO44 (MH)
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A12 DQ0-DQ15 Address Inputs Data Input/Output Chip Enable Output Enable WRITE Enable DQ 0-7 WRITE Enable DQ 8-15 Supply Voltage Ground Time-Out Pin
13 A0-A12
16 DQ0-DQ15
CE OE WE0
WE0 WE1
M616Z08
WE1
TO CE OE
VCC VSS TO
VSS
AI04213
Note: TO Pin should be connected to VCC.
July 2002
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M616Z08
TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 44-pin Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC and AC Measurement Conditions (Table 3.) . . . AC Testing Load Circuit (Figure 4.) . . . . . . . . . . . . . Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....5 .....5 .....5 .....6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Controlled, READ Mode AC Waveforms (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 6.). . . . . . . . . . . . . 7 READ Mode AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Enable Controlled, WRITE Mode AC Waveforms (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 "Operational" Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WE(0,1) States during Access (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating Modes (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M616Z08
DESCRIPTION The M616Z08 is a 128 Kbit (131,072 bit) CMOS SRAM, organized by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.6V 10% or Figure 3. 44-pin Connections
DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 VCC VSS DQ8 DQ9 DQ10 DQ11 VSS VCC DQ12 DQ13 DQ14 DQ15
Note: TO Pin should be connected to VCC.
3.3V 10% supply, and all inputs and outputs are TTL compatible. The M616Z08 is available in a 44-lead SOIC package.
44 1 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 34 11 M616Z08 33 12 32 13 31 14 30 15 29 16 28 17 27 18 26 19 25 20 24 21 23 22
A12 A11 A10 A9 VCC VSS A08 A07 TO CE OE WE1 WE0 A06 A05 A04 VSS VCC A03 A02 A01 A00
AI04212
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M616Z08
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG(1) VIO(2,3) VCC IO(4) PD Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltage Supply Voltage Output Current Power Dissipation Value -40 to 125 -65 to 150 -0.3 to VCC + 0.3 -0.3 to 4.0 10 270 Unit C C V V mA mW
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 and 120 seconds). 2. Up to a maximum operating VCC of 3.6V only. 3. VIL(min) = VSS - 2.0V AC (pulse width 10% tAVAV(min)) VIH(max) = VCC + 2.0V AC (pulse width 10% tAVAV(min)) 4. One output at a time, not to exceed 1 second duration.
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M616Z08
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 3. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output High Z is defined as the point where data is no longer driven.
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
M616Z08 2.34 to 3.0V or 3.0 to 3.6V -40 to 125C 50pF 5ns 0 to 3V 1.5V
Figure 4. AC Testing Load Circuit
3.0V
2.6 K DEVICE UNDER TEST OUT
2.6 K
CL = 50 pF or 5pF
AI05650
Table 4. Capacitance
Symbol CIN COUT(3) Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 3.3V; sampled only, not 100% tested. 2. At 25C; f = 1MHz. 3. Outputs deselected.
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M616Z08
Table 5. DC Characteristics
Sym ILI ILO ICC1(3) ICC3(4) VIL VIH VOL VOH
Note: 1. 2. 3. 4.
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition(1) 0V VIN VCC TO Pin(2) All other inputs 0V VOUT VCC VCC = 3.6V VCC = 3.6V, CE VCC - 0.2V, f = 0
Min
Typ 65
Max 125 1 1 75 1
Unit A A A mA mA V V V
-0.3 0.7VCC IOL = 1mA 2.34 to 3.0V IOH = -1mA 3.0 to 3.6V VCC-0.2V VCC-0.3V
0.3VCC VCC + 0.3 0.2
V
Valid for Ambient Operating Temperature: TA = -40 to 125C; VCC = 3.0 to 3.6V or 2.34 to 3.0V (except where noted). Input leakage on TO Pin due to internal pull-down to VSS. Average AC current, Outputs open, cycling at tAVAV minimum. All other Inputs at VIL 0.2V or VIH VCC -0.2V.
OPERATION READ Mode The M616Z08 is in the READ Mode whenever WRITE Enable (WE0 or WE1) is High with Output Enable (OE) Low, and Chip Enable (CE) is asserted. This provides access to data from sixteen of the 131,072 locations in the static memory array, specified by the 13 address inputs. Valid data will be available at the sixteen output pins within tAVQV
after the last stable address, providing OE is Low and CE is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV.
Figure 5. Address Controlled, READ Mode AC Waveforms
tAVAV A0-A12 tAVQV VALID tAXQX
DQ0-DQ15
DATA VALID
AI04210
Note: CE = Low, OE = Low, WE(0,1) = High.
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M616Z08
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV A0-A12 tAVQV tELQV CE tELQX tGLQV
OE
VALID tAXQX tEHQZ
tGHQZ
tGLQX DQ0-DQ15 VALID
AI05638
Table 6. READ Mode AC Characteristics
M616Z08 Symbol Parameter(1) -20 2.34 to 3.0V Min tAVAV tAVQV tELQV tGLQV tELQX tGLQX tEHQZ
(2)
3.0 to 3.6V Min 20 Max
Unit
Max
READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
36 36 36 20 0 0 10 10 0
ns 20 20 10 ns ns ns ns ns 10 10 ns ns ns
0 0
tGHQZ(2) tAXQX
0
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 125C (except where noted). 2. CL = 5pF.
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M616Z08
WRITE Mode The M616Z08 is in the WRITE mode whenever the WE0 (low memory addresses) or WE1 (high memory addresses) and CE pins are low (see Table 8, page 10). Either the Chip Enable input (CE) or the WRITE Enable input (WE0 or WE1) must be deasserted during Address transitions for subsequent WRITE cycles. WRITE begins with the concurrence of Chip Enable being active with WE0 or WE1 low. Therefore, address setup time is referenced to WRITE Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge.
The WRITE cycle can be terminated by the earlier rising edge of CE, or WE0/WE1. if the Output is enabled (CE = Low and OE = Low), then WE0 or WE1 will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of WRITE Enable, or for tDVEH before the rising edge of CE, whichever occurs first, and remain valid for tWHDX or tEHDX. Note: When using MCP555 with TO Pin high, relaxed WRITE timing (CSNT = 1 in the chip select configuration register) should be selected.
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A12 VALID tAVWH tAVEL CE tWLWH tAVWL WE (0,1) tWLQZ tWHDX DQ0-DQ15 DATA INPUT tDVWH
AI04211
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A12 VALID tAVEH tAVEL CE tAVWL WE (0,1) tEHDX DQ0-DQ15 DATA INPUT tDVEH
AI05639
tELEH
tEHAX
Note: 1. Output Enable (OE) = High. 2. If CE goes High with WE0 or WE1 high, the output remains in a high-impedance state.
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M616Z08
Table 7. WRITE Mode AC Characteristics
M616Z08 Symbol Parameter(1) -20 Unit 2.34 to 3.0V Min tAVAV tAVWL tAVWH tAVEH tWLWH tWHAX tWHDX tWHQX(3) tWLQZ(2,3) tAVEL tELEH tEHAX tEHDX tDVWH tDVEH WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable Pulse Width WRITE Enable High to Address Transition WRITE Enable High to Input Transition WRITE Enable High to Output Transition WRITE Enable Low to Output Hi-Z Address Valid to Chip Enable Low Chip Enable Low to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High 2 25 2 2 20 20 36 2 34 34 25 2 2 0 10 2 11 2 2 8 8 Max 3.0 to 3.6V Min 20 2 18 18 11 2 2 0 10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 125C (except where noted). 2. CL = 5pF 3. At any given temperature and voltage condition, t WLQZ is less than tWHQX for any given device.
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M616Z08
"Operational" Mode The M616Z08 has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (CE = High). An Output Enable (OE) signal provides a high speed tri-state control, allowing fast READ/WRITE cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs WE0 or WE1 and CE as summarized in "Operating Modes" (see Table 8 and Table 9). Noise Immunity When designing with high speed memory, proper power trace layout and capacitive decoupling must be maintained to ensure proper system operation. Power and ground line inductance should be reduced by providing separate power planes. The impedance of the decoupling path from the power pin through the decoupling capacitor should also be kept to a minimum. Small decoupling capacitors (10nF) should be located as close to the device pins as possible to limit the high frequency noise. Larger capacitor values (10uF and 1uF) are recommended to reduce low frequency noise and should be placed next to the power entry point of the board. Proper line termination should also be employed to minimize signal reflection. See Motorola Semiconductor Application Note AN2127/D for additional Electromagnetic Compatibility (EMC) system design guidelines.
Table 8. WE(0,1) States during Access
WRITE Enable WE0 WE1 Used during 16-bit Port Access WRITE Enable for DQ (0-7) WRITE Enable for DQ (8-15)
Table 9. Operating Modes
Operation Deselect Word WRITE Byte 0 WRITE Byte 1 WRITE Byte 0 WRITE, Byte 1 READ Byte 1 WRITE, Byte 0 READ Word READ
Note: 1. X = '1' or '0'
CE VIH VIL VIL VIL VIL VIL VIL
OE X(1) VIH VIH VIH VIL VIL VIL
WE0 X(1) VIL VIL VIH VIL VIH VIH
WE1 X(1) VIL VIH VIL VIH VIL VIH
DQ0-DQ7 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data Data
DQ8-15 Hi-Z Hi-Z Hi-Z Hi-Z Data Hi-Z Data
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M616Z08
PART NUMBERING Table 10. Ordering Information Example
Example: M6 16Z08 -20 MH 3 TR
Device Type M6
Device Function 16Z08 = 128Kbit (8 x16)
Speed -20 = 20ns (3.0 to 3.6V)
Package MH = 44-lead, Hatless SOIC
Temperature Range 3 = -40 to 125C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M616Z08
PACKAGE MECHANICAL INFORMATION Figure 9. SO44 - 44-Lead, Plastic, Hatless, Small Package Outline
A2 B e
A C CP
D
N
E
H A1 L
1 SOH-C
Note: Drawing is not to scale.
Table 11. SO44 - 44-lead, Plastic, Hatless, Small Package Mechanical Data
mm Symb Min A A1 A2 B C D E e H L a N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 - 11.51 0.41 0 44 0.10 Typ Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 - 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 - 0.453 0.016 0 44 0.004 Min Typ Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 - 0.500 0.050 8 inches
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M616Z08
REVISION HISTORY Table 12. Document Revision History
Date September 2001 11/1901 02/12/02 02/21/02 05/13/02 07/22/02 Rev. # 1.0 2.0 2.1 2.2 2.3 2.4 First Issue Correction of Operating Modes text (Table 9); document status changed to "Data Sheet;" add text for Noise Immunity (page 10) Add TO Pin (Figure 2, 3, Table 1); change WRITE Mode AC Characteristics (Table 7) Changes for TO Pin (Table 5) and change characteristics (Table 6, 7) Add reflow time and temperature footnote (Table 2) Add "Hatless" to package description (Figure 1, 9 and Table 10, 11) Revision Details
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M616Z08
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