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| CXD2458AR Timing Generator for Color LCD Panels For the availability of this product, please contact the sales office. Description The CXD2458AR is a timing signal generator for the color LCD panel LCX005BK/BKB, LCX009AK/ AKB, LCX024AK and LCX027AK drivers. Features * Generates the color LCD panel LCX005BK/BKB, LCX009AK/AKB, LCX024AK and LCX027AK drive pulse * Supports NTSC/PAL * Supports 16:9 (WIDE) display (NTSC/PAL) * Supports composite SYNC and separate SYNC (XHD, XVD) input * Standby function (low power consumption function) * Supports right/left inverse display * AC drive of LCD panels during no signal * Generates timing signal of external sample-andhold circuit * Generates line inversion and field inversion signals * AFC circuit supporting static and dynamic fluctuations Applications Color LCD viewfinders, compact LCD projectors, etc. Structure Silicon gate CMOS IC 48 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD VSS - 0.3 to +6.0 V * Input voltage VI VSS - 0.3 to VDD + 0.3 V * Output voltage VO VSS - 0.3 to VDD + 0.3 V * Operating temperature Topr -20 to +85 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 2.7 to 3.3 * Operating temperature Topr -20 to +85 V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98218-PS CXD2458AR Block Diagram 19 VDD CKO 41 master ck 43 VDD 6 CKI 42 STBY 15 SLCK PLNT XCLR 1 2 3 H-SYNC DETECTOR H-SKEW DETECTOR PLL PHASE COMPARATOR VSS 31 VSS 40 VSS 39 RPD XHD 27 HALF-H KILLER PLL-COUNTER 35 XCLP 36 HD XVD 45 TST0 TST1 TST2 7 8 9 V-SYNC SEPERATOR (NOISE SHAPE) 46 HP1 47 HP2 48 HP3 38 HP4 10 H-TIMING PULSE GENERATOR RGT TST3 37 TST4 44 22 HST1 14 HST2 24 HCK1 23 HCK2 32 SH1 33 SH2 BLK 12 EN 17 VD 25 VST 18 VCK1 21 VCK2 20 FLDO 29 SBLK 5 FIELD & LINE CONTROLLER PAL PULSE ELIMINATOR V-TIMING PULSE GENERATOR 34 SH3 30 SH4 16 CLR SLTM 11 SLNP 26 13 SLFR 28 FRP WIDE 4 -2- CXD2458AR Pin Description Pin Symbol No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SLCK PLNT XCLR WIDE SBLK VSS TST0 TST1 TST2 RGT SLTM BLK SLFR HST2 STBY CLR EN VST VDD VCK2 VCK1 HST1 HCK2 HCK1 VD SLNP XHD FRP FLDO SH4 VSS SH1 SH2 SH3 I/O I I I I O -- I I I I I O I O I O O O -- O O O O O O I I O O O -- O O O Description Switches between LCX005, LCX024 (H) and LCX009, LCX027 (L) Switches between PAL (H) and NTSC (L) Cleared at 0V Switches between 16:9 display (H) and 4:3 display (L) SBLK pulse output (during WIDE MODE) (positive polarity) GND Test (Leave open.) Test (Leave open.) Test (Leave open.) Switches between Normal scan (H) and Reverse scan (L) Switches between LCX027 (H) and LCX009 (L) BLK pulse output (during WIDE MODE) (positive polarity) Switches between field inversion (H) and line inversion (L) H start pulse 2 (positive polarity) Standby input (H: Operating mode, L: Standby mode) CLR pulse output EN pulse output V start pulse output Power supply V clock pulse 2 V clock pulse 1 H start pulse 1 (positive polarity) H clock pulse 2 H clock pulse 1 VD pulse output (positive polarity) Switches between LCX024 (H) and LCX005 (L) XHD (negative polarity)/Composite SYNC (positive polarity) input AC drive timing pulse Field identification signal Sample-and-hold pulse (positive polarity) GND Sample-and-hold pulse (positive polarity) Sample-and-hold pulse (positive polarity) Sample-and-hold pulse (positive polarity) Input pin for open status L L H L -- -- L L L H L -- L -- H -- -- -- -- -- -- -- -- -- -- L -- -- -- -- -- -- -- -- -3- CXD2458AR Pin Symbol No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 XCLP HD TST3 HP4 RPD VSS CKO CKI VDD TST4 XVD HP1 HP2 HP3 I/O O O I I O -- O I -- I I I I I Description Burst position clamp pulse (negative polarity) HD pulse (positive polarity) Test (Leave open.) Switches the horizontal display position Phase comparator output GND Oscillation cell (output) Oscillation cell (input) Power supply Test (Leave open.) XVD (negative polarity) input Switches the horizontal display position Switches the horizontal display position Switches the horizontal display position Input pin for open status -- -- H H -- -- -- -- -- H L L L L (H: Pull up, L: Pull down) Note) The CXD2458AR processes the composite SYNC and separate SYNC inputs with the same pins. Therefore, care should be given to the following points when using the CXD2458AR. 1) During composite SYNC input, the XVD input pin should be set to L or left open. 2) During separate SYNC (XHD, XVD) input, the XVD width specification is from 2H to 10H. -4- CXD2458AR Electrical Characteristics DC Characteristics Item H level input voltage L level input voltage H level input current L level input current H level input current L level input current H level input current L level input current L level output voltage H level output voltage L level output voltage H level output voltage L level output voltage H level output voltage Output leak current Current consumption 1 2 3 4 5 6 7 8 Symbol Measurement conditions VIH VIL IIH1 IIL1 IIH2 IIL2 IIH3 IIL3 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 IOZ IDD VI = VDD VI = 0V VI = VDD VI = 0V VI = VDD VI = 0V IOL = 1mA IOH = -250A IOL = 500A IOH = -125A IOL = 500A IOH = -250A At high impedance state VDD = 3.0V, STBY = H VDD = 3.0V, STBY = L 2.6 -1.0 12 3 1.0 2.6 0.2 2.6 0.2 -10 10 (VDD = 3.0V 10%, Topr = -20 to +85C) Min. 0.7VDD 0.3VDD 1.0 -1.0 180 -3.0 3.0 -180 0.2 Typ. Max. Unit Remarks V V A A A A A A V V V V V V A mA mA 1 2 3 4 5 6 7 8 All input pins. Input pins XHD and CKI. Input pins SLNP and XVD. Input pins XCLR, RGT, STBY, HP4, TST3 and TST4. Output pins HCK1 and HCK2. All output pins other than those listed in 5, 7 and 8. Output pin CKO. However, set the input level of input pin CKI to 0V or VDD during measurement. Output pin RPD. (VDD = 3.0V 10%, Topr = -20 to +85C) Applicable pins CKI HCK1, HCK2 Symbol Conditions tck t CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF 1 1 48 Min. 60 1 3 15 20 84 76 71 62 5 5 53 Typ. Max. Unit ns ns ns ns ns ns ns ns ns % AC Characteristics Item Clock input cycle Cross-point time difference VCK1, VCK2 VCKn, HCKn Output rise delay time Other than HCKn and VCKn VCKn, HCKn tpr Output fall delay time Other than HCKn and VCKn tpf dt1 dt2 dtyH HCK1, SH1 delay time difference HCK1, SH1 HCK2, SH1 delay time difference HCK2, SH1 HCK Duty HCK1, HCK2 -5- CXD2458AR Timing Definition AC Characteristics 100% tpr VDD Output 0V VDD Output tpf 0V VDD 0V CKI HCK1/VCK1 50% 50% VDD 0V VDD HCK2/VCK2 50% 50% 0V t t tck CKI HCK1/HCK2 50% 50% 50% tH tL SH1 50% 50% dt1 dt2 -6- LCX005BK/BKB, LCX024AK Pixel Arrangement dummy1 dummy1 dummy2 Vout1 Vout2 Vout3 B G B B G B G Hout1 Hout2 Hout3 Hout174 Hout175 dummy2 to 5 G R B G B R B R B R G B R G B R G B R G G G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G B G B G B G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G B G B G B G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G B G B G B G R B R B R B R G R G R G R G B G B G B G B R B R B R B R G R G R G R G B G B G B G B G B R G B R G B R G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G B G B G B G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G B G B G B G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G R 2 R R R BRGBR Drive display area R B R B R B G R G R B G G R B G R B B G R B G R B G G 218 B G B G B G R R R 222 -7- B B Vout217 Vout218 dummy3 dummy4 B G G G GBRGBRGBRGBRGBRGBRGBRGBRGBR Photo-shielding area BRGBRGBRGBRGBRGBRGBRGBRGBRG 2 3 521 537 13 CXD2458AR LCX009AK/AKB, LCX027AK Pixel Arrangement dummy1 to 4 dummy1 dummy2 Vout1 Vout2 Vout3 R B R G B R B R B Vout224 Vout225 dummy3 R G G R B G R B G R B G R B G R B G R B G R B G Hout1 Hout2 Hout3 Hout267 Hout268 dummy5 to 8 B G R B R B G R G R G R B G B G B G B R B R B R B R G G G G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G B G B G B G R B R B R B R B R B R B R B G R G R G R G R G R G R G R B G B G B G B G B G B G B G R B R B R B R G R G R G R G B G B G B G B R B R B R B R G R G R G R G B G B G B G B R B R B R B R G R G R G R G B G B G B G B R B R B R B R G R G R G R G B G B G B G B R B R B R B R G R G R G R G B G B G B G B R 2 R R R BRGBRGBRGBRGBRG Drive display area RGBRGBRGBRGBRGBR B R B R B G R G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R G R -8- 225 228 BRGBRGBRGBRGBRGBRGBRGBRGBR Photo-shielding area RGBRGBRGBRGBRGBRGBRGBRGBRG 1 14 800 827 13 CXD2458AR CXD2458AR Description of Mode Selection Switch (SLCK, SLTM, SLNP, PLNT, WIDE) SLCK SLTM SLNP PLNT WIDE H H H H H H H H L L L L L L L L X X X X X X X X L L L L H H H H L L L L H H H H X X X X X X X X L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H MODE LCX005BK/BKB, NTSC, NORMAL LCX005BK/BKB, NTSC, WIDE LCX005BK/BKB, PAL, NORMAL LCX005BK/BKB, PAL, WIDE LCX024AK, NTSC, NORMAL LCX024AK, NTSC, WIDE LCX024AK, PAL, NORMAL LCX024AK, PAL, WIDE LCX009AK/AKB, NTSC, NORMAL LCX009AK/AKB, NTSC, WIDE LCX009AK/AKB, PAL, NORMAL LCX009AK/AKB, PAL, WIDE LCX027AK, NTSC, NORMAL LCX027AK, NTSC, WIDE LCX027AK, PAL, NORMAL LCX027AK, PAL, WIDE NORMAL (4:3 display), WIDE (16:9 display) X: Don't Care SLFR SLFR is the selector switch for the AC drive timing pulse (FRP). This switch selects field inversion when H and line inversion when L. Normally, line inversion (L) is used. The transition point is one clock cycle after the transition point of the VCK1 and VCK2 pulses. FRP 1H inversion (2H cycle) 1H 1H 1H 1H 1F inversion (2F cycle) 1Field 1Field FRP polarity is not specified. -9- CXD2458AR AFC Circuit (PLL Method) The CXD2458AR employs the PLL method in order to achieve phase synchronization with the input sync signal. The PLL circuit phase comparator and frequency division counter are built in, and a fully synchronized AFC circuit is comprised by connecting an external VCO circuit and LPF. PLL errors are detected at the following timing. The phase comparison output of the entire bottom of XHD or the horizontal sync signal of composite SYNC and the internal H counter becomes RPD. RPD output is converted to DC error with the lag-lead filter (LPF), and then it changes the varicap capacitance to stabilize the oscillating frequency at 702fh in the LCX005BK/BKB and LCX024AK, and 1050fh in the LCX009AK/AKB and LCX027AK. This PLL circuit is adjusted by setting the RPD transition point so that it sets in the center of the window (XHD or horizontal sync signal of composite SYNC) as shown in the figure below. 4.7s XHD or horizontal sync signal of composite SYNC RPD WL = WH WL WH AC Driving for No Signal HST1/2, HCK1/2, FRP, VCK1/2, XCLP, VST, HD, VD, SH1/2/3/4 and EN are made to run freely so that the LCD panel is AC driven even when there are no input sync signals (XHD/XVD and composite SYNC). During this time, the horizontal sync separation circuit stops and the PLL internal frequency division counter is made to run freely. At the same time, the auxiliary V counter is used to create the reference pulse for generating the free running VD and VST because the vertical sync separation circuit is also stopped. The cycle of this V counter is set to 269H for NTSC and 321H for PAL. However, when there is no XVD (VSYNC) input for 301H (NTSC) and 360H (PAL), the no signal state is assumed and the free running VD and VST pulses are generated from the next field. RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing phase errors due to phase comparison. System Clear (XCLR) The entire logic is initialized by setting XCLR = L. Be sure to perform this operation during power-on and after changing the STBY pin from L to H. When this function is activated the outputs (XCLP, HD, FRP, VST, VD, CLR, EN, HST1/2, HCK1/2, SH1/2/3/4, VCK1/2, FLDO, SBLK and BLK) go to L. - 10 - CXD2458AR Right/Left Inverse Display The CXD2458AR outputs a right/left inversion timing pulse that supports the right/left inverse display function of the LCX005BK/BKB, LCX024AK, LCX009AK/AKB and LCX027AK. The LCD panel is arranged in a delta pattern, where the same signal line is 1.5-dot offset at adjoining vertical lines. For this reason, a 1.5-dot offset is attached to the horizontal start pulse (HST) of the LCD between odd lines and even lines in order to correct this difference. Other H system output pulses are also 1.5-dot offset. When the panel is driven with left scan (Reverse scan), this offset relationship becomes inverted for even and odd lines, and the asymmetrical dot arrangement produces an offset. Therefore, the CXD2458AR internally controls the right/left and interline offset to allow right scan or left scan display by setting RGT = H or L for right/left inversion. Right scan (Normal scan) Left scan (Reverse scan) H SCANNER V SCANNER Display area SH Pulse and HCK Phase Relationship The phase relationship between the SH pulse and HCK changes according to switching between right scan (Normal scan) and left scan (Reverse scan). SH3 is the re-sampling pulse. RGT = H (Normal scan) RGT = L (Reverse scan) HCK1/2 SH1 SH2 SH3 SH4 - 11 - CXD2458AR 16:9 (WIDE) Display Mode Setting the WIDE pin to H shifts the unit to WIDE display mode. In this mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE display. Vertical pulse eliminator scanning of 1/4 (NTSC) and 2/6 (PAL) for the LCX005BK/BKB and LCX009AK/AKB, and 1/4 (NTSC) and 10/28 (PAL) for the LCX024AK and LCX027AK is performed, and the video signal is compressed in the display area compared to 4:3 display to achieve 16:9 (WIDE) display. In addition, in areas outside the display area, vertical high-speed scanning is performed and black signals are written to the black display area in the upper 28 lines and the lower 27 or 28 lines. During this period, the FRP and HST output cycles are also changed, and EN and CLR are not output. In addition, the SBLK output, which is the black signal generation timing pulse, and the LCX024AK/LCX027AK black display area control signal BLK are both H. (For example, black display in the panel is permitted by connecting the SBLK output to the external RGB input pin of the CXA1785AR.) See the Timing Charts for details. Vertical high speed scanning Black display area 28 LINES (28 LINES) 218 LINES (225 LINES) Display area Display area 163 LINES (169 LINES) Black display area 4:3 display 16:9 display 27 LINES (28 LINES) Vertical pulse eliminator scanning Numbers in parentheses are for the LCX009AK/AKB and LCX027AK. Note) When the no signal status occurs during 16:9 (WIDE) display mode, 4:3 display mode results. - 12 - CXD2458AR HP1, 2, 3, 4 These are selector switches for the horizontal display position. The HST timing can be set at 2fh intervals in 16 different ways by using the four HP1, 2, 3 and 4 bits. The picture center is set at internal preset value: HP1/2/3/4: LLLH. However, because there is actually a difference between the RGB signal and the drive pulse delays, the picture center may not match the design center. In this case, adjust with these switches. The HST timing (from SYNC termination to the rising edge of HST) for even lines is shown below. LCX005BK/BKB, LCX024AK (NTSC/PAL) HP4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 HP3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 HP2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HP1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HST1 (NTSC/PAL) 72fh (6.51/6.56s) 70fh 68fh 66fh 64fh 62fh 60fh 58fh 56fh (5.06/5.11s) 54fh 52fh 50fh 48fh 46fh 44fh 42fh (3.80/3.83s) HST2 (NTSC/PAL) 74.5fh (6.74/6.79s) 72.5fh 70.5fh 68.5fh 66.5fh 64.5fh 62.5fh 60.5fh 58.5fh (5.29/5.33s) 56.5fh 54.5fh 52.5fh 50.5fh 48.5fh 46.5fh 44.5fh (4.02/4.06s) The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above timings. (See the Timing Charts for details.) - 13 - CXD2458AR LCX009AK/AKB, LCX027AK (NTSC/PAL) HP4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 HP3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 HP2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HP1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HST1 (NTSC/PAL) 91fh (5.51/5.55s) 89fh 87fh 85fh 83fh 81fh 79fh 77fh 75fh (4.54/4.57s) 73fh 71fh 69fh 67fh 65fh 63fh 61fh (3.69/3.72s) HST2 (NTSC/PAL) 93.5fh (5.66/5.70s) 91.5fh 89.5fh 87.5fh 85.5fh 83.5fh 81.5fh 79.5fh 77.5fh (4.69/4.72s) 75.5fh 73.5fh 71.5fh 69.5fh 67.5fh 65.5fh 63.5fh (3.84/3.87s) The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above timings. (See the Timing Charts for details.) - 14 - LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 SH1 SH2 SH3 SH4 FRP VCK1 VCK2 CLR EN ODD LINE Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. 0.5s (6fh) 3.0s (33fh) ODD FIELD EVEN FIELD 18.5fh 1.3s (14fh) 2.1s (23fh) 4.7s (52fh) 4.7s (52fh) 4.4s (49fh) 2.0s (22fh) 4.5fh 0.5fh 13fh 13fh - 15 - CXD2458AR LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 SH1 SH2 SH3 SH4 FRP VCK1 VCK2 0.5s (6fh) CLR EN EVEN LINE 3.0s (33fh) ODD FIELD EVEN FIELD 18.0fh 1.3s (14fh) 2.1s (23fh) 4.7s (52fh) 4.7s (52fh) 4.4s (49fh) 2.0s (22fh) 2.5fh 13fh 13fh 3.0fh - 16 - CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 SH1 SH2 SH3 SH4 FRP VCK1 VCK2 0.5s (5fh) CLR EN ODD LINE 3.0s (34fh) ODD FIELD EVEN FIELD 18.0fh 2.1s (23fh) 4.7s (52fh) 4.7s (52fh) 4.4s (49fh) 2.0s (22fh) 2.5fh 13fh 13fh 4.0fh - 17 - CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 SH1 SH2 SH3 SH4 FRP VCK1 VCK2 0.5s (5fh) CLR EN EVEN LINE 3.0s (34fh) ODD FIELD EVEN FIELD 18.5fh 1.4s (15fh) 2.0s (22fh) 4.7s (52fh) 4.7s (52fh) 4.5s (50fh) 2.0s (22fh) 0.5fh 13fh 13fh 5.5fh - 18 - CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 1.3s (22fh) 2.0s (34fh) 4.7s (78fh) 4.7s (78fh) 4.4s (72fh) 2.0s (33fh) 0.5fh 2.5fh 12fh 12fh - 19 - SH1 SH2 SH3 SH4 FRP VCK1 VCK2 0.5s (8fh) CLR EN ODD LINE 3.0s (50fh) ODD FIELD EVEN FIELD 43.5fh CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 SH1 SH2 SH3 SH4 FRP VCK1 VCK2 0.5s (8fh) CLR EN EVEN LINE 3.0s (50fh) ODD FIELD EVEN FIELD 43.0fh 1.3s (22fh) 2.0s (34fh) 4.7s (78fh) 4.7s (78fh) 4.4s (72fh) 2.0s (33fh) 2.5fh 12fh 12fh 4.0fh - 20 - CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 1.3s (22fh) 2.0s (34fh) 4.7s (78fh) 4.7s (78fh) 4.4s (72fh) 2.0s (33fh) 2.5fh 12fh 12fh 3.0fh - 21 - SH1 SH2 SH3 SH4 FRP VCK1 VCK2 0.5s (7fh) CLR EN ODD LINE Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. 3.0s (51fh) ODD FIELD EVEN FIELD 43.0fh CXD2458AR LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 1.3s (22fh) 2.0s (34fh) 4.7s (78fh) 4.7s (78fh) 4.4s (72fh) 2.0s (33fh) 0.5fh 12fh 12fh 1.5fh - 22 - SH1 SH2 SH3 SH4 FRP VCK1 VCK2 0.5s (7fh) CLR EN EVEN LINE Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. 3.0s (51fh) ODD FIELD EVEN FIELD 43.5fh CXD2458AR LCX005BK/BKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 - 23 - FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) - 24 - HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX005BK/BKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 25 - ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. - 26 - CXD2458AR LCX005BK/BKB Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 27 - ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 28 - EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL WIDE 163-line display area, 2/6 pulse elimination, XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 : 1st display line 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 29 - ODD FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX005BK/BKB Vertical Direction Timing Chart PAL WIDE 163-line display area, 2/6 pulse elimination, XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 : 1st display line 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 30 - EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX024AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD - 31 - CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 - 32 - FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 33 - ODD FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX024AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 34 - EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX024AK Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 - 35 - FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 36 - EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX024AK Vertical Direction Timing Chart PAL WIDE 163-line display area, 10/28 pulse elimination, XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 : 1st display line 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) - 37 - HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX024AK Vertical Direction Timing Chart PAL WIDE 163-line display area, 10/28 pulse elimination, XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 : 1st display line 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 38 - EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 39 - ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 - 40 - FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 41 - ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 42 - EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 43 - ODD FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX009AK/AKB Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 : 1st display line 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 44 - EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX009AK/AKB Vertical Direction Timing Chart PAL WIDE 169-line display area, 2/6 pulse elimination, XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 : 1st display line 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) - 45 - HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX009AK/AKB Vertical Direction Timing Chart PAL WIDE 169-line display area, 2/6 pulse elimination, XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 : 1st display line 50 55 (BLK) VST VCK1 VCK2 - 46 - FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 - 47 - FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. - 48 - CXD2458AR LCX027AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 49 - ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 50 - EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 51 - ODD FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX027AK Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 52 - EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart PAL WIDE 169-line display area, 10/28 pulse elimination, : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK - 53 - ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart PAL WIDE 169-line display area, 10/28 pulse elimination, : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 - 54 - FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR Application Circuit AC conversion circuit (RGB driver) Backlight driver circuit Sample-and-hold circuit (RGB driver) Sample-and-hold circuit (RGB driver) RGB driver RGB decoder +3V LCX024AK LCX005BK/BKB 36 35 34 33 32 31 30 29 28 27 26 25 SH1 FLDO XHD SH3 HD VSS XCLP SLNP SH2 FRP SH4 +3V 3.3 10k 3300p 0.01 10k 100k 20p RGB decoder +12V 33k 1000p L 1k 37 TST3 38 HP4 39 RPD 40 VSS 41 CKO 42 CKI 43 VDD 44 TST4 45 XVD 46 HP1 47 HP2 48 HP3 VD HCK1 24 HCK2 23 HST1 22 VCK1 21 VCK2 20 VDD 19 VST 18 EN 17 CLR 16 STBY 15 +3V HST2 14 LCD panel XCLR SLCK PLNT WIDE TST0 TST2 SLTM SBLK TST1 RGT BLK SLFR 13 LCD panel VSS 6 1 +3V 2 3 4 5 7 8 9 10 11 12 LCD panel RGB external input (RGB driver) LCX005BK/BKB, LCK024AK LCX009AK/AKB, LCK027AK 16:9 PAL NTSC 4:3 N LCX027AK LCX009AK/AKB R Reference examples of L value: when using LCX009AK/AKB, LCX027AK 4.7H when using LCX005BK/BKB, LCX024AK 10H Recommended varicap: 1T369 (SONY) The constants noted above are reference values, so care should be taken as they may change according to the wiring capacitance on the board, etc. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 55 - CXD2458AR Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 0.3 7.0 0.2 36 25 0.15 0.05 37 24 A 48 13 1 0.5 12 0.2 0.06 0.08 M 0.1 0.1 8.0 0.2 0.65 0.2 1.45 0.2 0 to 10 0.1 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L111 LQFP048-P-0707-AP LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g - 56 - 0.5 |
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