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CXA2056Q
Digital CCD Camera Head Amplifier
Description The CXA2056Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the lowband chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver. Features * High sensitivity made possible by a high-gain AGC amplifier * Blanking function provided for the purpose of calibrating the CCD output signal black level * Regulator output pin provided for A/D converter reference voltage * Built-in GCA and AMP for amplifying video signals (chroma and line signals) from external sources * Built-in sample-and-hold circuits for camera signals required by external A/D converters Absolute Maximum Ratings * Supply voltage VCC * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Conditions Supply voltage VCC1, 2, 3 Applications Digital CCD cameras Structure Bipolar silicon monolithic IC 32 pin QFP (Plastic)
11 -20 to +75 -65 to +150 1160
V C C mW
3 to 3.3
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E96119A8X-PS
CXA2056Q
Block Diagram and Pin Configuration
CCDLEVEL
CLPDM
GND1
SHD
SHP
VCC1
AGCCONT
24
23
22
21
20 BUF
19
18
17
SH1 PIN 25
SH2 AGC SH3 DC SHIFT OBSW 15 CLPOB CAM SH 14 XRS 16 AGCCLP
DMSW1 DIN 26 CDS CLP1 VCC2 27 DMSW2 BLK SW
VREF ICONT 28 LIN CLP
AGC CLP
CDS CLP2
N.C
13 OFFSET CAM DRV VIDC SHIFT CVSW 12
PBLK
LISW LIN/CH 29 CH SW
VB
OFFSET
GND2 30
LIN CH AMP VSI
2
VISW 1 3
VRT 11 VIDEO DRV VRT DRV VRB DRV 10
VRT
RFCONT 31
VCENT VRB LOUT CLP VB
VRB
LOSW PBRFC 32 VS2 CL GCA VCENT
VCENT VB
9
VCC3
MODE CONTROL & POWER SAVE CONTROL 1 2 3 4 5 6 7 8
LOUTCLP
MODE2
MODE1
GND3
N.C
PS
-2-
DRVOUT
MODE3
CXA2056Q
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
(VCC1, 2, 3 = 3V) Description Camera and video signal selector. Composite video signal and high-band chroma/low-band chroma signal selector of the video signal. For details on the selection conditions for each mode, refer to the diagram of the Electrical Characteristics Measurement Circuit. Power saving mode. No connection; normally ground. GND Ground.
1
MODE1
75k 50k
2
MODE2
1
145
VTH = 1.5V
2 3 4 10A
1.5V
50k
3
MODE3
4 5 17 6 23 30
PS N.C GND3 GND1 GND2
38k 100A 100A
1k
7
LOUTCLP
Approx. 1.1V
1.1V 22k
12k
7 145 90k
2A
Capacitor connection for LOUTCLP which clamps the output minimum level in modes which pass the composite video signal. (Recommended value: 0.1F)
-3-
CXA2056Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
IOFFSET
25A
200A
25A
8
* Camera mode (CAM) VRB to VRB + 100mV * Composite video mode (LIN) VRB + 50mV = approx. DRVOUT 1.4V * Chroma mode (CH, CL) Center voltage = (VRT - VRB)/2 = approx. 1.85V
0 to 50A
SW1
Driver output for A/D converter capable of DC coupling. Dynamic range = 1Vp-p Mode SW1 SW2 SW3
2k
SW1
50A VRT = 2.35V 5090 1.85V 4072 30k 1.4 509 SW3 VRB = 1.35V 100A
50A
ICONT 3.2 to 6.4mA 2.4mA 145 30k SW2 SW1
CAM LIN
1 0
0 1 1
0 1 0
CH, CL 0
8
VIDEO signal 10p CAM signal 48
0: Open 1: Closed
9 20 27
VCC3 VCC1 VCC2
VCC
Power supply. 1.35V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F) 2.35V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F)
200 16.5k 145
10
VRB
1.35V
1.35V
10 13.5k 110A 30k
30k 6.5k 145 2.35V 11 23.5k 55 200 55 220
11
VRT
2.35V
-4-
CXA2056Q
Pin No.
Symbol
Pin voltage
50k
Equivalent circuit
50k
Description
30k
2k
Controls the output offset during camera mode. When 3V: VRB When 1.5V: VRB + 100mV When 0V (preset mode): VRB + 35mV
12
OFFSET
1.5 to 3V & 0V
1.85V 1.5k 3k 25k 30k VRB
50A 145 50A 50A 12
30k
Camera signal preblanking pulse input.
145
VTH = 1.85V 13 PBLK
1.85V
30k 13 30k 50A
Active: Low
Active when Low only during camera mode. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to VRB.
40A
770A 145
VTH = 0.68V 14 XRS
0.68V
24k 14
Camera signal sample-and-hold pulse input.
7k Sampling 97
30k
VTH = 1.5V 15 CLPOB
1.5V
30k 145 15 30k
Active: Low
50A
Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier.
-5-
CXA2056Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
5k
5k
3k
145
16
AGCCLP
Approx. 1.3V
145
16
AGC clamp capacitor. (Recommended value: 0.1F)
50k 3k
3.3k 3.3k 145
AGC gain control.
18
18
AGCCONT
1.5 to 3.0V
3.4k 2.14V 3.4k
3.4k 2.29V
3.4k
When 1.5V: -1dB (Minimum gain) When 3.0V: +31.5dB (Maximum gain)
ICONT 300A 100A 300A 100A
200A
200A
100A
19
DIN input CCD signal CCDLEVEL black level: approx. 2.2V
19 500
Enables monitoring of the SH3 output camera signal.
340
21
SHP VTH = 0.65V
20A 36k
365A 145 21
Preset level sampleand-hold pulse input.
0.65V
22 10k
22
SHD
Sampling
Data level sampleand-hold pulse input.
-6-
CXA2056Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VTH = 1.5V 24 CLPDM
1.5V
30k 145 24 30k
Clamp pulse used to clamp the dummy pixel portion of the input CCD signal.
Active: Low
50A
145 25
15A 15A 23k 14k 7k
2k
25 26
PIN DIN
Black level: approx. 2.1V
26
145
CCD signal input.
2k
200A 50A
15k 145 2.25V 28 6k 45k 6k
DRVOUT output waveform rise time control. When 1.5V: Maximum rise time When 3V: Minimum rise time
28
ICONT
1.5 to 3V
100A
25A 145 29
29
LIN/CH
Clamp potential during LIN mode: approx. 1.46V During CH mode: approx. 1.85V
1.85V
50A 10k
54k 11.5k 30k
Common input for the composite video signal (LIN) and highband chroma signal (CH).
18.5k
CH mode 200A 100A
LIN mode 2A
VRB + 50mV
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CXA2056Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
27k 145 54k 31
42k
Gain control for the low-band chroma signal (CL). When 0.3V: -4dB (Minimum gain) When 2.7V: +12.5dB (Maximum gain)
31
RFCONT
0.3 to 2.7V
27k
2k 2.9V 145 32 7.8k 10k 58k
32
PBRFC
Approx. 1.9V
22k 1.9V 38k 100A
200A 10k
200A
Low-band chroma signal (CL) input.
25A
-8-
CXA2056Q
Electrical Characteristics Item Camera mode Symbol IDC Conditions AGCCONT = 1.5V, open between VRT and VRB MODE1 = 3V, MODE2 = 0V MODE3 = 0V, PS = 3V, ICONT = 3V Open between VRT and VRB MODE1 = 0V, MODE2 = 0V, MODE3 = 0V, PS = 3V Open between VRT and VRB MODE1 = 0V, MODE2 = 3V, MODE3 = 3V, PS = 3V RFCONT = 0.3V, open between VRT and VRB MODE1 = 0V, MODE2 = 3V, MODE3 = 0V, PS = 3V PS = 0V DIN = 1s, 20mVp-p pulse AGCCONT = 3V, ICONT = 3V DIN = 1s, 500mVp-p pulse AGCCONT = 1.5V, ICONT = 3V A CON max. - A CON min.
(Ta=25C, VCC1, 2, 3 = 3V) Min. 30 Typ. 41.0 Max. Unit 53
LINE mode IDL
Current consumption CH mode
10
13.9
19 mA
IDCH
9
12.2
17
CL mode PS mode Maximum gain Minimum gain AGC
IPCL IDP A CONT max. A CONT min.
9 2 28.5 -- 27.1 800
12.2 3.4 31.3 -0.8 32.1 895
17 6 -- 1.4 -- -- mV dB
Range of gain AGC G variance Dynamic range maximum Dynamic range typical Offset high
AGCmax. AGCCONT = 3V DRVOUT output signal at saturation level D AGCTYP. D CAOF high CAOF low CAOF pre VRTO VRBO VR BLKOF LIN G CH G AGCCONT = 2V DRVOUT output signal at saturation level Camera mode OFFSET = 1.5V Camera mode OFFSET = 3.0V Camera mode OFFSET = 0V With a 400 load With a 400 load With a 400 load BLKOF (PBLK = 3V) - BLKOF (PBLK = 0V) LIN/CH = 15kHz, 500mVp-p, Sine wave + offset voltage LIN/CH = 3MHz, 500mVp-p, sine wave
900 80 -- 25 2300 1300 950 --10 2.5 2.5 9.5 -- 600
955 98 2 34 2342 1359 983 9 3.43 3.18 12.7 -4.0 815
-- -- 5 40 2400 1400 1050 23 4.5 4.5 dB -- -2.5 -- mV mV mV mV
DRV
Offset low Offset preset VRT DC level
REF
VRB DC level VRT - VRB Offset LIN mode gain CH mode gain
BLK
AMP
GCA
RFCONT = 2.7V CL mode RF maximum gain CONmax. 15kHz 80mVp-p sine wave RFCONT = 0.3V CL mode RF minimum gain CONmin. 15kHz 500mVp-p sine wave Dynamic range SH3 D DIN = 1s, 1Vp-p pulse -9-
SH3
CXA2056Q
Electrical Characteristics Measurement Circuit
GND GND GND GND GND GND
PL1
PL2
PL3
VCC1 3V
V7 1.5 to 3V
CCDLEVEL
AGCCONT
CLPDM
GND1
SHD
SHP
VCC1
24 C4 1F AC V8 VCC2 3V V9 1.5 to 3V AC V11 V10 0 to 3V
OFF ON
23
22
21
20
19
18
N.C
17 C7 0.1F PL4
GND
25
16
GND
26
15
GND GND
27
14
SW5 LIN/ CH GND2
28
13
GND
29
12
GND
V12 0.3 to 2.7V RFCONT
30
GND
31
GND
32
9
AC V13
C2 0.047F 1 2 3 4 5 6 7 8 R2 22
LOUTCLP
MODE3
L
SW1 HL V1 3V
SW2 HL V2 3V
SW3 HL V3 3V
SW4 H V4 3V C5 0.1
R1 10k C6 70pF V5 1.85V GND GND
GND
GND
GND
GND
GND
GND
SW1 SW2 SW3 SW5 SW4 L H H L H L L L L L L H H H H L H L L L H L - 10 - OFF ON OFF
DRVOUT
MODE1
MODE2
GND3
N.C
PS
MODE CAM
H
LIN
CL CH POWER SAVE
GND
PBRFC
VCC3
VCC3 3V
C8 4.7F
GND
SW6
OFF ON
GND
C1 0.1F
VRT 11 R3 400 VRB 10
C9 4.7F
GND
OFFSET
V6 0 to 3V
GND
ICONT
PBLK
PL6
GND
VCC2
XRS
PL5
GND
C3 1F
DIN
CLPOB
GND
PIN
AGCCLP
CXA2056Q
Measurement Timing Chart
1H 2s 2.5V PL4 (CLPOB) 1H 2s 2.5V PL1 (CLPDM) GND GND
2.5V PL6 (PBLK) GND 1H
V8 (DIN)
Different for each test
Equivalent to CCD signal black level V11 (CH) V13 (PBRFC) V10 + V11 (LIN)
Different for each test
PL2 (SHD) PL3 (SHP) PL5 (XRS)
2.5V GND
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CXA2056Q
Application Circuit
GND
GND
GND
GND
GND
CLPDM
SHD
SHP VCC
VAGCCONT 1.5 to 3V
CCDLEVEL
AGCCONT
CLPDM
GND1
SHD
SHP
VCC1
24 1F CCD
23
22
21
20
19
18
N.C
17
26
15
VCC
27
14
GND
1.5 to 3V VICONT
28 LIN/CH
13
LIN/CH 0.1F
29 GND2
12
GND
30
11
GND
31
10
4.7F PBRFC PBRFC 0.047F 32 9 VCC3 VCC
1
2
3
4
5
6
7
8
LOUTCLP
MODE3
DRVOUT
MODE1
MODE2
GND3
N.C
PS
VRB A/D A/D IN
22
0.1F 3V 3V 3V 3V
GND
GND
GND
GND
GND
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 12 -
GND
0.3 to 2.7V VRFCONT RFCONT
VRB
VRT
GND
VRT
GND
4.7F
OFFSET
VOFFSET 0 to 3V
GND
ICONT
PBLK
PBLK
GND
VCC2
XRS
XRS
GND
1F
DIN
CLPOB
CLPOB
25
16
GND
PIN
AGCCLP
0.1F
CXA2056Q
Description of Operation Refer to the Block Diagram. 1. Camera signal processing system Process the video signal processing pins as follows only in camera mode. <7> LOUTCLP ... Connect to GND. <29> LIN/CH ... Connect to GND. <31> RFCONT ... Connect to GND via the capacitor (approx. 0.01F). <32> PBRFC ... Connect to GND. Operating conditions The camera signal processing system operates when PS is High, MODE1 is Low, MODE2 is Low and MODE3 is High, or when PS is High, MODE1 is High, MODE2 is Low and MODE3 is Low. Camera signal processing system timing chart (when VCC = 3V)
Sig interval Precharge level CCD output OPB interval Idle transfer interval Sig interval
Signal level SHP SHD SH1 output SH2 output SH3 output CLPDM (2 dummy bit portion during the idle transfer interval) AGC output SH3 output - SH2 output x (- N) XRS CLPOB (2 during the OPB interval) CAMSH output 0.65V PBLK (10 during the idle transfer interval) Basic black level [3] 2.1V [1] [2] 2.1V
2s Black level
0.65V
2s
10s
BLK SW output 1.35V [4]
CAM DRVOUT output [5] Approx. VRB + 35mV when OFFSET = 0V Approx. VRB + 100mV when OFFSET = 1.5V Approx. VRB when OFFSET = 3V
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CXA2056Q
CDS (SH1, SH2, SH3): The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the sample-and-hold circuits for the pre-charge level; SH3 is the sample-and-hold circuit for the signal level. CDSCLP 1, 2: CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([1], [2]) of SH2 and SH3 in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for the signal level. AGC: AGC is the gain control amplifier for the camera signal. The gain can be varied from -1 to +31dB by adjusting the AGCCONT voltage control VAGCCONT from 1.5 to 3.0V. CAM SH: CAM SH is the sample-and-hold circuit for the camera signal processing system; it synchronizes the data readin timing for the external A/D. Sampling is possible according to the approximately 10ns sampling pulse width input to XRS. AGCCLP: The basic black level is set ([*3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin. DC SHIFT: This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black level is maintained at its previous setting. BLK SW: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential with VRB. ([4]) The signal is blanked when PBLK is low. CVSW: When the MODE1, 2, 3 and PS pin voltages are set so that the camera signal processing system operates, CVSW conducts the CAMDRV output (camera signal) into the DRVOUT. In addition, when these voltages are set so that the video signal processing system operates, CVSW conducts the VIDEODRV output (video signal) into the DRVOUT.
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CXA2056Q
OFFSET: OFFSET controls the CAMDRV output waveform black level offset. In the camera signal processing system camera mode, the OFFSET pin is enabled, permitting adjustment of the offset for the [OFFSET] and DRVOUT camera signals. ([5]) The voltage controlled by OFFSET is output as the CAMDRV output DC offset via AGCLP, DCSHIFT, CAMSH, and BLKSW. When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from VRB + 100mV to VRB. In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 35mV. CAMDRV: CAMDRV operates in the camera signal processing system mode, driving the external A/D. The current that flows to the last-stage amplifier in CAMDRV is controlled by applying voltage to the ICONT pin, making it possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The variable range is 1.5 to 3V, with 1.5V yielding the maximum and 3V yielding the minimum. The optimum rise time for the external A/D input capacitance can be selected. VRT DRV, VRB DRV: These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB, supplying 2.35V and 1.35V, respectively, when VCC is 3V. The IC's internal primary voltage is also generated on the basis of the VRT and VRB voltages. (VRB, VB, and VCENT) MODE CONTROL & POWER SAVE CONTROL: This block selects the mode governing the operation of the camera signal system and the video signal system through the selection of High and Low potential for the MODE1, 2, 3, and PS pins. The PS pin is the POWER SAVE pin; the power saving function operates when this pin is Low.
2. Video signal processing system Operating conditions The video signal processing system has three modes: LIN signal mode, CH signal mode and CL signal mode. The video signal processing system operates in LIN signal mode when PS is High, MODE1 is High, MODE2 is Low and MODE3 is High, or when PS is High, MODE1 is Low, MODE 2 is Low and MODE3 is Low. The video signal processing system operates in CH signal mode when PS is High, MODE1 is Low, MODE2 is High and MODE3 is High. The video signal processing system operates in CL signal mode when PS is High, MODE1 is Low, MODE2 is High and MODE3 is Low, or when PS is High, MODE1 is Low, MODE2 is High and MODE3 is High. Video signal processing system timing chart (when VCC = 3V) LIN mode
LIN/CH input 1.46V
* LIN CHAMP output (3.5dB) * DRVOUT output
1.4V
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CXA2056Q
LIN signal mode In LIN signal mode, LINSW and LOSW close, VISW is set to "1" and the video signal passes through CVSW. In addition, LINCHAMP, LINCLP, LOUTCLP, VIDC SHIFT, and VIDEO DRV all operate. LINCLP: LINCLP is an input clamp circuit that clamps the video composite signal sync level. The video composite signal is input to LIN/CH pin. LINCLP expands the input dynamic range, and sync tip clamps the input signal at VB (= 1.4V) to allow full input. The input level and frequency are respectively 571mVp-p (Max.) and DC is up to 7MHz. LINCHAMP: LINCHAMP amplifies the LIN signal and the CH (high-band chroma) signal; the gain is fixed at 3.5dB. VISW: VISW switches the LIN signal, the CH (high-band chroma) signal, and the CL (low-band chroma) signal. The signals are switched according to the mode selection. LOUTCLP: LOUTCLP is an output clamp circuit that clamps the sync level of the video composite signal that is output from VIDEO DRV. Because the VIDEO DRV output signal is fully input to the external A/D, the clamp level is set to VB (= 1.4V). If the sync level of the signal output from VIDEO DRV drops below VB, LOUTCLP operates: the LOUTCLP current flows so that the sync level equals VB, and the LOUTCLP potential is set. A clamping capacitor is connected to the LOUTCLP pin. VIDC SHIFT: VIDC SHIFT functions when LOUTCLP operates, following the LOUTCLP potential and forcing a DC shift of the VIDEO output signal sync level to VB. VIDEO DRV: VIDEO DRV outputs the video signal (LIN, CH, CL) to the external A/D in video signal processing mode.
- 16 -
CXA2056Q
CH (high-band chroma) signal mode In CH mode, CHSW closes, VISW is set to "2" and the video signal passes through CVSW. In addition, LINCHAMP and VIDEO DRV operate. VS1: The video high-band chroma signal is input to the LIN/CH pin. VS1 expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 1.85V to allow full input. The input level and frequency of the CH signal are respectively 470mVp-p (Max.) and from 1 to 7MHz. VCENT: VCENT is a DC bias circuit that operates when the CH signal is output to VIDEO DRV. The DC bias potential is generated from VRT and VRB, and is set to 1.85V. CH mode
LIN/CH input
1.85V
* LINCH AMP output (3.5dB) * DRVOUT output
1.85V
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CXA2056Q
CL (low-band chroma) signal mode In CL mode, VISW is set to "3" and the video signal passes through CVSW. In addition, CLGCA and VIDEO DRV operate. VS2: The video low-band chroma signal is input to the PBRFC pin. VS2 expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 1.9V to allow full input. The input level and frequency of the CH signal are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz. CLGCA: The CLGCA amplifier controls the gain of the CL signal input to the PBRFC pin. The gain can be varied from -4 to +12.5dB by adjusting the RFCONT voltage from 0.3 to 2.7V. The phase of the CLGCA output waveform is reversed in DRVOUT. VCENT: VCENT is a DC bias circuit that operates when the CL signal is output to VIDEO DRV. The DC bias potential is generated from VRT and VRB, and is set to 1.85V. CL mode
PBRFC input
1.9V
* CLGCA output (-4 to +12.5dB) * DRVOUT output
1.85V
- 18 -
CXA2056Q
Example of Representative Characteristics
CAM mode AGCCONT control supply voltage characteristics VAGCCONT vs. Gain
35 30 Tc = 27C VCC = 3V VCC = 3.15V VCC = 3.3V
Gain [dB]
20
10
0 -4 1.5 2.0 2.5 VAGCCONT [V] 3.0 3.3
CAM mode OFFSET control supply voltage characteristics VOFFSET vs. OFFSET
115 Tc = 27C 100
80
OFFSET [mV]
60
40
20 VCC = 3.3V VCC = 3V 0 1.0 2.0 VOFFSET [V] 3.0 3.3
(VRB =) 0
CL mode RFGCA gain control supply voltage characteristics VRFCONT vs. Gain
Tc = 27C VCC = 3V VCC = 3.15V VCC = 3.3V 25
Gain [dB]
20
10
0
-5 0 1.0 2.0 VRFCONT [V] 3.0 3.3
- 19 -
CXA2056Q
CAM mode AGCCONT control temperature characteristics AGCCONT vs. Gain
35 30 VCC = 3.0V Tc = -20C Tc = +27C Tc = +75C
Gain [dB]
20
10
0 -4 1.5 2.0 2.5 3.0 AGCCONT [V]
CAM mode OFFSET control temperature characteristics VOFFSET vs. OFFSET
VCC = 3.0V Tc = -20C Tc = +27C Tc = +75C 150
OFFSET [mV]
100
50
(VRB =) 0 0 1.0 2.0 3.0 VOFFSET [V]
CL mode RFGCA gain control temperature characteristics VRFCONT vs. Gain
VCC = 3V Tc = -20C Tc = +27C Tc = +75C 25
Gain [dB]
20
10
0 -5 0 0.3 1.0 2.0 VRFCONT [V] 2.7 3.0
- 20 -
CXA2056Q
CAM mode maximum signal amplitude temperature characteristics (Max. gain) Tc vs. Vout
VCC = 3.0V, AGCCONT = 3.0V Input amplitude DIN = 28mVp-p Input amplitude DIN = 24mVp-p Input amplitude DIN = 21mVp-p 0.9 Gain temperature characteristics from -20 to +100C DIN = 28mVp-p +0 30.99 -0.23 dB 0.8
CAM mode maximum signal amplitude temperature characteristics (Min. gain) Tc vs. Vout
VCC = 3.0V, AGCCONT = 1.5V Input amplitude DIN = 870mVp-p Input amplitude DIN = 800mVp-p Input amplitude DIN = 750mVp-p Input amplitude DIN = 700mVp-p Input amplitude DIN = 600mVp-p
Vout [Vp-p]
1.0 30.99dB 30.99dB DIN = 24mVp-p +0 31.41 -0.38 dB 0.9 31.41dB 31.41dB DIN = 21mVp-p +0 31.45 -0.33 dB 0.8 31.45dB 31.45dB 31.12dB 31.03dB 30.76dB
Vout [Vp-p]
DIN = 870mVp-p
DIN = 800mVp-p 0.7 DIN = 750mVp-p DIN = 700mVp-p 0.6 DIN = 600mVp-p 0.53 -20
0.75 -20
0
50 Tc [C]
100
0
50 Tc [C]
100
LIN, CH mode LINCHAMP gain temperature characteristics Tc vs. Gain
VCC = 3.0V LIN mode CH mode 4
LIN, CH mode LINCHAMP gain supply voltage characteristics VCC vs. Gain
Tc = 27C CH mode LIN mode
Gain [dB]
3.5
3 -20
0 Tc [C]
75
Gain [dB]
4
3.5
3 3 3.15 VCC [V] 3.3
- 21 -
CXA2056Q
CH, LIN, CL mode input pin DC voltage temperature characteristics Tc vs. DCIN
1.9 1.85 1.8 1.75 CH mode CL mode
DCIN
1.7 VCC = 3.0V 1.65 1.6 1.55 1.5 1.45 1.4 -20 0 LIN mode 20 40 60 80
Tc [C]
1.9 1.85
CH, LIN, CL mode DRVOUT output DC voltage temperature characteristics Tc vs. DCOUT
CL mode CH mode
1.8 1.75
DCOUT
1.7 VCC = 3.0V 1.65 1.6 1.55 1.5 1.45 1.4 -20 0 LIN mode 20 Tc [C] 40 60 80
VRT, VRB, VRT - VRB temperature characteristics Tc vs. VRT, VRB, VRT - VRB
2.4 VRT 2.2
VRT, VRB, VRT - VRB [V]
2.0 VCC = 3.0V 1.8 1.6 1.4 1.2 1.0 0.8 -20 VRT - VRB VRB
0
20 Tc [C]
40
60
80
- 22 -
CXA2056Q
-30
LIN mode 2nd/3rd harmonic distortion temperature characteristics Tc vs. 2nd/3rd harmonic distortion
2nd/3rd Harmonic Distortion [dB]
VCC = 3.0V f = 5MHz 2nd: out = 0.9Vp-p 3rd: out = 0.9Vp-p
CH mode 2nd/3rd harmonic distortion temperature characteristics Tc vs. 2nd/3rd harmonic distortion
-30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -20 0 20 Tc [C] 40 60 80 3rd: out = 0.75Vp-p 2nd: out = 0.75Vp-p 2nd: out = 0.9Vp-p VCC = 3.0V f = 5MHz 3rd: out = 0.9Vp-p
2nd/3rd Harmonic Distortion [dB]
-35 -40 -45 -50 -55 -60 -65 -70 -75
3rd: out = 0.75Vp-p 2nd: out = 0.75Vp-p
-80 -20
0
20 Tc [C]
40
60
80
CL mode 2nd/3rd harmonic distortion temperature characteristics (Min. gain) Tc vs. 2nd/3rd harmonic distortion
-30
CL mode 2nd/3rd harmonic distortion temperature characteristics (Max. gain) Tc vs. 2nd/3rd harmonic distortion
-30
2nd/3rd Harmonic Distortion [dB]
-40 -45 -50 -55 -60 -65 -70 -75
2nd/3rd Harmonic Distortion [dB]
-35
VCC = 3.0V, RFCONT = 0.3V f = 700kHz 2nd: out = 0.75Vp-p 3rd: out = 0.75Vp-p 2nd: out = 0.3Vp-p 3rd: out = 0.3Vp-p
-35 -40 -45 -50 -55 -60 -65 -70 -75
VCC = 3.0V, RFCONT = 2.7V f = 700kHz 3rd: out = 0.75Vp-p 2nd: out = 0.75Vp-p
3rd: out = 0.3Vp-p
2nd: out = 0.3Vp-p
-80 -20
0
20 Tc [C]
40
60
80
-80 -20
0
20 Tc [C]
40
60
80
- 23 -
CXA2056Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
- 24 -
0.50
(8.0)

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