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TC9447F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9447F
Single-Chip Audio Digital Signal Processor
The TC9447F is a single-chip audio digital signal processor incorporating an AD/DA converter. The built-in program memory (ROM) can contain a range of application programs for concert hall acoustic field simulation, for digital filters such as equalizers, and for dynamic range control. In addition, the device includes 64kb of data delay RAM, making external RAM unnecessary.
Features
* * * * * * Incorporates a 1-bit -type AD converter (two channels). THD: -82dB, S/N ratio: 95dB (typ.) Incorporates a 1-bit -type DA converter (four channels). THD: -85dB, S/N ratio: 100dB (typ.) A 10-dB attenuator is built into the DA converter output block (two channels only) Each port has a digital input/output (three lead-type) A built-in self-boot function automatically sets the coefficients and register values at initialization. Boot ROM Data bus Multiplier/adder Accumulator Program ROM Coefficient RAM Coefficient ROM Offset RAM Data RAM Operation speed * * * * : 1024 words x 18 bits : 24 bits : 24 bits x 16 bits + 43 bits 43 bits : 43 bits (sign extension: 4 bits) : 1024 words x 32 bits : 320 words x 16 bits : 256 words x 16 bits : 64 words x 16 bits : 256 words x 24 bits : 44ns (510-step (approx) operation per cycle at fs = 44.1 kHz) The DSP block specifications are as follows: Weight: 1.57g (typ.)
Interface buffer RAM : 32 words x 16 bits Incorporates data delay RAM. Delay RAM : 4096 words x 16 bits (64 kbits) The microcontroller interface can be selected between Standard Transmission mode and I2C bus mode. CMOS silicon structure supports high speed. The package is a 100-pin flat package.
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Pin Connection
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TC9447F
Block Diagram
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TC9447F
Pin Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25~29 30 31 32 33~40 41 42 43 44 45 46 47 Symbol ECKO ECKI GNDX GNDAL AOL VRL VDAL VDAR VRR AOR GNDAR GNDAC AOC AOCT VRC VDAC VRO VRI VDAS VRS AOST AOS GNDAS GND TP0~TP4 VDD VDDR GNDR TP5~TP12 FS CKO0 CKO1 GND TP13 MCK VDD I/O O I O O O O O I O O O O O O O O O O I I I I Function Amp output pin for external clock input Amp input pin for external clock input Ground pin for oscillator circuit Ground pin for DAC L channel DAC analog signal output pin (L channel) DAC reference voltage pin (L channel) Power pin for DAC L channel Power pin for DAC R channel DAC reference voltage pin (R channel) DAC analog signal output pin (R channel) Ground pin for DAC R channel Ground pin for DAC C channel DAC analog signal output pin (C channel) DAC analog signal output pin with attenuator (C channel) DAC reference voltage pin (C channel) Power pin for DAC C channel Reference voltage pin for attenuator (buffer output) Reference voltage pin for attenuator (buffer input) Power pin for DAC S channel DAC reference voltage pin (S channel) DAC analog signal output pin with attenuator (S channel) DAC analog signal output pin (S channel) Ground pin for DAC S channel Ground pin Test pins (leave open) Power pin Power pin for DLRAM Ground pin for DLRAM Test pins (leave open) Clock output pin (1 fs) Clock output pin 0 Clock output pin 1 Ground pin Test pin (leave open) MCK clock output pin (256 fs/512 fs/ (384/768 fs) ) Power pin Test pin (leave open) Master clock switching pin Execution step switching pin 0 Execution step switching pin 1 Reset pin Schmitt input Schmitt input Schmitt input Schmitt input Push-pull output Pulled-down resistor (with on/off switching function) Remarks
48~53 TP14~TP19 54 55 56 57 CKS STEP0 STEP1
RST
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Pin No. 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Symbol VDD SYNC ELRO ELRI EBCO EBCI DIN DOUT EM0 EM1 IFF0 IFF1 IFF2 GND
CS
I/O I I I I I I O I I I I I I I I/O O O O O I I I I I I I I O Power pin Program SYNC signal input pin
Function
Remarks
Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input Push-pull output Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input
LR clock input pin for serial data output LR clock input pin for serial data input Bit clock input pin for serial data output Bit clock input pin for serial data input Serial data input pin Serial data output pin De-emphasis setting pin 0 De-emphasis setting pin 1 Interface flag pin 0 Interface flag pin 1 Interface flag pin 2 Ground pin Microcontroller interface chip select signal input pin Microcontroller interface data shift clock input pin Microcontroller interface data2input pin (Data input/output pin when I C bus selected) Microcontroller interface data output pin 2 (Leave open when I C bus selected.) Microcontroller interface operation flag output pin Microcontroller interface acknowledge output pin Microcontroller interface error flag output pin Microcontroller interface I C bus switching pin Self-boot control pin Boot address setting pin 0 Boot address setting pin 1 Power pin Test pins. Use fixed to low level. Ground pin Ground pin for analog mode (ADC L channel) ADC analog signal input pin (L channel) ADC reference voltage pin (L channel) Power pin for analog mode (ADC L channel) Power pin for analog mode (ADC R channel) ADC reference voltage pin (R channel) ADC analog signal input pin (R channel) Ground pin for analog mode (ADC R channel) Ground pin for oscillator circuit Crystal oscillator connecting pin (input) Crystal oscillator connecting pin (output) Power pin for oscillator circuit
2
Schmitt input Schmitt input Schmitt input/ open drain output Push-pull output Open drain output Open drain output Open drain output
IFCK IFDI IFDO IFOK
ACK
ERR
I CS BOOT BA0 BA1 VDD
2
Schmitt input Schmitt input Schmitt input
84~87 TST0~TST3 88 89 90 91 92 93 94 95 96 97 98 99 100 GND VSAL LIN AVRL VDL VDR AVRR RIN VSAR GNDX XI XO VDX
Schmitt input
Pulled-down resistor (with on/off switching function)
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Operation
1. Pin operations
Pin No. 1 2 3~24 25~40 41 Symbol ECKO ECKI Omitted TP [0:12] FS Test pins (leave open) (TPx description is omitted.) 1 fs output Timing output pins. The output frequency is set from the microcontroller. (CMD-40h) CKOS0 2 1 0 0 42, 43 CKO [1:0] 1 0 0 1 0 1 0 1 0 1 CKO0 Fixed to L (initial value) fs2 fs4 fs8 fs16 fs32 fs64 fs128 1 1 0 1 CKOS1 2 1 0 0 0 1 0 1 0 1 0 1 CKO1 Fixed to L (initial value) fs2 fs4 fs8 fs16 fs32 fs64 1/2 XI or 1/2 ECKI Function Supplies an external clock to ECKI (for slave operations). When CKS pin = H, oscillation activated. When CKS = L, pulled down internally.
0 1 1
0
Master clock output pin. Output is validated/invalidated and the frequency is switched from the microcontroller. (CMD-4Dh) MCKE 46 MCK 0 1 Fixed to L Output valid (initial value) MCK MCKE 0 1 STEP1 don't care 256 fs 0 1 Source oscillation (XI/XO or ECKI) For testing MCK
Source oscillation selector pin CKS 54 CKS 0 1 Source Oscillation XI/XO pin ECKI/ECKO pin
Source oscillation frequency/ASP operation speed switching pins STEP1 STEP0 55, 56 STEP [1:0] 0 1 0 1 * Source Oscillation Frequency 512 fs 768 fs For testing No. of ASP Operation Steps 340/fs 510/fs
*: don't care
57 59 60 61 62 63
RST
Reset input (L at initialization) Program operation SYNC signal input pin. Valid when program is executing a slave operation. LR clock signal input pin for serial output data. Valid when serial data are output in a slave operation. LR clock signal input pin for serial input data. Valid when serial data are input in a slave operation. Bit clock signal input pin for serial output data. Valid when serial data are output in a slave operation. Bit clock signal input pin for serial input data. Valid when serial data are input in a slave operation.
SYNC ELRO ELRI EBCO EBCI
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Pin No. 64 65 Symbol DIN DOUT Function Serial input data signal input pin. Normally connected to internal register SI2 in ASP block. Serial output data signal output pin. Normally connected to internal register SO2 in ASP block. De-emphasis control pins EM1 0 EM0 0 1 0 1 De-Emphasis Settings De-emphasis off For fs = 48 kHz For fs = 44.1 kHz For fs = 32 kHz
66, 67
EM [1:0]
1
68~70 72 73 74 75 76 77 78
IFF [2:0]
CS
IFF control input pins. This functions the same as the microcontroller IFF [2:0] setting. The program uses the latest changes to the flags. Microcontroller interface pins Standard Transmission Mode (I CS = L) I CS
CS
2 2
IFCK IFDI IFDO IFOK
ACK ERR
I C Mode (I CS = H)
2
2
2
Transmit/receive mode switching (Standard Transmission mode/I C mode) Chip select (Control required) Transmit/receive clock MCU data input Monitor data output Acknowledge signal output Error flag signal output Internal operation confirmation flag signal output MCU data input/output Fixed to L output Fixed to HZ Chip select (Can be fixed to L)
IFCK IFDI IFDO
ACK
79
I CS
2
ERR
IFOK
For details, see 2, microcontroller interface below. Self-boot select pin BOOT 80 BOOT 0 1 Operation Does not boot at reset Boot at reset
Self-boot start address pins (at reset) BA1 0 BA0 0 1 0 1 Start Address 000h 001h 002h 003h
81, 82
BA [1:0]
1
84~87 88~97 98 99
TST [3:0] Omitted XI XO
Pins for inputting test settings. Use fixed to L. Connect the crystal oscillator (master mode). Setting CKS = L enables oscillation. Setting CKS = H pulls down XI/XO using the internal resistor.
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2. Microcontroller interface
(1) Standard transmission mode 1 When I2CS = L, data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care. (1-1) Setting registers
The registers are set by command data using the IFDI signal. The first byte is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB. The ACK signal is the acknowledge signal that the TC9447F returns to the microcontroller. Because the ACK signal is open drain output, it must be pulled up outside the pin. Data are loaded on the rising edge of the IFCK signal. Note that commands or data that must be switched on the SYNC signal, such as the RUN command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal. (1-2) Setting RAM (sequential)
The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written. The length of the data field following the RAM address bytes is 2 x n bytes. The address is automatically incremented by 1.
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(1-3) Setting RAM (ACMP mode)
In ACMP mode, the TC9447F does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must first be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC9447F is operating. This mode can suppress noise in almost all cases. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32 words. The format of IFB-RAM is similar to the format of the RAM in 1-2 above. The length of the data field is 2 x n bytes, where n 32. In ACMP mode, the IFOK pin outputs an ACMP operation end flag. When ACMP operations complete, the flag is set to Low (1) and is initialized at the next low chip select CS signal (2).
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(1-4) Monitor mode
Monitor mode is used to monitor the data bus or pointers. There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to the PC. After the command is issued, when the TC9447F loads data to the IFDO register (IFDOR), the IFOK pin signal is set to Low (see (1) above). Next, when the IFCK signal is sent, the data are output on the IFCK signal falling edge starting from the MSB. The data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. In cases where transfer must be interrupted, such as where only eight or 16 bits of the MSB side are required, monitoring can be interrupted at any time by setting the CS signal to High. When the CS signal goes High, the IFOK signal also goes High. When CS = H, all monitor circuits are initialized.
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(2) Standard transmission mode 2 When I2CS = L, data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care. (2-1) Setting registers
The registers are set by command data using the IFDI signal. The first byte is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB. The ACK signal is the acknowledge signal that the TC9447F returns to the microcontroller. As the ACK signal is open drain output, it must be pulled up outside the pin. The data are loaded on the rising edge of the IFCK signal. Note that commands or data that must be switched on the SYNC signal, such as the RUN command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal. (2-2) Setting RAM (sequential)
The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written. The length of the data field following the RAM address bytes is 2 x n bytes. The address is automatically incremented by 1.
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(2-3) Setting RAM (ACMP mode)
In ACMP mode, the TC9447F does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must first be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example, if a signal flow filter is designed as in the following diagram, unless the K1 to K5 data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data. Using ACMP mode can reduce the noise caused by updating coefficients while the TC9447F is operating. This mode can suppress noise in almost all cases. IFB-RAM is 32-word memory. Therefore, data can be updated at one time in units of up to 32 words. The format of IFB-RAM is similar to the format of the RAM in 2-2 above. The length of the data field is 2 x n bytes, where n 32. In ACMP mode, the IFOK pin outputs an ACMP operation end flag. When ACMP operations complete, the flag is set to Low (1) and is initialized at the next low chip select CS signal (2).
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TC9447F
(2-4) Monitor mode
Monitor mode is used to monitor the data bus or pointers. There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to the PC. After the command is issued, when the TC9447F loads data to the IFDO register (IFDOR), the IFOK pin signal is set to Low (see (1) above). Next, when the IFCK signal is sent, data are output on the IFCK signal falling edge from the MSB first. The data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. In cases where transfer must be interrupted, such as where only eight or 16 bits of the MSB side are required, monitoring can be interrupted at any time by setting the CS signal to High. When the CS signal goes High, the IFOK signal also goes High. When CS = H, all monitor circuits are initialized.
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(3) I2C bus mode When I2CS = H, data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. In I2C mode, the CS signal can be used fixed to L. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC9447F loads the IFDI data on the IFCK signal rising edge. When CS = H, the IFCK and IFDI signals are don't care. (3-1) Setting registers
The registers are set by command data using the IFDI signal. The first byte after the I2C address (32h) is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C format. The ACK pin cannot be used in I2C format. However, the acknowledge signal can be read by using data signals in I2C format. The data are loaded internally every two bytes. Note that commands or data that must be switched on the SYNC signal, such as the RUN command or the IFF flag, must be synchronized with the SYNC signal and loaded on that signal. (3-2) Setting RAM (sequential)
The RAMs are set by command data using the IFDI signal. The first byte after the I2C address (32h) is a command, which differs for each RAM. The next two bytes contain the start address for the RAM to be written to. The length of the data field following the RAM address bytes is 2 x n bytes. The address is automatically incremented by 1.
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TC9447F
(3-3) Monitor mode
Monitor mode is used to monitor the data bus or pointers. There are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (PC) and a mode where a loop counter (LC) is added to monitor conditions in addition to the PC. First, issue the monitoring command, which has no data. When the TC9447F loads data to the IFDO register (IFDOR), the IFOK pin signal is set to Low (see (1) above). Next, the I2C read command (ID = 33h) is issued, then when the IFCK signal is sent, the data are output on the IFCK signal falling edge starting from the MSB. The data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. In cases where transfer must be interrupted, such as where only eight or 16 bits of the MSB side are required, monitoring can be interrupted by sending the I2C end condition (set data level to H while the clock = H). After issuing a monitor command (50h~56h), be sure to perform a continuous read operation by issuing the I2C read command (ID = 33h). (3-4) MCU does not write data by ACMP mode at I2C bus controlling.
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(4) IFOK pin description The IFOK signal has the following three functions. (4-1) ACMP mode end flag output After the completion of a RAM data update with CRAM-ACMP (CMD: 47h) or OFRAM-ACMP (CMD: 49h), the IFOK pin goes Low. Setting the CS signal to Low changes the IFOK signal from Low to High. Example:
(4-2)
Loading end flag output in Monitor mode When monitoring using the bus monitor command (CMD: 50h), for example, after data are loaded to the internal register under the specified conditions, the IFOK signal goes Low. In monitor mode, when the CS signal goes High, the IFOK signal also goes High. Example:
(4-3)
Mute end flag output for digital filter (DF) block When using a command to control the DF block mute on/off (CMD: 36h, bit 5), the mute end flag is output from the IFOK pin after the mute operation completes. Example:
Note 1: At power on, the IFOK pin output is undefined. When the CS signal goes Low, the IFOK signal goes High.
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3. Control commands
The following table lists the control commands that can be used from the microcontroller. (1) Control commands
Table 1 Control commands
Command TIMING BOOT DAC SIO RUN-MUTE MSEQ CRAM CRAM-ACMP OFRAM OFRAM-ACMP IFF MONI-PC MONI-LC MISC M-RST MONI-DB MONI-CP MONI-OFP MONI-DP MONI-AR MONI-CRP MONI-SR Code 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h R W R/W Timing Self-boot ROM start address DAC output attenuator SIO setting Program execution, mute Sequential RAM CRAM CRAM (ACMP mode) OFRAM OFRAM (ACMP mode) Interface flag (IFF) Monitor (PC conditions) Monitor (LC conditions) Others (Prohibited) Initialization DB monitor CP monitor OFP monitor DP monitor AR monitor CRP monitor SR monitor Enable Description RAM Sequential Transfer Sync With/Async to Sync Signal Async Async Async Async Sync (Note 2)
Sync (RUN)/Async (STOP) Sync (RUN)/Async (STOP) Async Sync (RUN)/Async (STOP) Async Sync Async Async Async Async Async Async Async Async Async Async Async (Note 2)
Note 2: The command which is "Sync" in the transfer Sync with Sync signal needs to set the CS = H section to a minimum of 1 fs more until it transmits the following command.(It needs more than 22.68 s at fs = 44.1 kHz)
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(2) Control commands
0100 0000 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND-40h (Timing) D15 D14
Unas- CKOS1 CKOS1 CKOS1 CKOS0 CKOS0 CKOS0 SYPD SYD1 SYD0 SYPA SYA1 SYA0 SYPS SYS1 SYS0 signed 2 1 0 2 1 0 Name Description Value 0 1 0 SYD [1:0] ASP digital block SYNC signal input switching 1 2 3 SYPA Analog block sync polarity switching 0 1 0 SYA [1:0] Analog block SYNC signal input switching 1 2 3 SYPS Overall system sync polarity switching 0 1 0 SYS [1:0] SYNC circuit input switching 1 2 3 0 1 2 CKOS1 CKO1 pin output selection [2:0] 3 4 5 6 7 0 1 2 CKOS0 CKO0 pin output selection [2:0] 3 4 5 6 7 Operation ASP program starts on falling edge ASP program starts on rising edge (initial value) Signal after SYNC output (initial value) SYNC pin ELRI pin ELRO pin Digital filter (DF) program starts on falling edge (initial value) Digital filter (DF) program starts on rising edge Signal after SYNC output (initial value) SYNC pin ELRI pin ELRO pin Operates at polarity for SYPD, SYPA settings above (initial value). Reverses all polarities for SYPD, SYPA settings above. Internal SYNC signal (initial value) SYNC pin ELRI pin ELRO pin Fixed to L (initial value) fs2 fs4 fs8 fs16 fs32 fs64 Outputs XI or ECKI clock divided by 2 Fixed to L (initial value) fs2 fs4 fs8 fs16 fs32 fs64 fs128
SYPD Digital block sync polarity switching
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COMMAND-41h (BOOT) D15 0 D14 0 0100 0001 D13 0 D12 0 D11 0 D10 0 D9 D8 D7 D6 D5 BTA5 D4 BTA4 D3 BTA3 D2 D1 D0 BTA0
BTA9 BTA8
BTA7 BTA6
BTA2 BTA1
Name BTA [9:0]
Description Self-boot ROM start address
Value
Operation
000h ~ Starts self-boot operation from specified address. 3FFh
COMMAND-42h (DAC) D15 0 D14 0
0100 0010 D13 0 D12 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 D3 D2 D1 D0
ATTC4 ATTC3 ATTC2 ATTC1 ATTC0
ATTS4 ATTS3 ATTS2 ATTS1 ATTS0
Name
Description
Value 00h ~ 1Fh 00h ~ 1Fh
Operation 00h 0dB, 01h = -1dB, 02h = -2dB, ..., 15h~1Fh = - (Initial value = 1Fh=) 00h 0dB, 01h = -1dB, 02h = -2dB, ..., 15h~1Fh = - (Initial value = 1Fh = -)
ATTC DAC C channel attenuator value
ATTS DAC S channel attenuator value
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COMMAND-43h (SIO) D15 CHSI D14 0 0100 0011 D13 ISLT 1 D12 ISLT 2 D11 IBCS 1 D10 IBCS 0 D9 IFMT 1 Value 0 1 0 ISLT [1:0] Number of serial input slots 1 2 3 0 IBCS Serial input bit length [1:0] 1 2 3 0 IFMT Serial input format [1:0] 1 2 3 0 CHSO Serial output switching [1:0] 1 2 3 0 OSLT Number of serial output slots [1:0] 1 2 3 0 OBCS Serial output bit length [1:0] 1 2 3 0 OFMT Serial output format [1:0] 1 2 3 D8 D7 D6 D5 D4 D3 D2 D1 D0
IFMT CHSO CHSO OSLT OSLT OBCS OBCS OFMT OFMT 0 1 0 1 0 1 0 1 0 Operation ADC SI0 register, DIN pin SI1 register (initial value) ADC SI1 register, DIN pin SI0 register 16 bits/channel (initial value) 20 bits/channel 24 bits/channel 32 bits/channel 16 bits (initial value) 18 bits 20 bits 24 bits Pads from the beginning (initial value) Pads from the end I S format SO0 register DOUT pin SO1 register DOUT pin SO2 register DOUT pin (initial value = 2) 16 bits/channel (initial value) 20 bits/channel 24 bits/channel 32 bits/channel 16 bits (initial value) 18 bits 20 bits 24 bits Pads from the beginning (initial value) Pads from the end I S format
2 2
Name
Description
CHSI Serial input switching
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COMMAND-44h (RUN-MUTE) D15 0 D14 0 0100 0100 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 RUN D6 0 D5 D4 D3 D2 D1 D0
DF DA SO- OMUTE OMUTE MUTE MUTE IMUTE MUTE 1 0 Operation
Name RUN
Description ASP program execution
Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Stops program (initial value). Runs program. Mute off Mute on (initial value) Mute off Mute on (initial value) Mute off Mute on (initial value) Mute off Mute on (initial value) Mute off Mute on (initial value) Mute off Mute on (initial value)
DF DF block mute MUTE DA DAC mute (all four channels) MUTE IMUTE ASP block input mute (SI0, SI1) ASP block serial output mute (Mutes SODOUT output whichever register is MUTE selected in CHSO.)
OMUTE ASP block output mute (SO1) 1 OMUTE ASP block output mute (SO0) 0
COMMAND-45h (MSEQ) D15 0 D14 0
0100 0101 D13 0 D12 0 D11 0 D10 0 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
Name MSA [9:0]
Description Sequential RAM address
Value
Operation
000h Set sequential RAM. ~ Enable a sequential write to RAM. 3FFh
COMMAND-46h (MSEQ) D15 D15 D14 D14
0100 0110 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Name D CRAM [15:0]
Description
Value
Operation
0000h Set CRAM. ~ Enable a sequential write to RAM. FFFFh
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COMMAND-47h (CRAM-ACMP) D15 D15 D14 D14 0100 0111 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Name
Description
Value 0000h ~ Set CRAM in ACMP mode. FFFFh
Operation
D CRAM-ACMP [15:0]
COMMAND-48h (OFRAM) D15 D15 D14 D14
0100 1000 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Name D OFRAM [15:0]
Description
Value
Operation
0000h Set OFRAM. ~ Enable a sequential write to RAM. FFFFh
COMMAND-49h (OFRAM-ACMP) D15 D15 D14 D14
0100 1001 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
D13 D13
Name
Description
Value 0000h ~ Set OFRAM in ACMP mode. FFFFh
Operation
D OFRAM-ACMP [15:0]
COMMAND-4Ah (IFF) D15 0 D14 0
0100 1010 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 IFF2 D1 IFF1 D0 IFF0
D13 0
Name IFF [2:0]
Description Interface flag (IFF)
Value 0 1 IFFn = 0 (initial value) IFFn = 1
Operation
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COMMAND-4Bh (MONI-PC) D15 D14 0100 1011 D12 0 D11 0 D10 0 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
D13 0
I2COS I2COS 1 0 Name
Description
Value 0h ~ 3h
Operation Set the data byte length when monitoring in I C mode. (3 = 3 byte, 2 = 2 byte, 1 or 0 = 1 byte)
2
2 I2COS Monitor data length in I C mode [1:0]
A [9:0]
Monitor conditions (PC: program counter)
000h ~ Set the PC conditions when monitoring. 3FFh
COMMAND-4Ch (MONI-LC) D15 0 D14 0
0100 1100 D12 0 D11 0 D10 LCE D9 LCS D8 D7 D6 LCA6 D5 LCA5 D4 LCA4 D3 LCA3 D2 LCA2 D1 LCA1 D0 LCA0
D13 0
LCDE LCA7
Name LCE
Description Adds the LC (loop counter) value to the monitor conditions. LC selection
Value 0 1 0 1 0
Operation Does not add LC value to the conditions (initial value). Adds LC value to the conditions. Compares with LC0 value. Compares with LC1 value. After a match, does not change the value to be compared with the LC. After a match, automatically decrements by 1 the value to be compared with the LC. Set the value to be compared with the LC.
LCS
LCDE Automatic LC decrement
1 00h ~ FFh
LCA [7:0]
Monitor conditions (LC)
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COMMAND-4Dh (MISC) D15 0 D14 0 0100 1101 D12 0 D11 0 D10 SIS D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D13 0
SOS ERDET ZST
DP7F SYRC SYRO MCKE MCKS DLSEP DLAC4
Name SIS Serial input
Description
Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Operation Master (LRCK = FS, BCK = FSxx) (initial value) Slave (LRCK = ELRI, BCK = EBCI) Master (LRCK = FS, BCK = FSxx) (initial value) Slave (LRCK = ELRO, BCK = EBCO) Invalid Valid (initial value) 2-cycle access 1-cycle access (initial value) 256 words (initial value) 128 words Does not initialize. Initializes (initial value). Does not initialize. Initializes (initial value). Fixes to L Output (initial value) 256 fs When STEP1 pin = 0, outputs source oscillation (initial value). When STEP1 pin = 1, used for testing. Does not use table. Uses 2-k word area as the table (initial value). One access/6 cycles (initial value) One access/4 cycles
SOS
Serial output
ERDET Error detection Switches to access CROM using LOG-LIN adjustment.
ZST
DP7F DATA-RAM 128/256 word switching
SYRC Initializes CP at each SYNC.
SYRO Initializes OFP at each SYNC
MCKE MCK pin output enable
MCKS MCK pin output switching
1 0 1 0 1
DLSEP Delay RAM table area switching
DLAC4 Delay RAM access method
COMMAND-4Fh (M-RST) D15 MRST D14 0
0100 1111 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
D13 0
Name
Description
Value 0 1 Does not initialize.
Operation
MRST Initialization from the microcontroller
Initializes (after initialization, automatically set to 0).
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COMMAND-50h (MON-DB) 0101 0000 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D3 D2 D1 D1 D0 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
Name
Description
Value 000000h~FFFFFFh
Operation Reads data bus on the condition CMD: 4Bh, 4Ch.
D Data bus monitor [23:0]
COMMAND-51h (MON-CP)
0101 0001 D8 D7 D6 D5 D4 D3 D2 D1 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CP8 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0
Name CP [8:0]
Description CP monitor
Value 000000h~00013h
Operation Reads CP on the condition CMD: 4Bh, 4Ch.
COMMAND-52h (MON-OFP)
0101 0010 D8 0 D7 0 D6 D5 D4 D3 D2 D1 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFP OFP OFP OFP OFP OFP 0 5 4 3 2 1 0 Operation
Name OFP [5:0]
Description OFP monitor
Value 000000h~00003h
Reads OFP on the condition CMD: 4Bh, 4Ch.
COMMAND-53h (MON-BP)
0101 0011 D8 D7 D6 D5 D4 D3 D2 D1 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0
BP BP BP BP BP BP BP BP BP BP BP BP 11 10 9 8 7 6 5 4 3 1 2 0 Operation
Name
Description
Value 000000h~000FFFh
BP BP monitor [11:0]
Reads BP on the condition CMD: 4Bh, 4Ch.
COMMAND-54h (MON-AR)
0101 0100 D8 D7 D6 D5 D4 D3 D2 D1 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0
AR AR AR AR AR AR AR AR AR AR AR AR 11 10 9 8 7 5 4 3 1 6 2 0 Operation
Name
Description
Value 000000h~000FFFh
AR Delay RAM address [11:0] monitor
Reads delay RAM address on the condition CMD: 4Bh, 4Ch.
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COMMAND-55h (MON-CRP) 0101 0101 D8 D7 D6 D5 D4 D3 D2 D1 D0
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CRP CRP CRP CRP CRP CRP CRP CRP CRP 0 8 7 6 5 4 3 2 1 0 Operation
Name CRP [8:0]
Description CRP (LIN-LOG adjustment pointer) monitor
Value 000000h~0001FFh
Reads CRP on the condition CMD: 4Bh, 4Ch.
COMMAND-56h (MON-SR)
0101 0110 D8 D7 D6 D5 D4 D3 D2 D1 D0 SF
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0
LI LG OV OV RD RD LRF GF3 GF2 GF1 GF0 LG LI 1E 0E 24 16 V1F V0F ZF Operation Reads SR on the condition CMD: 4Bh, 4Ch.
Name SR
Description SR (status register) monitor
Value
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4. Self-boot function description
(1) Self-boot function The TC9447F supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various modes to be set later. The microcontroller interface circuit supports two formats: I2C and the original mode. However, the boot must be executed in Standard Transmission (the original) mode.
Figure 1 Self-boot system
(2) Boot ROM format The following shows the breakdown of the 18 bits.
00 01 10 11 Data that are being sent Command Final data (after the data are sent, the CS signal is set to "H"). Jump address (jump to any address in the self-boot ROM).
Figure 2 Boot ROM Format and Example
Boot mode completes when the address reaches 3FFh, the maximum value. Therefore, for the final address, write JMP 3FFh (data = 303FFh).
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(3) Self-boot operation Self-boot operations support two modes: one for use at reset and one for setting the microcontroller. The modes can be used in combination. (3-1) Self-boot operation at reset To enter this mode, set the BOOT pin to High, then set the RST pin from Low to High. The 2048 fs period (46.4 ms when fs = 44.1 kHz) after a reset release is a wait period (for power-on reset). The boot operation starts at the end of this period. When switching the setting according to the application, specify the start address using the BA [1:0] pin. At addresses 000h to 002h, set jump addresses. The data setting speed is one word of SBROM per 1 fs. As up to 1024 words can be set in the SBROM, the maximum time required for setting the data is half of the wait period.
Table 2 Relationship between fs and wait period
fs 32 kHz 44.1 kHz 48 kHz Wait Period 64.0 ms 46.4 ms 42.7 ms Boot Time (Maximum) 32.0 ms 23.2 ms 21.3 ms
Table 3 Relationship between BA [1:0] pin value and start address
BA1 0 0 1 1 BA0 0 1 0 1 Start Address 000h 001h 002h 003h
(3-2)
Self-boot operation when setting microcontroller In this mode, the microcontroller can specify any address and the operation starts from that address. The BOOT pin can be set to either High or Low. Setting the self-boot ROM start address using the BOOT command (CMD: 41h) from the microcontroller starts the boot operation with no wait. The boot operation when set from the microcontroller is the same as the self-boot operation at reset except that the boot operation can start from any address.
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Figure 3 Boot timing chart (at reset)
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Table 4 Differences depending on operating mode
Parameter Boot wait period Boot start address Boot pin Boot Mode at Reset Yes Select from 000h to 003h "H" level Boot Mode Set from Microcontroller No Any address specified from microcontroller Don't care
(4)
Programming examples
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(5) Code format example The following shows the format for storing data in SBROM.
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5. Cautions on use
(1) The cautions at the time of using IFOK terminal The timing which outputs IFOK signal is the signal which shows whether the command received from the microcomputer was performed normally. Since the initial value of IFCK signal is unfixed when a control microcomputer is checking IFOK signal, before sending a command, it may stop performing control from a microcomputer. (2) The cautions at the time of using ACMP (address comparing mode) In rewriting coefficient data and offset data using ACMP mode, please do not use it the following condition. (2-1) Please do not transmit the following command before completing rewriting of data. Please do not send the following command before completing rewriting of data of CRAM or OFRAM. Please check that waiting the term after rewriting of data is completed until it transmits the following command was carried out, or rewriting has been completed using IFOK signal. (2-2) Please do not include data of an intact address. Please do not include coefficient data of offset data of an address which are not used by the program under execution, into transmitting data. When data of an intact address is contained, operation in ACMP mode cannot be ended. If the following command is transmitted in this state, RAM data will become unfixed also by the command with the command unrelated to CRAM or OFRAM. It needs to reset and all data needs to be re-set up to interrupt before completing rewriting of data in the rewriting processing. (2-3) Please do not perform continuation transmission over the 0th address. The transmission over the 0th address may incorrect-operate. The same of this restriction is said not only of ACMP mode but continuation transmission of usual RAM data. For example, when writing in 007h from 1BFh and 000h from 1B8h of CRAM, it must transmit in 2 steps. (3) The following cautions are required when transmitting a reset command and a boot command in the cautions I2C bus mode at the time of using the I2C bus mode. (3-1) At the time of reset command use When transmitting a reset command (4Fh: M-RST) from a microcomputer, the acknowledgement signal in front of the end conditions outputted from IFDI terminal is not transmitted to a microcomputer. Therefore, the acknowledgement signal of the last of IFDI signal should repeal at the time of reset command transmission. The timing at the time of reset command transmission is shown if Figure 4.
Figure 4 Timing at the time of command transmission
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(3-2) At the time of self boot command use When a self boot command (41h: BOOT) is transmitted, even if end conditions happen to the acknowledgement signal of the last of boot command data, please repeal. If it becomes the boot mode, data will be transmitted internal boot ROM data using the internal circuit of a microcomputer interface. Data is transmitted not in the I2C bus mode but in the standard transmitting mode at the time of boot mode operation in that case. Therefore, IFDI terminal will be in the state of H level, and operation of an I2C bus and conditions may not be performed normally. The timing at the time of self boot command transmission is shown if Figure 5.
Figure 5 Timing at the time of self boot command transmission
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Peripheral Circuit Example 1 (standard transmission mode)
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
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Peripheral Circuit Example 2 (I C bus mode)
2
The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba.
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Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation Operating temperature Storage temperature Note 3: Symbol VDD VIN PD Topr Tstg Rating -0.3~6.0 -0.3~VDD + 0.3 1500 -40~75 (Note 3) -55~150 Unit V V mW C C
Only when frequency of operation is 340 step mode, a temperature of operation becomes Ta = -40~85C.
Electrical Characteristics
(unless otherwise noted, Ta = 25C, VDD = VDX = VDDR = VDL = VDR = VDAL = VDAR = VDAC = VDAS = 5 V) DC characteristics
Characteristics Operating power supply voltage Operating frequency range Operating power supply current Symbol VDD fopr IDD Test Circuit Test Condition Ta = -40~75C 340-step mode 511-step mode fopr = 33.8688 MHz 511-step mode Min 4.5 8 12 Typ. 5.0 15 33.8 135 Max 5.25 25 34 140 Unit V MHz mA
Clock pins (XI, XO, ECKI, ECKO)
Characteristics Input voltage (1) "H" level "L" level "H" level "L" level Symbol VIH1 VIL1 VOH1 VOL1 RXD Test Circuit Test Condition XI, ECKI pin IOH = -3.0 mA IOL = 5.0 mA XI, ECKI pin Min 3.5 XO, ECKO pin 4.5 Typ. 3.0 Max 1.5 0.5 5.0 Unit V
Output voltage (1)
V k
Pull-down resistance
Input pins
Characteristics Input voltage (2) Input leakage current Threshold voltage Hysteresis voltage Note 4: Note 5: "H" level "L" level "H" level "L" level "H" level "L" level Symbol VIH2 VIL2 IIH2 IIL2 VP VN VH Test Circuit VIN = VDD VIN = 0 V Test Condition (Note 4) Min 4.2 -10 2 Typ. 2.8 2.0 0.8 Max 0.8 10 Unit V
(Note 4)
A
(Note 5) (Note 5)
V V
CKS, STEP0, STEP1, RST , SYNC, ELRO, ELRI, EBCO, EBCI, DIN, EM0, EM1, I CS, CS , IFCK, IFDI, BOOT, BA0, BA1, TST0~3 (Normally input pins and Schmitt input pins) Pins excluding I CS pins in Note 1 above (Schmitt input pins)
2
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Output pins
Characteristics Output voltage (2) "H" level "L" level "H" level "L" level Symbol VOH2 VOL2 VOH3 VOL3 VOL4 IOZ4 Test Circuit Test Condition IOH = -2.0 mA IOL = 2.0 mA IOH = -4.0 mA IOL = 4.0 mA IOL = 4.0 mA VOH = VDD (Note 6) Min 4.5 4.5 Typ. Max 0.5 0.5 0.5 10 Unit V
Output voltage (3)
(Note 7)
V V A
Output voltage (4) "L" level Output open leakage current
(Note 8)
Note 6: FS, CKO0, CKO1, MCK, DOUT (Normally output) Note 7: IFDO (Normally output) Note 8: IFDI (When I C mode output), IFOK, ACK , ERR (Open drain output)
2
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AC Characteristics (1) Analog
AD converter characteristics
Characteristics Maximum input signal level Input impedance Symbol Vi Zin S/Na1 S/(N + D) ratio S/Na2 THD + N Crosstalk Dynamic range THDa CTa DRa Test Circuit Test Condition Input level that ADC digital output does not overflow (Note 9) LIN, RIN pins (Note 9) Min 1.13 90 88 Typ. 1.20 27.0 98 94 -77 -95 95 Max dB -70 -88 90 dB dB dB Unit Vrms k
A-Weight, When using X'tal oscillator at 33.8688 MHz (Note 9) CCIR-ARM, When using X'tal oscillator at 33.8688 MHz (Note 9) 20 kHz LPF, When using X'tal oscillator at 33.8688 MHz (Note 9) A-Weight, When using X'tal oscillator at 33.8688 MHz (Note 9) A-Weight, When using X'tal oscillator at 33.8688 MHz (Note 9)
Note 9: Input channels: LIN, RIN
DA converter characteristics
Characteristics Symbol VO1 Output signal level VO2 Trim output pin: attenuation level Trim output pin: step level S/N ratio VOAL VOAS S/Nd THDd1 THD+N THDd2 Crosstalk Dynamic range CTd DRd Test Circuit Test Condition Output voltage at full-scale digital input (Note 10) Output voltage at full-scale digital input (Trim output) (Note 11) (Note 11) (Note 11) A-Weight, When using X'tal oscillator at 33.8688 MHz (Note 12) 20 kHz, When using X'tal oscillator at 33.8688 MHz (Note 10) 20 kHz, When using X'tal oscillator at 33.8688 MHz (Note 11) A-Weight, When using X'tal oscillator at 33.8688 MHz (Note 12) A-Weight, When using X'tal oscillator at 33.8688 MHz (Note 12) Min 1.10 1.35 0 90 Typ. 1.21 1.52 1 100 -87 -82 -95 95 Max 1.32 Vrms 1.61 -20 -80 dB -75 -88 90 dB dB dB dB dB Unit
Note 10: Output channel: AOL, AOR, AOC, AOS Note 11: Output channel: AOCT, AOST Note 12: Output channel: AOL, AOR, AOC, AOS, AOCT, AOST
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AC Characteristics (2) Timing
Clock input pins (XI, ECKI)
Characteristics Clock cycle Clock "H" cycle width Clock "L" cycle width Symbol tXI tXIH tXIL Test Circuit Test Condition Min 29 Typ. 14.5 14.5 Max Unit ns ns ns
Reset pin ( RST )
Characteristics Standby time Reset pulse width Symbol tRRS tWRS Test Circuit Test Condition Min 10 1.0 Typ. Max Unit ms s
Timing output
Characteristics CKO output delay time Symbol tDFC Test Circuit Test Condition Min -150 Typ. Max 150 Unit ns
Audio serial interface (EBCI, DIN, EBCO, DOUT)
Characteristics ELRI hold time DIN setup time DIN hold time EBCI clock cycle EBCI clock "H" cycle width EBCI clock "L" cycle width ELRO hold time DOUT output delay time (1) DOUT output delay time (2) EBCO clock cycle EBCO clock "H" cycle width EBCO clock "L" cycle width Symbol tLIH tSDI tHDI tEBCI tEBIH tEBIL tLOH tDO1 tDO2 tEBCO tEBOH tEBOL Test Circuit Test Condition CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF Min -75 50 50 300 150 150 -75 300 150 150 Typ. Max 75 75 60 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns
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Microcontroller Interface Standard transmission mode ( CS , IFCK, IFDI, IFDO, ACK )
Characteristics Standby time
CS - IFCK Setup time (Mode 1)
Symbol tSTB tCCD tWLC tWHC tCKC tWCS tCCU tSCK tSCD tHCD tDDO tDAKD tDAKZ
Test Circuit
Test Condition
Min 1.0 0.5 0.5 0.5 0.5 (Note 13) 1.0 0.5 0.5 0.5 0.5
Typ.
Max 0.5 0.5 0.5
Unit s s s s s s s s s s s s s
IFCK "L" cycle width IFCK "H" cycle width IFCK - CS Setup time
CS "H" cycle width
IFCK - CS Setup time (Mode 2) IFCK - CS Setup time IFDI - IFCK Setup time IFCK - IFDI Hold time IFCK - IFDO Propagation delay time IFCK - ACK Propagation delay time IFCK - ACK Propagation delay time
CL = 30 pF CL = 30 pF (Pull-up resistor) RL = 1 k CL = 30 pF (Pull-up resistor) RL = 1 K

Note 13: The command which is "Sync" in the transfer Sync with Sync signal of a 17 page table 1 control command table needs to set the CS = H section to a minimum of 1 fs more until it transmits the following command.(It needs more than 22.68 s at fs = 44.1 kHz)
I C mode ( CS , IFCK, IFDI)
Characteristics IFCK clock frequency IFCK "H" cycle width IFCK "L" cycle width Data setup time Data hold time Transmission start condition hold time Repeat transmission start condition setup time Transmission end condition setup time Data transmission interval I C rise time I C fall time
2 2
2
Symbol fIFCK tH tL tDS tDH tSCH tSCS tECS tBUF tR tF
Test Circuit
Test Condition CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF
Min 0 0.6 1.3 0.1 0 0.6 0.6 0.6 1.3
Typ.
Max 400 0.3 0.3
Unit kHz s s s s s s s s s s
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AC Characteristics Test Points
1. Clock pins (XI, ECKI)
2. Reset
3. Timing output
4. Audio serial interface (ELRI, EBCI, DIN, ELRO, EBCO, DOUT)
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5. Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO, ACK )
6. Microcontroller interface in I C mode (IFCK, IFDI)
2
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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Package Dimensions
Weight: 1.57 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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