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CXA2111R
LCD Signal Processor (Gamma Correction)
Description The CXA2111R is a signal processor IC developed for LCD panels. Gamma correction, gain and bias, etc., can be adjusted using the I2C bus and external adjustment pins. The output of this IC is ideal as the input of the CXA2112R (LCD sample-and-hold driver IC), and the sample-and-hold position, etc., can also be adjusted using the I2C bus. Features * Independent R, G and B gamma adjustment * Three-point gamma gain and position adjustment (one white side point, two black side points) * Independent R, G and B output amplifier gain and bias adjustment * Various I2C bus-based controls and adjustment of various characteristics by external DC input * Input signal clamp function (variable clamp voltage) * Black side limiter adjustment * CXA2112R adjustment output * Precharge output (for CXA2112R) * High frequency response * High slew rate output Applications * Liquid crystal projectors * Compact liquid crystal monitors Structure Bipolar silicon monolithic IC 52 pin LQFP (Plastic)
Absolute Maximum Ratings -0.3 to +5.5 V * Supply voltage VCC * Input voltage VI -0.3 to VCC + 0.3 V * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1000 mW Operating Conditions * Supply voltage * Digital input voltage high * Digital input voltage low * Operating temperature
VCC VH VL Topr
4.75 to 5.25 2.2 to VCC 0 to 0.8 -20 to +70
V V V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E97448-PS
CXA2111R
Pin Configuration and Block Diagram
GAMG_WHP
GAMG_B1P
GAMR_B2P
GAMR_B1P
GAMB_WHP
GAMR_WHP
GAMB_B1P
AMPGGAIN
28
AMPGBIAS
39
38 37
36 35
34 33
32
AMPBBIAS
31
AMPRBIAS
AMPBGAIN
30 29
27
GAMG_B2P 40 CLAMP GAMB_B2P 41 GAMR_WHG 42 CLAMP GAMG_WHG 43 GAMB_WHG 44 CLAMP GAMR_B1G 45 GAMG_B1G 46 GAMB_B1G 47 GAMR_B2G 48 GAMG_B2G 49 GAMB_B2G 50 SCL 51 SDA 52 Input I/F CLAMP Control
AMPRGAIN
26 BIN AMP DRIVER 25 CLPLEV 24 GIN AMP DRIVER 23 ATT 22 RIN AMP DRIVER 21 VCC 20 CLPPLS 19 GND
* AMP Adjust
DAC/Control 6bit x 25 I2C Bus Output I/F
18 ROUT 17 PVCC 16 GOUT 15 PGND PRG/SID 14 BOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
POS_CNT1
POS_CNT2
DLY_CNT
DIR_CNT
INV_CNT
-2-
GAMOFF
PRGPLS
PRGLEV
DATEST
SIDOUT
SIDLEV
BLKLIM
V33
CXA2111R
Pin Description Pin No. Symbol I/O Typical pin voltage Equivalent circuit Description CXA2112R control. The sample-and-hold position is determined by the I2C data. POS_CNT1 is the low-order 4-value output and POS_CNT2 is the highorder 4-value output for a total of 16value control.
I2C data input (2 bits) 00 01 10 11 Pin output L H
1
POS_CNT1
VCC
VCC
VCC
O
0 to 5V (4 value)
1 2 300
2
POS_CNT2
70k
VCC
VCC 25k
CXA2112R control. The clock delay time is controlled by output analog value using I2C data.
I2C data input (6 bits) all 0 all 1 Pin output 5V 3V
3
DLY_CNT
O
3 to 5V
300 3
CXA2112R control. The scan direction is determined by the I2C data. 4 DIR_CNT
VCC VCC 20k
I2C data input (1 bit) 0 1
Pin output H L
O
L/H (0V/5V)
300 4 5
5
INV_CNT
CXA2112R control. The clock polarity is determined by the I2C data.
I2C data input (1 bit) 0 1
VCC VCC
Pin output H L
Output for CXA2112R. This pin outputs the precharge signal. 6 SIDOUT O 2.3 to 3.3V
6
Pin 6 output Pin 10 input Level controlled by Pin 11 H Level controlled by Pin 9 L
7
DATEST
DAC test output. Set the I2C data to "1". This pin is normally open.
-3-
CXA2111R
Pin No.
Symbol
I/O
Typical pin voltage
Equivalent circuit
VCC VCC
Description
8
V33
O
3.3V
8
Output for CXA2112R. This pin outputs 3.3V.
VCC
VCC 50k 75k 100
9
SIDLEV
50k
I 11 PRGLEV
0 to 5V
9 11
These pins determine the Pin 6 output level. See Pin 6.
VCC VCC
10
PRGPLS
I
L/H L: 0 to 0.8V H: 2.2 to 5V
25 300 10
This pin determines the Pin 6 output. See Pin 6. Set to low or high when using SIDOUT (Pin 6) as a DC output.
VCC
VCC 750
12
BLKLIM
I
1 to 5V
12
1.6k
Output black level (low level side) limit voltage control. Apply voltage of 1V DC or more.
VCC VCC
Gamma characteristics ON/OFF setting.
I2C data input (1bit) Pin 13 input H L H L mode ON OFF OFF OFF
13
GAMOFF
I
L/H L: 0 to 0.8V H: 2.2 to 5V
50k 300 13
0 1
14
BOUT
14
PVCC
PVCC
B channel output.
16
GOUT
O 1.8 to 3.3V
50
16 18
G channel output.
18 15 17 19
ROUT PGND PVcc GND GND 5V GND
GND
R channel output. GND. 5V GND.
-4-
CXA2111R
Pin No.
Symbol
I/O
Typical pin voltage
Equivalent circuit
Description
VCC VCC
20
CLPPLS
I
L/H L: 0 to 0.8V H: 2.2 to 5V
50 300 20
Input signal clamp pulse input. Set to low when not using the clamp function.
Pin input H L Clamp function ON OFF
21 22
Vcc RIN
5V
VCC VCC 22 24 26 300 170
5V R channel input.
24
GIN
I
1.5 to 3.5V
G channel input.
26
BIN
VCC VCC
B channel input.
23
ATT
I
L/H L: 0 to 0.8V H: 2.2 to 5V
50 300 23
Input signal gain control. This pin also supports 2Vp-p input.
Pin input Clamp block gain Signal level For 1Vp-p H 0dB For 2Vp-p L -6dB
VCC VCC 50
Clamp voltage control during clamp operation.
Pin input 5V 2.5V (open) 0V Clamp voltage 2.5V 2.0V 1.5V
25
CLPLEV
I
0 to 5V
60k 25 20k 2.5V
27
AMPRGAIN
27 28 29
VCC 2.5V
28
AMPGGAIN
25k
Amplifier gain control. Independent control for R, G and B. Equivalent to 2.5V input when open.
29
AMPBGAIN I 0 to 5V
VCC 2.5V 30 31 32
30
AMPRBIAS
31
AMPGBIAS
25k
Amplifier bias control. Independent control for R, G and B. Equivalent to 2.5V input when open.
32
AMPBBIAS -5-
CXA2111R
Pin No. 33
Symbol GAMR_WHP
I/O
Typical pin voltage
Equivalent circuit
Description
VCC 2.5V 33 34 35
34
GAMG_WHP
25k
Gamma white position control. Independent control for R, G and B. Equivalent to 2.5V input when open.
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GAMB_WHP GAMR_B1P GAMG_B1P GAMB_B1P GAMR_B2P GAMG_B2P GAMB_B2P GAMR_WHG GAMG_WHG GAMB_WHG GAMR_B1G GAMG_B1G GAMB_B1G GAMR_B2G GAMG_B2G GAMB_B2G
VCC
Gamma black 1 position control. Independent control for R, G and B. Equivalent to 2.5V input when open. Gamma black 2 position control. Independent control for R, G and B. Equivalent to 2.5V input when open.
2.5V 25k
I
0 to 5V
43 36 44 37 45 38 46 39 47 40 48 41 49 42 50
VCC
Gamma white gain control. Independent control for R, G and B. Equivalent to 2.5V input when open. Gamma black 1 gain control. Independent control for R, G and B. Equivalent to 2.5V input when open. Gamma black 2 gain control. Independent control for R, G and B. Equivalent to 2.5V input when open.
51
SCL
I
50
I2C bus clock input. L/H (0V/5V)
4k 51 52
52
SDA
I/O
I2C bus data input.
-6-
CXA2111R
I2C Bus Format Slave address: 0111 0110 (76h) Sub address 00000 (00h) 00001 (01h) 00010 (02h) 00011 (03h) 00100 (04h) 00101 (05h) 00110 (06h) 00111 (07h) 01000 (08h) 01001 (09h) 01010 (0Ah) 01011 (0Bh) 01100 (0Ch) 01101 (0Dh) 01110 (0Eh) 01111 (0Fh) 10000 (10h) 10001 (11h) 10010 (12h) 10011 (13h) 10100 (14h) 10101 (15h) 10110 (16h) 10111 (17h) 11000 (18h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AMPRGAIN AMPGGAIN AMPBGAIN AMPRBIAS AMPGBIAS AMPBBIAS GAMR_WHP GAMG_WHP GAMB_WHP GAMR_B1P GAMG_B1P GAMB_B1P GAMR_B2P GAMG_B2P GAMB_B2P GAMR_WHG GAMG_WHG GAMB_WHG GAMR_B1G GAMG_B1G GAMB_B1G GAMR_B2G GAMG_B2G GAMB_B2G DLY_CNT GAMOFF DATEST POS_CNT2 POS_CNT1 DIR_CNT INV_CNT
-7-
CXA2111R
Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.)
No. Item
(VCC, PVCC = 5V, Ta = 25C)
Min. Typ. Max. Unit
MeasuSymbol rement Measurement conditions and measurement outline point Icc I21 [Gamma gain (white, black 1, black 2) = max., amplifier gain = max.] V22, 24, and 26 = 2.5V, V27 to 29 and 42 to 50 = 5V, V30 to 41 = open, Measure the I21 current. Excluding the I2C bus pins (Pins 51 and 52). Excluding the I2C bus pins (Pins 51 and 52). Pins 22, 24 and 26 input V14 V16 V18 V14 V16 V18 V14 V16 V18 V14 V16 V18 V14 V16 V18 V14 V16 V18 V14 V16 V18 Pins 14, 16 and 18 output V27 to 29 and 36 to 44 = 5V, V30 to 35 = open, V45 to 50 = 0V Calculate Vwx/Vo (a) for the maximum Vwx at Vo (e), Vo (f) and Vo (g). V27 to 29, 39 to 41 and 45 to 47 = 5V, V30 to 32 and 36 to 38 = open, V33 to 35, 42 to 44 and 48 to 50 = 0V. Calculate Vb1x/Vo (i) for the maximum Vb1x at Vo (c), Vo (d) Vo (e) and Vo (f).
1
Current consumption Digital input voltage high Digital input voltage low Maximum input voltage amplitude Maximum output voltage amplitude
80
135
180
mA
2 3 4 5
Vih Vil Vix Vox
2.2 GND 2 1.5
Vcc 0.8
V V V V
6
Gamma white gain Ggwx max. Gamma black 1 gain max.
6.0
7.4
9.2
times
7
Ggb1x
8.0
9.5
11.6 times
8
Gamma black 2 gain max.
Ggb2x
V27 to 29, 36 to 38 and 48 to 50 = 5V, V30 to 32 = 3.75V, V33 to 35 and 42 to 47 = 0V, V39 to 41 = 3.3V 16.0 Calculate Vb2x/Vo (h) for the maximum Vb2x at Vo (a), Vo (b) and Vo (c). V13 = 0V, V27 to 29 = 0V, V30 to 50 = open Calculate Vo (j)/0.1. V13 = 0V, V27 to 29 = 5V, V30 to 50 = open Calculate Vo (j)/0.1. V13 = 0V, V22, 24 and 26 = 2.5V, V27 to 29 = 0.75V, V33 to 50 = open V14, 16 and 18 voltages when V30 to 32 = 0V, open and 5V. Calculate Vb (0V) - Vb (open) and Vb (5V) - Vb (open) at Vb (0V), Vb (open) and Vb (5V). V27 to 29 and 36 to 44 = 5V, V30 to 35 and 42 to 44 = open, V45 to 50 = 0V, I2C data = 3Fh Calculate Vwxi/Vo (a) for the maximum Vwxi at Vo (e), Vo (f) and Vo (g). V27 to 29 and 36 to 44 = 5V, V30 to 35 and 42 to 44 = open, V45 to 50 = 0V, I2C data = 00h Calculate Vwni/Vo (a) for the maximum Vwni at Vo (e), Vo (f) and Vo (g). V27 to 29, 39 to 41 and 45 to 47 = 5V, V30 to 32, 36 to 38 and 45 to 47 = open, V33 to 35, 42 to 44 and 48 to 50 = 0V, I2C data = 3Fh Calculate Vb1xi/Vo (i) for the maximum Vb1xi at Vo (c), Vo (d) Vo (e) and Vo (f). V27 to 29, 39 to 41 and 45 to 47 = 5V, V30 to 32, 36 to 38 and 45 to 47 = open, V33 to 35, 42 to 44 and 48 to 50 = 0V, I2C data = 00h Calculate Vb1ni/Vo (i) for the maximum Vb1ni at Vo (c), Vo (d) Vo (e) and Vo (f). V27 to 29, 36 to 38 and 48 to 50 = 5V, V30 to 32 = 3.75V, V33 to 35 and 42 to 47 = 0V, V39 to 41 = 3.3V, V48 to 50 = open, I2C data = 3Fh Calculate Vb2xi/Vo (h) for the maximum Vb2xi at Vo (a), Vo (b) and Vo (c). 1.65
19.7
26.8 times
9
Amplifier gain max. Gax
2.26
3.25 times
10
Amplifier gain min. Gan
0.28
0.35
0.46 times
11
Amplifier bias output variable range
Vab
0.80 0.96 1.15
V
12
Gamma white gain Ggwxi I2C max.
V14 V16 V18 V14 V16 V18
5.85
7.21
8.65
times
13
Gamma white gain Ggwni I2C min.
3.80
4.71
5.65 times
14
Gamma black 1 gain I2C max.
V14 Ggb1xi V16 V18
7.6
9.11
10.7 times
15
Gamma black 1 gain I2C min.
V14 Ggb1ni V16 V18 V14 Ggb2xi V16 V18
5.05
6.02
7.00 times
16
Gamma black 2 gain I2C max.
15.8
19.5
23.2 times
-8-
CXA2111R
No.
Item
17
Gamma black 2 gain I2C min.
MeasuSymbol rement Measurement conditions and measurement outline point V27 to 29, 36 to 38 and 48 to 50 = 5V, V30 to 32 = V14 3.75V, V33 to 35 and 42 to 47 = 0V, V39 to 41 = Ggb2ni V16 3.3V, V48 to 50 = open, I2C data = 3Fh V18 Calculate Vb2xi/Vo (h) for the maximum Vb2xi at Vo (a), Vo (b) and Vo (c). Gaxi V14 V16 V18 V14 V16 V18 V14 V16 V18 V14 V16 V18 Vr Vg Vb Vr Vg Vb V14 V16 V18 V14 V16 V18 V6 V6 V13 = 0V, V27 to 50 = open, I2C data = 00h Calculate Vo (j)/0.1. V13 = 0V, V27 to 50 = open, I2C data = 3Fh Calculate Vo (j)/0.1. V13 = 0V, V22, 24 and 26 = 2.5V, V27 to 29 = 0.75V, V30 to 50 = open V14, 16 and 18 voltages when I2C data = 00h, 20h and 3Fh. Calculate Vbi (00h) - Vbi (20h) and Vbi (3Fh) - Vbi (20h) at Vbi (00h), Vbi (20h) and Vbi (3Fh). [Gamma OFF, amplifier gain min., ratio of 100MHz to 20MHz] V13 = 0V, V27 to 29 = 5V, V30 to 50 = open Calculate 20LOG {Vo (k)/Vo (j)}. SW22, 24, 26 = b, SW25 = ON V20 = 5V, V25 = 0V SW22, 24, 26 = b, SW25 = ON V20 = 5V, V25 = 5V V12 = 1.3V, V13 = 0V, V22, 24, 26 = 2V, V27 to 29 = 0.75V, V30 to 32 = 0V, V33 to 50 = open V13, 27 to 29 = 0V, V22, 24, 26 = 3.1V, V30 to 32 = 5V, V33 to 50 = open V9 = V11 = 0.5 V, V10 = 0V or 5V V9 = V11 = 4.5 V, V10 = 0V or 5V DAC output when DAC data = 00h, 1Fh, 20h and 3Fh. Calculate | {V (20h) - V (1Fh)}/[{V (3Fh) - V (00h}/63] | - 1 at V (00h), V (1Fh), V (20h) and V (3Fh). V14 V16 V18 Gamma OFF, gain adjusted so that 1Vp-p pulse input results in 1.5Vp-p output, output 3pF load With input DC 2.0 to 3.0V set as 0 to 100 IRE V33 to V41 = 0V With input DC 2.0 to 3.0V set as 0 to 100 IRE V33 to V41 = 5V With input DC 2.0 to 3.0V set as 0 to 100 IRE V33 to 35 = open, I2C data = 3Fh With input DC 2.0 to 3.0V set as 0 to 100 IRE V33 to 35 = open, I2C data = 00h With input DC 2.0 to 3.0V set as 0 to 100 IRE V36 to 41 = open, I2C data = 00h With input DC 2.0 to 3.0V set as 0 to 100 IRE V36 to 41 = open, I2C data = 3Fh
Min.
Typ.
Max. Unit
11.3
14.0
16.7 times
18
Amplifier gain I2C max. Amplifier gain I2C min. Amplifier bias I2C output variable range Frequency response Clamp voltage min. Clamp voltage max. Black limiter voltage
0.44
0.55
0.67 times
19
Gani
0.30
0.39
0.47 times
20
Vabi
0.34 0.39 0.45
V
21
Gf
-2.7
dB
22
Vcn
1.35
1.45
1.55
V
23
Vcx
2.75
2.85
2.95
V
24
Vbl
1.00
1.19
1.35
V
25 26 27 28
Output maximum voltage value Vwl (white limiter voltage) SIDOUT output min. Vsn SIDOUT output max. Vsx I2C DAC (6-bit) DLE Output rise/fall time Dle
3.50 1.75 3.30 -0.9
3.71 1.98 3.48
4.00 2.15 3.65 0.6
V V V LSB
29
Trf
4
ns
30
Gamma position max. (white/black 1/black 2) Pgx Gamma position min. (white/black 1/black 2) Pgn Gamma position I2C max. (white) Gamma position I2C min. (white) Pgwxi
100
IRE
31
0
IRE
32
100
IRE
33
Pgwni
40
IRE
34
Gamma position I2C max. (black 1/black 2) Pgbxi Gamma position I2C min. (black 1/black 2) Pgbni
70
IRE
35
0
IRE
-9-
Electrical Characteristics Measurement Circuit

Slave address = 76h
V39 Vr Vg Vb 0.1 to DAC/Control 25 to CLAMP Control CLAMP b 0.1 V23 5V 0.1 22 CLAMP to DAC/Control CLAMP Control * AMP Adjust 20 DAC/Control 6bit x 25 Input I/F I2C Bus 18 ROUT V18 PVCC 17 I21 V21 5V 47/16V Output I/F PRG/SID 16 GOUT 0.1 PGND 15 V16 to CLAMP Control 19 21 VCC 47/16V CLPPLS V20 0V 0.1 GND AMP DRIVER RIN b a SW22 V22 23 AMP to CLAMP Control DRIVER ATT AMP DRIVER 24 GIN SW25 V24 a SW24 CLPLEV a SW26 V25 5V 26 BIN b V26 V38 V37 V36 V35 V34 V33 V32 V31 V30 V29 V28 V27
No.
GAMG_B1P GAMB_B1P AMPBBIAS GAMR_B2P GAMR_WHP GAMG_WHP GAMB_WHP GAMR_B1P AMPGBIAS AMPRBIAS AMPBGAIN AMPGGAIN AMPRGAIN
27
Item
Data
1
AMPRGAIN
00h
2
39 34 29 38 36 33 31 30 28 37 32 35
AMPGGAIN
00h
3
AMPBGAIN
00h
4
AMPRBIAS
20h
GAMG_B2P
5
AMPGBIAS
20h
40
V40
6
AMPBBIAS
20h
GAMB_B2P
41
7
GAMR_WHP
00h
V41
8
GAMG_WHP
00h
GAMR_WHG
42
V42
9
CLAMP
GAMB_WHP
00h
GAMG_WHG
10
GAMR_B1P
00h
43
V43
11
GAMG_B1P
00h
GAMB_WHG
44
12
GAMB_B1P
00h
V44
GAMR_B1G
13
GAMR_B2P
00h
45
V45
SIDOUT
DATEST
SIDLEV
INV_CNT
PRGPLS
PRGLEV
BLKLIM
28
DIR_CNT
0
POS_CNT1
POS_CNT2
DLY_CNT
DIR_CNT
V6
V9
V10
V11
29
INV_CNT
0
V12 1V
GAMOFF
27
POS_CNT2
00
V33
- 10 -
14 1 2 3 4 5 6 7 8 9 10 11 12 13 V13 5V
14
GAMG_B2P
00h
GAMG_B1G
46
15
GAMB_B2P
00h
V46
16
GAMR_WHG
00h
GAMB_B1G
47
17
GAMG_WHG
00h
V47
GAMR_B2G
18
GAMB_WHG
00h
48
V48
The following sine wave signals are defined as the V22, 24 and 26 inputs.
19
GAMR_B1G
00h
GAMG_B2G
49
20
GAMG_B1G
00h
V49
21
GAMB_B1G
00h
GAMB_B2G
50
V50
22
GAMR_B2G
00h
23
GAMG_B2G
00h
V51
24
GAMB_B2G
00h
BOUT
V14
25
DLY_CNT
00h
V52
SCL 51 I2C input (clock) SDA 52 I2C input (data)
26
POS_CNT1
00
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k)
2.15Vdc + 0.1Vp-p 20MHz 2.25Vdc + 0.1Vp-p 20MHz 2.35Vdc + 0.1Vp-p 20MHz 2.45Vdc + 0.1Vp-p 20MHz 2.55Vdc + 0.1Vp-p 20MHz 2.65Vdc + 0.1Vp-p 20MHz 2.75Vdc + 0.1Vp-p 20MHz 2.85Vdc + 0.1Vp-p 20MHz 2.95Vdc + 0.1Vp-p 20MHz 2.5Vdc + 0.1Vp-p 20MHz 2.5Vdc + 0.1Vp-p 100MHz
30
GAMOFF
0
CXA2111R
31
DATEST
1
In addition, the V14, 16 and 18 output levels for the above inputs (x) are labeled Vo (x).
CXA2111R
Description of Operation 1. Gamma control The bend positions and respective gains of one white side point and two black side points can be varied. Control is performed independently for R, G and B by the I2C bus or by external DC. In addition, the gamma function can easily be forced OFF (by Pin 13 or the I2C bus).
White gain Gamma OFF White position Black 2 position Black 1 gain
Black 1 position
Black 2 gain
2. Amplifier gain and bias control After adjusting the gamma, the signal gain and DC voltage can also be adjusted. 3. SIDOUT SIDOUT generates the precharge signal. After the CXA2111R determines the DC level (Pins 9 and 11) and the pulse width (Pin 10), the signal is inverted by the CXA2112R and applied to the LCD panel. See the Example of Representative Characteristics for the DC level.
PRGPLS input (Pin 10) Voltage determined by Pin 9 SIDOUT output (Pin 6) Voltage determined by Pin 11
Output example 4. I2C bus The various gamma and amplifier controls can be performed in accordance with the I2C Bus Format table. In addition, the sample-and-hold position and other items can also be controlled by connecting the CXA2112R.
- 11 -
CXA2111R
Notes on Operation 1. External DC voltage adjustment, I2C adjustment and variable ranges (a) When varying the external DC voltage Setting the I2C data to the standard setting values (listed in the Electrical Characteristics Measurement Circuit) is recommended when performing the various adjustments using the external pins (Pins 27 to 50). Note that setting data that differs from these standard setting values may clip one side of the variable ranges below. (b) When varying the I2C setting The variable ranges when the external pins are open or 2.5V are as shown in the table below. The I2C variable range position can be altered by changing the voltage applied to the external pins. However, note that characteristics in excess of the range in (a) above cannot be obtained. (a) External voltage adjustment (b) I2C adjustment (external pins open or 2.5V) x 7.4 5V x 7.21 x 4.71 x1 3Fh
white gain 0V
00h
(I2C standard setting 00h)
The variable position can be altered by changing the external voltage.
x 9.5
5V
x 9.11 x 6.02
3Fh
black 1 gain x1 0V
00h
(I2C standard setting 00h)
x 19.7
5V
x 19.5 x 14.0
3Fh
black 2 gain x1 0V
00h
(I2C standard setting 00h)
- 12 -
CXA2111R
(a) External voltage adjustment (b) I2C adjustment (external pins open or 2.5V) 100 IRE 0V 100 IRE 3Fh
white position 0 IRE 5V
40 IRE
00h
(I2C standard setting 00h)
100 IRE
0V
black 1 position 0 IRE 5V
70 IRE
00h
0 IRE
3Fh
(I2C standard setting 00h)
100 IRE
0V
black 2 position 0 IRE 5V
70 IRE
00h
0 IRE
3Fh
(I2C standard setting 00h)
Note) The 0 to 100 IRE levels here correspond to the following values when ATT (Pin 23) is high. Clamp OFF: Input 2 to 3V (1Vp-p) Clamp ON: Input 1Vp-p (however, Pin 25 = open or 2.5V)
- 13 -
CXA2111R
(a) External voltage adjustment (b) I2C adjustment (external pins open or 2.5V) x 2.26 0V x 0.55 Amplifier gain x 0.35 5V x 0.39 3Fh
00h
(I2C standard setting 00h)
+0.96V
5V +0.39V 00h 20h 3Fh
Amplifier bias (relative variation)
0V -0.96V
2.5V 0V
0V -0.39V
(I2C standard setting 20h)
2. Input signal level and clamp Set Pin 23 (ATT) low when the input amplitude exceeds 1Vp-p (up to 2Vp-p). In this case, care should be taken for the clamp voltage setting (Pin 25) when applying the clamp. See the figure below. (The input pin voltage should not exceed the range of 1.5V DC to 3.5V DC.)
Pin 25 setting voltage range 2.5Vdc 2.5V (0 to 5V)
2.5Vdc 0V 1Vp-p
2Vp-p
Input level
3. I2C bus The CXA2111R requires I2C bus control. The initial values must be set after power-on even when using only external DC adjustment.
- 14 -
CXA2111R
Application Circuit
GAMG_WHP
GAMB_WHP
GAMR_B2P
GAMR_WHP
GAMG_B1P
GAMB_B1P
GAMR_B1P
AMPGGAIN
39 GAMG_B2P
38
37
36
35
34
33
32
31
AMPBGAIN
30
29
28
AMPRGAIN
27 BIN 0.1
AMPGBIAS
40
AMPBBIAS
AMPRBIAS
to DAC/Control
26
GAMB_B2P
41 to CLAMP Control 42 CLAMP AMP DRIVER
25
CLPLEV 0.1
GAMR_WHG
24
GIN
GAMG_WHG
43 CLAMP
23 AMP DRIVER to CLAMP Control 22
ATT 0.1
GAMB_WHG
44 CLAMP AMP DRIVER
RIN
GAMR_B1G
45
to DAC/Control CLAMP Control * AMP Adjust
21
VCC 47/16V
5V
GAMG_B1G
46
20 DAC/Control 6bit x 25 to CLAMP Control 19
CLPPLS 0.1 GND Clamp pulse
GAMB_B1G
47 Input I/F
GAMR_B2G
48
I2C Bus
18
ROUT
47
GAMG_B2G
49 Output I/F
17
PVCC 47/16V
GAMB_B2G
50
PRG/SID
16
GOUT 0.1 PGND
47
I2C bus (clock) I2C bus (data)
SCL
51
15
SDA
52
14
BOUT
47
1
2
3
4
5
6
7
8
9
10
11
12
13
INV_CNT
DIR_CNT
DLY_CNT
PRGPLS
SIDLEV
V33
POS_CNT2
POS_CNT1
15k 1
15k 2 49 13 52 39 42 48
CXA2112R When using two CXA2112R, connect the ICs directly without inserting resistors.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 15 -
GAMOFF
DATEST
SIDOUT
PRGLEV
BLKLIM
CXA2112R
CXA2111R
Example of Representative Characteristics (Vcc = 5V, Ta = 25C)
R/G/B gamma white gain (I2C: standard setting)
9 8 7 10 9 8 7
R/G/B gamma black 1 gain (I2C: standard setting)
Gain [times]
Gain [times]
0 1 2 3 4 5 Control pin voltage (Pins 42, 43 and 44) [V]
6 5 4 3 2 1
6 5 4 3 2 1 0 1 2 3 4 5 Control pin voltage (Pins 45, 46 and 47) [V]
R/G/B gamma black 2 gain (I2C: standard setting)
25
R/G/B gamma white gain I2C characteristics (Control pins = open)
8.0 7.5
20 7.0
Gain [times]
15
Gain [times]
0 1 2 3 4 5 Control pin voltage (pins 48, 49 and 50) [V]
6.5 6.0 5.5
10
5 5.0 0 4.5 00 08 10 20 18 28 I2C setting [HEX] 30 38 3F
R/G/B gamma black 1 gain I2C characteristics (Control pins = open)
9.5 9.0 8.5
R/G/B gamma black 2 gain I2C characteristics (Control pins = open)
21 20 19
Gain [times]
7.5 7.0 6.5 6.0 5.5 00 08 10 18 28 30 20 I2C setting [HEX] 38 3F
Gain [times]
8.0
18 17 16 15 14 13 00 08 10 18 28 20 I2C setting [HEX] 30 38 3F
- 16 -
CXA2111R
R/G/B amplifier gain (I2C: Standard setting)
3.0 0.60
R/G/B amplifier gain I2C characteristics (Control pins = open)
2.5
0.55
2.0
Gain [times]
Gain [times]
0.50
1.5
0.45
1.0 0.40
0.5
0 0 1 2 3 4 5 Control pin voltage (Pins 27, 28 and 29) [V]
0.35 00 08 10 18 20 28 I2C setting [HEX] 30 38 3F
R/G/B output black limiter voltage
4.0 3.0 2.8 2.6
R/G/B input clamp voltage characteristics
3.5
Output voltage [V]
3.0
Clamp voltage [V]
2.4 2.2 2.0 1.8 When Pin 25 = open
2.5
2.0
1.5
1.6 1.4 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Pin 12 (BLKLIM) voltage [V] 4.5 5.0 0 1 2 3 4 Pin 25 (CLPLEV) voltage [V] 5
1.0
Pin 6 (SIDOUT) output
4.0 -7
R/G/B frequency response (Gamma OFF, amplifier gain = min.)
3.5
-8
Pin 6 voltage [V]
Gain [dB]
0 1 2 3 4 Control voltage (Pin 9/11) [V] 5
3.0
-9
2.5
-10
2.0
-11
1.5
-12 0.1 1 10 Frequency [MHz] 100
- 17 -
CXA2111R
Package Outline
Unit: mm
52PIN LQFP(PLASTIC)
12.0 0.2 10.0 0.1 39 40 27 26 B + 0.1 1.5 0 0.1
A 52 1 + 0.08 0.32 - 0.07 13 0.65 0.13 M 14
0.25
0.6 0.15
0.1 0.1
(11.0)
+ 0.08 0.32 - 0.07 (0.3)
0 to 10
DETAIL A
(0.5)
DETAIL B
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-52P-L01 LQFP052-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.3g
- 18 -
(0.125) + 0.04 0.145 - 0.025

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