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CS4340
24-Bit, 96 kHz Stereo DAC for Audio
Features
l Complete Stereo DAC System: Interpolation,
Description
The CS4340 is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4340 accepts data at audio sample rates from 2 kHz to 100 kHz, consumes very little power, and operates over a wide power supply range. The features of the CS4340 are ideal for DVD players, CD players, set-top box and automotive systems.
D/A, Output Analog Filtering l 101 dB Dynamic Range l 91 dB THD+N l Low Clock Jitter Sensitivity l +3 V to +5 V Power Supply l Filtered Line Level Outputs l On-Chip Digital De-emphasis for 32, 44.1, and 48 kHz l 30 mW with 3 V supply l Popguard(R) Technology for Control of Clicks and Pops
ORDERING INFORMATION CS4340-KS 16-pin SOIC, -10 to 70 C CS4340-BS 16-pin SOIC, -40 to 85 C CDB4340 Evaluation Board
I
SCLK/DEM1 RST
DEM0
MUTEC External Mute Control DAC Analog Filter AOUTL
De-emphasis Interpolation Filter Interpolation Filter
LRCK SDATA
Serial Input Interface
DAC
Analog Filter
AOUTR
DIF0 DIF1
MCLK
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
NOV `00 DS297PP3 1
CS4340
TABLE OF CONTENT
1. CHARACTERISTICS AND SPECIFICATIONS .............................................. 5 ANALOG CHARACTERISTICS................................................................... 5 ANALOG CHARACTERISTICS................................................................... 6 ANALOG CHARACTERISTICS................................................................... 7 POWER AND THERMAL CHARACTERISTICS ......................................... 8 DIGITAL CHARACTERISTICS.................................................................... 8 RECOMMENDED OPERATING CONDITIONS .......................................... 9 SWITCHING CHARACTERISTICS ........................................................... 10 2. TYPICAL CONNECTION DIAGRAM ............................................................ 12 3. PIN DESCRIPTION ....................................................................................... 13 4. APPLICATIONS ............................................................................................ 16 4.1 Grounding and Power Supply Decoupling ......................................... 16 4.2 Oversampling Modes ......................................................................... 16 4.3 Recommended Power-up Sequence ................................................. 16 4.4 Popguard(R) Transient Control ............................................................ 16 5. INTERPOLATION FILTER RESPONSE PLOTS .............................. 17 6. DIGITAL INTERFACE FORMATS ............................................. 19 7. ANALOG PERFORMANCE PLOTS ............................................................. 21 8. PARAMETER DEFINITIONS ........................................................................ 26 Total Harmonic Distortion + Noise (THD+N) ............................................. 26 Dynamic Range ......................................................................................... 26 Interchannel Isolation................................................................................. 26 Interchannel Gain Mismatch ...................................................................... 26 Gain Error .................................................................................................. 26 Gain Drift.................................................................................................... 26 9. REFERENCES .............................................................................................. 26 10. PACKAGE DIMENSIONS ........................................................................... 27
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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LIST OF FIGURES
Figure 1. External Serial Mode Input Timing ............................................................. 11 Figure 2. Internal Serial Mode Input Timing .............................................................. 11 Figure 3. Internal Serial Clock Generation ................................................................ 11 Figure 4. Typical Connection Diagram ...................................................................... 12 Figure 5. Base-Rate Stopband Rejection .................................................................. 17 Figure 6. Base-Rate Transition Band ........................................................................ 17 Figure 7. Base-Rate Transition Band (Detail)............................................................ 17 Figure 8. Base-Rate Passband Ripple ...................................................................... 17 Figure 9. High-Rate Stopband Rejection ................................................................... 17 Figure 10. High-Rate Transition Band ....................................................................... 17 Figure 11. High-Rate Transition Band (Detail) .......................................................... 18 Figure 12. High-Rate Passband Ripple ..................................................................... 18 Figure 13. Output Test Load...................................................................................... 18 Figure 14. Maximum Loading .................................................................................... 18 Figure 15. Power vs. Sample Rate (VA = 5V) ........................................................... 18 Figure 16. CS4340 Format 0 (I2S)............................................................................. 19 Figure 17. CS4340 Format 1 ..................................................................................... 19 Figure 18. CS4340 Format 2 ..................................................................................... 20 Figure 19. CS4340 Format 3 ..................................................................................... 20 Figure 20. De-Emphasis Curve ................................................................................. 21 Figure 21. FFT 0 dB input, BRM, VA = 3V ................................................................ 22 Figure 22. FFT -60 dB input, BRM, VA = 3V ............................................................. 22 Figure 23. FFT Idle Noise, BRM, VA = 3V................................................................. 22 Figure 24. Fade-to-Noise Linearity, BRM, VA = 3V................................................... 22 Figure 25. THDN vs Ampl, BRM, VA = 3V ................................................................ 22 Figure 26. THDN vs Freq, BRM, VA = 3V ................................................................. 22 Figure 27. FFT 0 dB input, BRM, VA = 5V ................................................................ 23 Figure 28. FFT -60 dB input, BRM, VA = 5V ............................................................. 23 Figure 29. FFT Idle Noise, BRM, VA = 5V................................................................. 23 Figure 30. Fade-to-Noise Linearity, BRM, VA = 5V................................................... 23 Figure 31. THDN vs Ampl, BRM, VA = 5V ................................................................ 23 Figure 32. THDN vs Freq, BRM, VA = 5V ................................................................. 23 Figure 33. FFT 0 dB input, HRM, VA = 3V ................................................................ 24 Figure 34. FFT -60 dB input, HRM, VA = 3V ............................................................. 24 Figure 35. FFT Idle Noise, HRM, VA = 3V ................................................................ 24 Figure 36. Fade-to-Noise Linearity, HRM, VA = 3V................................................... 24 Figure 37. THDN vs Ampl, HRM, VA = 3V ................................................................ 24 Figure 38. THDN vs Freq, HRM, VA = 3V ................................................................. 24 Figure 39. FFT 0 dB input, HRM, VA = 5V ................................................................ 25 Figure 40. FFT -60 dB input, HRM, VA = 5V ............................................................. 25 Figure 41. FFT Idle Noise, HRM, VA = 5V ................................................................ 25 Figure 42. Fade-to-Noise Linearity, HRM, VA = 5V................................................... 25 Figure 43. THDN vs Ampl, HRM, VA = 5V ................................................................ 25 Figure 44. THDN vs Freq, HRM, VA = 5V ................................................................. 25
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LIST OF TABLES
Table 1. Internal Serial Clock Mode .......................................................................... 14 Table 2. External Serial Clock Mode ......................................................................... 14 Table 3. Common Master Clock Frequencies ........................................................... 14 Table 4. Digital Interface Format - DIF1 and DIF0 ................................................... 15
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1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): TA = 25 C; Logic "1" =
VA = 5 V; Logic "0" = AGND;Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for HighRate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load RL = 10 k, CL = 10 pF (see Figure 13) Base-rate Mode Parameter Symbol Min -10 93 96 -10 89 92 Typ 98 101 95 97 -91 -78 -38 -90 -75 -35 102 94 97 93 96 -94 -74 -34 -93 -73 -33 102 Max 70 -86 70 -88 High-Rate Mode Min -10 91 95 -10 87 91 Typ 96 100 94 97 -89 -76 -36 -89 -74 -34 102 92 96 92 96 -92 -72 -32 -91 -72 -32 102 Max 70 -84 70 -87 Unit C dB dB dB dB dB dB dB dB dB dB dB C dB dB dB dB dB dB dB dB dB dB dB
CS4340-KS Dynamic Performance for VA = 5 V (Note 1) Specified Temperature Range TA Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted Total Harmonic Distortion + Noise (Note 2) THD+N 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) CS4340-KS Dynamic Performance for VA = 3 V (Note 1) Specified Temperature Range TA Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted Total Harmonic Distortion + Noise (Note 2) THD+N 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz)
Notes: 1. CS4340-KS parts are tested at 25 C and Min/Max performance numbers are guaranteed across the specified temperature range, TA. 2. One-half LSB of triangular PDF dither is added to data.
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ANALOG CHARACTERISTICS (Continued)
Base-rate Mode Parameter Symbol Min CS4340-BS Dynamic Performance for VA = 5 V (Note 3) Specified Temperature Range TA -40 Dynamic Range (Note 2) 18 to 24-Bit unweighted TBD A-Weighted TBD 16-Bit unweighted A-Weighted Total Harmonic Distortion + Noise (Note 2) THD+N 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) CS4340-BS Dynamic Performance for VA = 3 V (Note 3) Specified Temperature Range TA -40 Dynamic Range (Note 2) 18 to 24-Bit unweighted TBD A-Weighted TBD 16-Bit unweighted A-Weighted Total Harmonic Distortion + Noise (Note 2) THD+N 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Interchannel Isolation (1 kHz) Typ 98 101 95 97 -91 -78 -38 -90 -75 -35 102 94 97 93 96 -94 -74 -34 -93 -73 -33 102 Max 85 TBD 85 TBD High-Rate Mode Min -40 TBD TBD -40 TBD TBD Typ 96 100 94 97 -89 -76 -36 -89 -74 -34 102 92 96 92 96 -92 -72 -32 -91 -72 -32 102 Max 85 TBD 85 TBD Unit C dB dB dB dB dB dB dB dB dB dB dB C dB dB dB dB dB dB dB dB dB dB dB
Notes: 3. CS4340-BS parts are tested at the extremes of the specified temperature range and Min/Max performance numbers are guaranteed across the specified temperature range, TA. Typical numbers are taken at 25 C.
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ANALOG CHARACTERISTICS (Continued)
Parameters Symbol Min 0.63*VA VQ (Note 4) (Note 4) RL CL 3 Typ 0.7*VA 0.5*VA 0.1 100 Max 0.77*VA 100 Units Vpp VDC dB ppm/C k pF
Analog Output Full Scale Output Voltage Quiescent Voltage Interchannel Gain Mismatch Gain Drift AC-Load Resistance Load Capacitance
Base-rate Mode
High-Rate Mode
Parameter Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 5) Passband (Note 6) to -0.05 dB corner 0 .4535 Fs to -0.1 dB corner 0 .4621 Fs to -3 dB corner 0 .4998 0 .4982 Fs Frequency Response 10 Hz to 20 kHz -.02 +.08 -0.06 0.2 dB StopBand .5465 .577 Fs StopBand Attenuation (Note 7) 50 55 dB Group Delay tgd 9/Fs 4/Fs s Passband Group Delay Deviation 0 - 40 kHz 1.39/Fs s 0 - 20 kHz 0.36/Fs 0.23/Fs s +.2/-.1 dB De-emphasis Error Fs = 32 kHz +.05/-.14 (Note 8) dB (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz +0/-.22 dB Notes: 4. Refer to Figure 14. 5. Filter response is guaranteed by design. 6. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 5-12) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 7. For Base-Rate Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 8. De-emphasis is not available in High-Rate Mode.
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CS4340
POWER AND THERMAL CHARACTERISTICS
CS4340-KS Parameters Symbol Min normal operation power-down state (Note 9) normal operation power-down normal operation power-down state (Note 9) normal operation power-down JA (Note 10) PSRR (60 Hz) IA IA IA IA Typ 15 60 75 0.3 10 30 30 0.09 110 60 40 Max 18 90 14 42 CS4340-BS Min Typ 15 60 75 0.3 10 30 30 0.09 110 60 40 Max TBD TBD TBD TBD Units mA A mW mW mA A mW mW C/Watt dB dB
Power Supplies Power Supply Current VA = 5 V Power Dissipation VA = 5 V
Power Supply Current VA = 3 V Power Dissipation VA = 3 V Package Thermal Resistance
Power Supply Rejection Ratio (1 kHz) Notes: 9. Refer to Figure 15.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 4. Increasing the capacitance will also increase the PSRR.
DIGITAL CHARACTERISTICS (for -KS parts TA = -10 to 70C; for -BS parts TA = -40 to 85C;
VA = 2.7 V - 5.5 V) Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current VA = 5 V VA = 3 V VA = 5 V VA = 3 V Symbol VIH VIL Iin Min 2.0 2.0 Typ 8 3 Max 0.8 0.8 10 Units V V V V A pF mA
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ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)
Parameters DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA Iin VIND TA Tstg Min -0.3 -0.3 -55 -65 Max 6.0 10 VA+0.4 125 150 Units V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
ground.) Parameters DC Power Supply
(AGND = 0V; all voltages with respect to Min 2.7 Typ 5.0 Max 5.5 Units V
Symbol VA
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CS4340
SWITCHING CHARACTERISTICS (VA = 2.7 V - 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = VA, CL =
20 pF; for -KS parts T A = -10 to 70C; for -BS parts TA = -40 to 85C) Parameters Input Sample Rate MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width Low MCLK Pulse Width Low Base-Rate Mode High-Rate Mode MCLK/LRCK = 512 MCLK/LRCK = 512 MCLK / LRCK = 384 or 192 MCLK / LRCK = 256 or 128 Symbol Fs Min 2 50 10 10 21 21 31 31 40 tsclkl tsclkh tsclkw tsclkw tslrd tslrs tsdlrs tsdh (Note 11) (Note 12) tsclkw tsclkr tsdlrs tsdh tsdh 20 20
1 --------------------( 128 )Fs 1 -----------------( 64 )Fs
Typ 50 50 tsclkw ----------------2
Max 50 100 1000 1000 1000 1000 1000 1000 60 -
Units kHz kHz ns ns ns ns ns ns % ns ns ns ns ns ns ns ns % ns s ns ns ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192 MCLK Pulse Width High MCLK / LRCK = 256 or 128
External SCLK Mode
LRCK Duty Cycle (External SCLK only) SCLK Pulse Width Low SCLK Pulse Width High SCLK Period SCLK Period MCLK / LRCK = 512, 256 or 384 MCLK / LRCK = 128 or 192
SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time
20 20 20 20 1 --------------SCLK
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only) SCLK Period SCLK rising to LRCK edge SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192
1 --------------------- + 10 ( 512 )Fs 1 --------------------- + 15 ( 512 )Fs 1 --------------------- + 15 ( 384 )Fs
-
Notes: 11. In Internal SCLK Mode, the Duty Cycle must be 50% +/- 1/2 MCLK Period. 12. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See figures 16-19)
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LRCK t slrd t slrs t sclkl t sclkh
SCLK t sdlrs
SDATA
t sdh
Figure 1. External Serial Mode Input Timing
LRCK t sclkr SDATA
t sclkw
t sdlrs *INTERNAL SCLK t sdh
Figure 2. Internal Serial Mode Input Timing *The SCLK pulses shown are internal to the CS4340.
LRCK
MCLK 1
*INTERNAL SCLK
N 2
N
SDATA
Figure 3. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4340. N equals MCLK divided by SCLK DS297PP3 11
CS4340
2. TYPICAL CONNECTION DIAGRAM
+ 14 VA 2 Audio Data Processor 3 4 0.1 F 1 F
+5 V to +3 V
SDATA SCLK/DEM1 LRCK CS4340 AOUTL 15
3.3 F + 10 k
560
Left Audio Output C RL
External Clock
5
MUTEC 16 MCLK FILT+ 9 VQ 10 .1 F + 1 F 11 3.3 F AOUTR 12 + 10 k AGND 13 C= C 560 + 0.1 F 1 F
OPTIONAL MUTE CIRCUIT
6 7 Mode Configuration 8 1
DIF1 DIF0 DEM0 RST
REF_GND
Right Audio Output RL RL + 560 4 FSRL 560
Figure 4. Typical Connection Diagram
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3. PIN DESCRIPTION
Reset Serial Data Left/Right Clock Master Clock Digital Interface Format Digital Interface Format De-emphasis RST SDATA LRCK MCLK DIF1 DIF0 DEM0
1 2 3 4 5 6
7
16 15 14 13 12 11
10
MUTEC AOUTL VA AGND AOUTR VQ FILT+
Mute Control Left Analog Output Analog Power Analog Ground Right Analog Output Quiescent Voltage Positive Voltage Reference
Serial Clock / De-emphasis SCLK/DEM1
REF_GND Reference Ground
8
9
RST
1
Reset (Input) - The device enters a low power mode and all internal state machines are reset to the default settings when low. RST should be held low during power-up until the power supply, master and left/right clocks are stable. Serial Audio Data (Input) - Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 16-19. Serial Clock (Input) - Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 16-19. The CS4340 supports both internal and external serial clock generation modes. Internal SCLK mode is used to gain access to extra de-emphasis modes. Internal Serial Clock Mode - In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon the DIF1-0 pins as shown in Figures 16-19. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. External Serial Clock Mode - The CS4340 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
SDATA
2
SCLK
3
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CS4340
DEM1 and DEM0 3 & 8 De-emphasis Control (Input) - Implementation of the standard 15s/50s digital de-emphasis filter response, Figure 20, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis control, DEM1, and all de-emphasis filters are available, Table 3. When using External Serial Clock Mode, as described above, Pin 3 is not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is available, Table 4. NOTE: De-emphasis is not available in High-Rate Mode.
DEM1 0 0 1 1
DEMO 0 1 0 1
DESCRIPTION Disabled 44.1kHz 48kHz 32kHz
Table 1. Internal Serial Clock Mode DEMO 0 1 DESCRIPTION Disabled 44.1kHz
Table 2. External Serial Clock Mode
LRCK 4 Left/Right Clock (Input) - The Left/Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in Figures 16-19. Master Clock (Input) - The master clock frequency must be either 256x, 384x or 512x the input sample rate in Base Rate Mode (BRM) and either 128x or 192x the input sample rate in High Rate Mode (HRM). Table 3 illustrates several standard audio sample rates and the required master clock frequencies.
MCLK
5
MCLK (MHz) Sample Rate (kHz) 32 44.1 48 64 88.2 96 HRM 128x 4.0960 5.6448 6.1440 8.1920 11.2896 12.2880 192x 6.1440 8.4672 9.2160 12.2880 16.9344 18.4320 256x 8.1920 11.2896 12.2880 BRM 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 -
Table 3. Common Master Clock Frequencies
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DIF1 and DIF0 6 & 7 Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 16-19
.
DIF1 0 0 1 1
DIF0 0 1 0 1
DESCRIPTION I2S, up to 24-bit data Left Justified, up to 24-bit data Right Justified, 24-bit Data Right Justified, 16-bit Data
FORMAT 0 1 2 3
FIGURE 16 17 18 19
Table 4. Digital Interface Format - DIF1 and DIF0
FILT+ 9 Positive Voltage Reference (Output) - Positive reference for internal sampling circuits. An external capacitor is required from FILT+ to analog ground, as shown in Figure 4. The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage, typically 50% of VA. Capacitors must be connected from VQ to analog ground, as shown in Figure 4. VQ is not intended to supply external current. VQ has a typical source impedence of 250 k and any current drawn from this pin will alter device performance. Reference Ground (Input) - Ground reference for the internal sampling circuits. Must be connected to analog ground.
VQ
10
REF_GND AOUTR and AOUTL AGND VA MUTEC
11
12 & 15 Analog Outputs (Output) - The full scale analog output level is specified in the Analog Characteristics specifications table. 13 14 16 Ground (Input) - Ground Reference. Analog Power (Input) - Analog power supply. Typically 3 to 5 VDC. Mute Control (Output) - The Mute Control pin goes high during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
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4. APPLICATIONS 4.1 Grounding and Power Supply Decoupling
To prevent transients at power-down, the device must first enter its power-down state by setting the RST pin low. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a softstart current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning off the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds. Use of the Mute Control function is recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340/41 data sheet for a suggested mute circuit.
As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 shows the recommended power arrangement with VA connected to a clean supply. Decoupling capacitors should be located as close to the device package as possible.
4.2
Oversampling Modes
The CS4340 operates in one of two oversampling modes. Base Rate Mode supports input sample rates up to 50 kHz while High Rate Mode supports input sample rates up to 100 kHz. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192.
4.3
RST
Recommended Power-up Sequence
should be held low until the power supply, master and left/right clocks are stable.
4.4
Popguard(R) Transient Control
The CS4340 uses Popguard(R) technology to minimize the effects of output transients during powerup and power-down. This technique, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 left/right clock cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient.
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5. INTERPOLATION FILTER RESPONSE PLOTS
Figure 5. Base-Rate Stopband Rejection
Figure 6. Base-Rate Transition Band
Figure 7. Base-Rate Transition Band (Detail)
Figure 8. Base-Rate Passband Ripple
Figure 9. High-Rate Stopband Rejection
Figure 10. High-Rate Transition Band
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Figure 11. High-Rate Transition Band (Detail)
Figure 12. High-Rate Passband Ripple
3.3 F AOUTx + V out R L C L
AGND
Figure 13. Output Test Load
125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
75 70 Power (mW) 65
HR
M BR
M
60 55
2.5 3
5
10
15
20
50 30 40 50 60 70 80 Sample Rate (kHz) 90 100
Resistive Load -- RL (k )
Figure 14. Maximum Loading
Figure 15. Power vs. Sample Rate (VA = 5V)
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6. DIGITAL INTERFACE FORMATS
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode I2S, 16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 I2S, up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode I2S, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 16. CS4340 Format 0 (I2S)
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode Left Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Left Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 17. CS4340 Format 1
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CS4340
LRCK
Left Channel
Right Channel
SCLK
SDATA
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Internal SCLK Mode Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 18. CS4340 Format 2
LRCK
Left Channel
Right Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 19. CS4340 Format 3
20
DS297PP3
CS4340
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 20. De-Emphasis Curve
7. ANALOG PERFORMANCE PLOTS
The following CS4340 Analog Performance Plots were taken from the CDB4340 evaluation board using the Audio Precision Dual Domain System Two Cascade. All Base Rate Mode (BRM) plots were taken at a 48 kHz sample rate with a 20 Hz to 20 kHz bandwidth using a 20 kHz low-pass brickwall filter in the DSP Analyzer. All High Rate Mode (HRM) plots were taken at a 96 kHz sample rate with a 20 Hz to 40 kHz bandwith using a 40 kHz brickwall filter in the DSP Analyzer.
DS297PP3
21
CS4340
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
Figure 21. FFT 0 dB input, BRM, VA = 3V
+0 -10 -20 -30 -40
Figure 22. FFT -60 dB input, BRM, VA = 3V
+20 +18 +16 +14 +12 +10
-50
+8
d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140
d B r A
+6 +4 +2 +0 -2 -4 -6 -8 -10 -100
2k
4k
6k
8k
10k Hz
12k
14k
16k
18k
20k
-90
-80
-70
-60
-50 dBFS
-40
-30
-20
-10
+0
Figure 23. FFT Idle Noise, BRM, VA = 3V
-85 -86 -87 -88 -89 -90 -91 -92 -93 d B r A -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 -60 -55 -50 -45 -40 -35 -30 dBFS -25 -20 -15 -10 -5 +0 d B r A
Figure 24. Fade-to-Noise Linearity, BRM, VA = 3V
-85 -86 -87 -88 -89 -90 -91 -92 -93 -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 25. THDN vs Ampl, BRM, VA = 3V
Figure 26. THDN vs Freq, BRM, VA = 3V
22
DS297PP3
CS4340
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
d B r A +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
Figure 27. FFT 0 dB input, BRM, VA = 5V
+0 -10 -20 -30 -40 -50
+8 +20 +18 +16 +14 +12 +10
Figure 28. FFT -60 dB input, BRM, VA = 5V
d B r A
-60 -70 -80 -90 -100 -110 -120 -130 -140 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
d B r A
+6 +4 +2 +0 -2 -4 -6 -8 -10 -100
-90
-80
-70
-60
-50 dBFS
-40
-30
-20
-10
+0
Figure 29. FFT Idle Noise, BRM, VA = 5V
-85 -86 -87 -88 -89 -90 -91 -92 -93 d B r A -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 -60 -55 -50 -45 -40 -35 -30 dBFS -25 -20 -15 -10 -5 +0
d B r A
Figure 30. Fade-to-Noise Linearity, BRM, VA = 5V
-85 -86 -87 -88 -89 -90 -91 -92 -93 -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 31. THDN vs Ampl, BRM, VA = 5V DS297PP3
Figure 32. THDN vs Freq, BRM, VA = 5V 23
CS4340
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 5k 10k 15k 20k Hz 25k 30k 35k 40k
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 5k 10k 15k 20k Hz 25k 30k 35k 40k
Figure 33. FFT 0 dB input, HRM, VA = 3V
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90
Figure 34. FFT -60 dB input, HRM, VA = 3V
+20 +18 +16 +14 +12 +10 +8 d B r A +2 +0 +6 +4
-100
-2
-110
-4
-120
-6
-130 -140 5k 10k 15k 20k Hz 25k 30k 35k 40k
-8 -10 -100
-90
-80
-70
-60
-50 dBFS
-40
-30
-20
-10
+0
Figure 35. FFT Idle Noise, HRM, VA = 3V
-85 -86 -87 -88 -89 -90 -91 -92 -93 d B r A -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 -60 -55 -50 -45 -40 -35 -30 dBFS -25 -20 -15 -10 -5 +0
Figure 36. Fade-to-Noise Linearity, HRM, VA = 3V
-85 -86 -87 -88 -89 -90 -91 -92 -93 d B r A -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 20 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 37. THDN vs Ampl, HRM, VA = 3V 24
Figure 38. THDN vs Freq, HRM, VA = 3V DS297PP3
CS4340
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 5k 10k 15k 20k Hz 25k 30k 35k 40k
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 5k 10k 15k 20k Hz 25k 30k 35k 40k
Figure 39. FFT 0 dB input, HRM, VA = 5V
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90
Figure 40. FFT -60 dB input, HRM, VA = 5V
+20 +18 +16 +14 +12 +10 +8 d B r A +2 +0 +6 +4
-100
-2
-110
-4
-120 -130 -140
-6 -8
5k 10k 15k 20k Hz 25k 30k 35k 40k
-10 -100
-90
-80
-70
-60
-50 dBFS
-40
-30
-20
-10
+0
Figure 41. FFT Idle Noise, HRM, VA = 5V
-85 -86 -87 -88 -89 -90 -91 -92 -93 d B r A -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 -60 -55 -50 -45 -40 -35 -30 dBFS -25 -20 -15 -10 -5 +0
Figure 42. Fade-to-Noise Linearity, HRM, VA = 5V
-85 -86 -87 -88 -89 -90 -91 -92 -93 d B r A -94 -95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105 20 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 43. THDN vs Ampl, HRM, VA = 5V DS297PP3
Figure 44. THDN vs Freq, HRM, VA = 5V 25
CS4340
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
9. REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4340 Evaluation Board Datasheet
26
DS297PP3
CS4340
10. PACKAGE DIMENSIONS
16L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1 b c
D SEATING PLANE e A1
A L
DIM A A1 b C D E e H L
MIN 0.053 0.004 0.013 0.0075 0.386 0.150 0.040 0.228 0.016 0
INCHES NOM 0.064 0.006 0.016 0.008 0.390 0.154 0.050 0.236 0.025 4
MAX 0.069 0.010 0.020 0.010 0.394 0.157 0.060 0.244 0.050 8
MIN 1.35 0.10 0.33 0.19 9.80 3.80 1.02 5.80 0.40 0
MILLIMETERS NOM 1.63 0.15 0.41 0.20 9.91 3.90 1.27 6.0 0.64 4
MAX 1.75 0.25 0.51 0.25 10.00 4.00 1.52 6.20 1.27 8
JEDEC #: MS-012
Controling Dimension is Millimeters
DS297PP3
27

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