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BA7078AF/AS
Multimedia ICs
Synchronization signal processor for high definition displays
BA7078AF/AS
The BA7078AF is a synchronization signal processing LSI chip designed for multiscan high-definition displays. It generates a synchronization signal and clamp pulse for three types of input signals: separate synchronization, composite synchronization, and synchronization on video.
!Application CRT displays
!Features 1) Operates on a single 5V power supply, with low power consumption. 2) Synchronization signal existence and polarity detec-tion output. 3) Adjustable clamp pulse width, allowing for the selec-tion of front or back editing. 4) Vertical synchronization separation is based on hori-zontal frequency tracking, for separation starting at 1H. 5) Minimal attached components.
!Absolute maximum ratings (Ta = 25C)
Parameter Power supply voltage Power dissipation Operating temperature Symbol VCC
1
Limits 7.0 450(BA7078AF) 600(BA7078AS) -25 to +75
2
Unit V mW C C
Pd Topr
-55 to +125 Tstg Storage temperature 1 Reduced by 4.5mW for each increase in Ta of 1C over 25C. 2 Reduced by 6.0mW for each increase in Ta of 1C over 25C.
!Recommended operating conditions (Ta = 25C)
Parameter Power supply voltage Symbol VCC Min. 4.5 Typ. 5.0 Max. 5.5 Unit V
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Multimedia ICs
!Block diagram
HSCTL
1
18
POLH
C / HSYNC IN
2
H SYNC DET.
17
EXIH
VIDEO IN
3 SYNC SEPA.
16
POLV
VSEPA
4
HOR. SYNC CONTROL V SYNC SEPA.
15
EXIV
VSYNC IN
5
14
Vcc
CVPOL
6 V SYNC DET.
13
HDRV
CVEXI
7
12
CLAMP
CPSEL
8
CLAMP PULSE GEN.
11
VDRV
GND
9
10
CPWID
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Multimedia ICs
!Pin descriptions
Pin No. Pin name
Functions Used to select whether to output the VDRV section of the HDRV output signal. High : VDRV section of HDRV is output Low : VDRV section of HDRV is not output Input either the composite synchronization signal or the horizontal synchronization signal. Input is clamped, and is initiated by capacitor coupling. Inputs the SYNC ON VIDEO signal(green). Input is sink chip clamped. Input is initiated by capacitor coupling. Converts the horizontal synchronization signal frequency into a voltage. The voltage generated is proportional to the frequency of the horizontal synchronization signal. Attach a 0.56F capacitor between the ground pins. Inputs the vertical synchronization signal. Integrates the vertical synchronization signal polarity detection circuit. Attach a 1.5F capacitor between this pin and the ground. Integrates the vertical synchronization signal existence detection circuit. Attach a 1F capacitor between this pin and the ground. Used to set the clamp pulse generation position to either the front or back edge of HSYNC High : The front edge is the generation position Open : Composite / H SYNC IN : The front edge is the generation position VIDEO IN : The back edge is the generation position Low : The back edge is the generation position - Sets the clamp pulse width according to the attached time constant. Attach a resistor between this pin and VCC and, a capacitor between this pin and GND. When R = 3.9k and C = 100pF, pulse width is approximately 400 ns. Set the resistor to register an abnormality at 1k. Outputs the vertical synchronization signal. The output signal has positive polarity. Outputs the clamp pulse generated from the vertical synchronization signal. The output signal has a positive polarity. Outputs the clamp pulse generated from the horizontal synchronization signal. The output signal has positive polarity. - Indecates whether the vertical synchronization signal exists. For the output logic, refer to the separate table. Indicates the polarity of the vertical synchronization signal. For the output logic, refer to the separate table. Indicates whether the horizontal synchronization signal exists. For the output logic, refer to the separate table. Indicates the polarity of the horizontal synchronization signal. For the output logic, refer to the separate table.
1
HSCTL
HDRV output
2
C / HSYNC IN
Composite sync / H SYNC input SYNC ON VIDEO input
3
VIDEO IN
4
VSEPA
f-V conversion
5 6 7
VSYNC IN CVPOL CVEXI
V SYNC input Vertical polarity integration Vertical existence integration
8
CPSEL
Setting the clamp position
9
GND
Ground
10
CPWID
Setting the clamp pulse width
11 12 13 14 15 16 17 18
VDRV CLAMP HDRV VCC EXIV POLV EXIH POLH
VDRV output Clamp output HDRV output Power supply Vertical existence output Vertical polarity output Horizontal existence output Horizontal polarity output
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BA7078AF/AS
Multimedia ICs
!Input / output circuits
HSCTL
VSEPA
C / HSYNC IN
VCC
VCC
VCC 670
60k
51k 1pin
1k 4pin
200 2pin
30k
10A
VSYNC IN
VCC
VIDEO IN
VCC 2k
CVPOL
VCC
200
5pin
200 6pin
3pin
CVEXI
VCC
CPWID
VCC
CPSEL
VCC
50k
1k
7pin
10pin
8pin
50k
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BA7078AF/AS
Multimedia ICs
VDRV
GND
CLAMP
VCC
VCC
9pin
12pin
11pin
HDRV
VCC
POLV
VCC
VCC
VCC
10k
13pin
16pin
14pin
EXIH
VCC
EXIV
VCC
POLH
VCC
10k
10k
10k
17pin
15pin
18pin
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Multimedia ICs
!Electrical characteristics (unless otherwise noted, VCC = 5V, Ta = 25C)
Parameter Power supply voltage Quiescent current VDRV output voltage "H" VDRV output voltage "L" VDRV output current "L" VDRV rising delay time HDRV output voltage "H" HDRV output voltage "L" HDRV output current "L" HDRV rising delay time (1) HDRV rising delay time (2) CLAMP output voltage "H" CLAMP output voltage "L" CLAMP output current "L" CLAMP rising delay time (1) CLAMP rising delay time (2) Synchronization detection output voltage "H" Synchronization detection output voltage "L" Synchronization detection output current "L" Synchronization detection output impedance Minimum synchronization separation level HSCTL "H" level threshold voltage HSCTL "L" level threshold voltage CPSEL "H" level threshold voltage CPSEL "L" level threshold voltage Symbol VCC ICC V VDH V VDL I VDL trdVD V HDH V HDL I HDL trdHD1 trdHD2 V CPH V CPL I CPL trdCP1 trdCP2 V DH V DL I DL Z oD V SMin. V tHSH V tHSL V tCPH V tCPL Min. 4.5 21 4.5 - 8 - 4.5 - 8 - - 4.5 - 8 - - 4.5 - 3 7 - 2.5 - 3.8 - Typ. 5.0 30 5.0 0.2 - 280 5.0 0.2 - 65 95 5.0 0.2 - 75 95 5.0 0.2 - 10 - - - - - Max. 5.5 39 - 0.5 - 450 - 0.5 - 115 145 - 0.5 - 125 145 - 0.5 - 13 0.2 - 1.5 - 1.2 Unit V mA V V mA ns V V mA ns ns V V mA ns ns V V mA k VP-P V V V V front edge back edge C / HSYNC IN VIDEO IN VSYNC IN Conditions
!Synchronization signal detection chart
INPUT Composite / HSYNC H. COMP (Positive) VSYNC No signal Positive Negative No signal H. COMP (Negative) Positive Negative No signal No signal Positive Negative EXIH H H H H H H L L L OUTPUT EXIV L H H L H H L H H POLH L L L H H H L L L POLV L L H L L H L L H
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Multimedia ICs
!Relationship between INPUT to OUTPUT
INPUT Composite / HSYNC - - - - - : No Signal - - - - - -
Explanation of symbol : Signal Input
OUTPUT VSYNC - - VIDEO HDRV VIDEO CS VIDEO CS - CS - CS VDRV VIDEO CS VS VS - CS VS VS CLAMP VIDEO CS VIDEO CS - CS - CS
!Input signal range
Parameter Polarity
Amplitude (Sync) : Vs (Video) : Vv Vert. sync frequency range : fV Vert. sync pulse width range : pwV Hor. sync frequency range : fH
Vert. separate sync Hor. separate sync Posi. / Neg. 1.0 to 5.0VP-P Posi. / Neg. 1.0 to 5.0VP-P - - 15k to 200kHz 94ns to Duty35%
Composite sync Posi. / Neg. 1.0 to 5.0VP-P
Sync on Video Neg. 0.2 to 0.6VP-P 0 to 2.1VP-P
40 to 200Hz 8.0s to Duty35% - -
40 to 200Hz 1HMin. to 400s 15k to 200kHz 94ns to Duty30%
40 to 200Hz 1HMin. 15k to 200kHz Duty30% Max.
Hor. sync pulse width range : pwH
1H = 1 / fH
!Input signal waveform
Vert. / Hor.separate sync T=1/f
VS
pw
Duty=pw/T(%)
Composite sync TH=1/fH
VS
pwH Duty=pwH/TH(%)
pwV (ex.pwV=1H)
Sync on Video
VV
VS pwH TH=1/fH
Duty=pwH/TH(%)
pwV (ex.pwV=1H)
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Multimedia ICs
!Measurement circuit
1
HSCTL
POLH
18 1
SW18 2 3 4
V1
V
3mA
V Oscilloscope
A
SW2 1 2 4.7F 4.7F 75 V2 3
2
C / HSYNC IN
EXIH
17 1
SW17 2 3 4 A Oscilloscope
V
3mA
V
SW3 1 2 1F 1F 75 V3 3
3
VIDEO IN
POLV
16 1
SW16 2 3 4 A Oscilloscope
V
3mA
V
4 0.56F
VSEPA
EXIV
15 1
SW15 2 3 4
V
3mA
V Oscilloscope Vcc 5V
A
SW5 1 4.7F 75 1M V5 2 3
5
VSYNC IN
VCC
14
A 0.01F 47F
6 1.5F
CVPOL
HDRV
13 1
SW13 2 3
V
8mA
V Oscilloscope
7 1F
CVEXI
CLAMP
12 1
SW12 2 3
V
8mA
V Oscilloscope
8
CPSEL
VDRV
11 1
SW11 2 3
V8
V
8mA
V Oscilloscope
9
GND
CPWID
10
VCC 3.9k
100pF
Fig.1
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Multimedia ICs
!Conditions for measurement of electrical characteristics
Switch condition Parameter
Quiescent current VDRV output voltage "H" VDRV output voltage "L" VDRV output current "L" VDRV rising delay time HDRV output voltage "H" HDRV output voltage "L" HDRV output current "L" HDRV rising delay time (1) HDRV rising delay time (2) CLAMP output voltage "H" CLAMP output voltage "L" CLAMP output current "L" CLAMP rising delay time (1) CLAMP rising delay time (2) POLH output voltage "H" POLH output voltage "L" POLH output current "L" POLH output impedance EXIH output voltage "H" EXIH output voltage "L" EXIH output current "L" EXIH output impedance POLV output voltage "H" POLV output voltage "L" POLV output current "L" POLV output impedance EXIV output voltage "H" EXIV output voltage "L" EXIV output current "L" EXIV output impedance Minimum synchronization separation level HSCTL "H" level threshold voltage HSCTL "L" level threshold voltage CPSEL "H" level threshold voltage CPSEL "L" level threshold voltage
2 1 1 1 1 1 3 3 3 2 1 2 2 3 2 1 2 2 3 3 2 1 3 3 1 1 1 1 1 1 1 1 1 2 2 1 2
3 1 1 1 1 1 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 1
5 1 3 3 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 2 1 3 3 1 2 2 1 1
11 1 1 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 1 1 1 1 1 1 1 1 1 1 3 3 2 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3
13 1 1 1 1 1 1 1 2 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3
15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1
16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1
17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1
18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Multimedia ICs
!Application example
HSCTL
1
18
POLH
C / H SYNC IN
C1 4.7F C2 1F
2
H SYNC DET.
17
EXIST H
VIDEO IN
3 SYNC SEPA.
16
POLV
4 C3 0.56F 0.47F C7 R2 1M 6 C4 1.5F V SYNC DET. 7 C5 1F 8 V SYNC SEPA. 5 HOR. SYNC CONTROL
15
EXIST V
Vcc 5V 14 0.01F 47F
VSYNC IN
13
HDRV
12
CLAMP
CPSEL OPEN : AUTO H : Front L : Back
CLAMP PULSE GEN.
11 Vcc
VDRV
9
10
R1
3.9k
C6
100pF
Fig.2
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Multimedia ICs
!Attached components R: The resistor for limiting the LED current. Use the resistor of not less than 1W. C1 : 47F Coupling capacitor for C / H SYNC IN A low capacitance increases the size of the input pin waveform's sag. Coupling capacitor for VIDEO IN A low capacitance increase the size of the input pin waveform's sag. Conversion capacitor for f-V A low capacitance increase the size of the ripple of the f-V conversion voltage. A large capacitance is not a problem, but will delay the reaction speed. Capacitor for POLH (detection of the vertical synchronization signal's polarity) The minimum capacitance is determined as follows: The internal hysteresis comparator does not react when the duty of minimum frequency synchronization (fV = 40Hz, T = 25ms) is 50%. CMin. = 16 x T [F] A large capacitance is not a probrem, built will deray the reaction speed. Capacitor for EXIH (detection of the vertical synchronization signal's existance) The minimum capacitance is determined as follows: The internal hysteresis comparator does not react at the minimum frequency synchronization (fV = 40Hz, T = 25ms) CMin. = 16 x T [F] A large capacitance is not a problem, but will deray the reaction speed. Constant for setting the clamp pulse width
R RPM-850 LED
C2 : 1F
C3 : 0.56F
C4 : 1.5 F
C5 : 1F
C6 : 100pF
C7 : 0.47F Coupling capacitor for VSYNC IN A low capacitance increases the size of the input pin waveform's sag. R1 : 3.9k R2 : 1M A low resistance results in a narrow clamp pulse width. Set no lower than 1k. Discharge current setting resistor for CLAMP IN
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Multimedia ICs
!Electrical characteristic curves
PROPAGATION DELAY OF RISE TIME : trdhd (ms) PROPAGATION DELAY OF RISE TIME : trdcl (ns)
90 80 70 60 50 40 30 20 10 0 -50 VCC=5.0V -25 0 25 50 75 100
Output position : front edge 120 100 80 60 40 20 Vcc=5.0V 0 -50 -25 0 25 50 75 100
PROPAGATION DELAY OF RISE TIME : trdhd (ns)
100
140
160 140 120 100 80 60 40 20 Vcc=5.0V 0 -50 -25 0 25 50 75 100
TEMPERATURE : Ta(C)
TEMPERATURE : Ta (C)
TEMPERATURE : Ta (C)
Fig.3 C / HSYNC IN-HDRV Rising delay time vs. temperature
Fig.4 C / HSYNC IN-CLAMP Rising delay time vs. temperature
Fig.5 VIDEO IN-HDRV Rising delay time vs. temperature
PROPAGATION DELAY OF RISE TIME : trdcl (ns)
Output position back edge 120 100 80 60 40 20 Vcc=5.0V 0 -50 -25 0 25 50 75 100
PROPAGATION DELAY OF RISE TIME : trdvd (ns)
140
260 240 220 200 180 160 140 120 VCC=5.0V 100 -50 -25 0 25 50 75 100
PIN VOLTAGE : VS (V)
3 2.5 2
1.5 1 0.5
VCC=5.0V
0 0
20 40 60 80 100 120 140 160 180 200 HORIZONTAL FREQUENCY : fH (kHz)
TEMPERATURE : Ta (C)
TEMPERATURE : Ta (C)
Fig.6 VIDEO IN-CLAMP Rising delay time vs. temperature
Fig.7 VSYNC IN-VDRV Rising delay time vs. temperature
Fig.8 VSEPA horizontal frequency vs. pin voltage
!External dimensions (Unit : mm)
BA7078AF
BA7078AS
11.20.2
19.4 0.3
18
7.80.3 5.40.2
10
18 10
6.5 0.3
0.150.1
0.51Min.
1
9
1
1.80.1
9
3.95 0.3
7.62
0.11
1.27
0.40.1
0.3Min. 0.15
3.4 0.2
0.3 0.1
1.778 0.5 0.1 0 15
SOP18
SDIP18
12/12
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document use silicon as a basic material. Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of with would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. About Export Control Order in Japan Products described herein are the objects of controlled goods in Annex 1 (Item 16) of Export Trade Control Order in Japan. In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause) on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction.
Appendix1-Rev1.0

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