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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75402A(A)
4 BIT SINGLE-CHIP MICROCOMPUTER
The PD75402A(A) is a CMOS single-chip microcomputer which uses the 75X series architecture. It operates at high speed with a minimum instruction execution time of 0.95 s. The PD75P402 is also available for system development evaluation. It contains one-time PROM instead of mask ROM used in the PD75402A(A). The following user's manual describes the details of the functions of the PD75402A(A). Be sure to read it before designing an application system.
PD75402A User's Manual: IEU-644
FEATURES * More reliable than the PD75402A * High-speed operation with a minimum instruction execution time of 0.95 s (when the microcomputer
operates at 4.19 MHz)
* Low voltage and low-speed instruction execution time of 15.3 s (when the microcomputer operates at
4.19 MHz)
* * * *
Memory mapping by on-chip peripheral hardware NEC standard serial bus interface (SBI) 8-bit basic interval timer (watchdog timer applicable) Interrupt function * * Three vectored interrupts (one external and two internal interrupts) One external test input
* Clock output function (remote controller output applicable) * Capable of specifying the incorporation of 16 pull-up resistors by software APPLICATIONS
Electronic units for automobiles, and suchlike
ORDERING INFORMATION
Part number Package 28-pin plastic DIP (600 mil) 28-pin plastic shrink DIP (400 mil) 44-pin plastic QFP (10 x 10 mm) Quality grade Special Special Special
PD75402AC(A)-xxx PD75402ACT(A)-xxx PD75402AGB(A)-xxx-3B4
Remark xxx indicates the ROM code number.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. IC-2841B (O.D.No. IC-8273B) Date Published November 1993 P Printed in Japan
Major changes in this revision are indicated by stars (
) in the margins.
1 (c) NEC CORPORATION 1991 1990 (c)
PD75402A(A)
DIFFERENCES BETWEEN THE PD75402A(A) AND PD75402A
Product Item Quality grade
PD75402A(A)
Special
PD75402A
Standard
FUNCTIONAL OVERVIEW
Item Number of basic instructions Minimum instruction execution time Built-in memory General register I/O line ROM RAM 37 0.95, 1.91, or 15.3 s (when operating at 4.19 MHz) Switchable among three speeds Function
* *
1920 x 8 bits 64 x 4 bits 4 bits x 4 or 8 bits x 2 (memory mapping) * * * * * * * CMOS input ports : 6 lines CMOS I/O ports : 12 lines (8 lines can drive the LED directly.) N-ch open-drain I/O ports : 4 lines (All lines can drive the LED directly.) Capable of controlling the incorporation of 16 pull-up resistors by software Capable of controlling the incorporation of 4 pull-up resistors by mask option 1.05 MHz, 524 kHz, or 65.5 kHz (when operating at 4.19 MHz) Applicable to remote controller output
Pull-up resistor
Clock output
Timer/counter Serial interface
8-bit basic interval timer (watchdog timer applicable) * * 8 bits Two transfer modes (three-wire synchronous mode and SBI mode)
Vectored interrupt Test input Standby Instruction set
One external and two internal interrupts One external input (See Chapter 6 for details.) STOP/HALT mode * * * * * * * Bit manipulation instructions (set, clear, test, and Boolean operation) 1-byte relative branch instructions 4-bit operation instructions (add, Boolean operation, and compare) 4- and 8-bit transfer instructions 28-pin plastic DIP (600 mil) 28-pin plastic shrink DIP (400 mil) 44-pin plastic QFP (10 x 10 mm)
Package
2
PD75402A(A)
CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ...................................................................................... BLOCK DIAGRAM ...................................................................................................................... PIN FUNCTIONS .......................................................................................................................
3.1 3.2 3.3 3.4 3.5 3.6 PORT PINS ..................................................................................................................................... NON-PORT PINS ........................................................................................................................... PIN INPUT/OUTPUT CIRCUITS .................................................................................................. SELECTION OF A MASK OPTION ........................................................................................... HANDLING UNUSED PINS ......................................................................................................... NOTES ON USING THE P00 AND RESET PINS .................................................................
4 6 7
7 8 8 10 11 11
4. 5.
MEMORY CONFIGURATION ................................................................................................... PERIPHERAL HARDWARE FUNCTIONS ................................................................................
5.1 5.2 5.3 5.4 5.5 PORTS .............................................................................................................................................. CLOCK GENERATOR .................................................................................................................... CLOCK OUTPUT CIRCUIT ........................................................................................................... BASIC INTERVAL TIMER ............................................................................................................ SERIAL INTERFACE ......................................................................................................................
12 14
14 15 16 17 18
6. 7. 8. 9.
INTERRUPT FUNCTION ........................................................................................................... STANDBY FUNCTION .............................................................................................................. RESET FUNCTION .................................................................................................................... INSTRUCTION SET ...................................................................................................................
20 22 23 25 29 38 42 43 44 45
5
10. ELECTRICAL CHARACTERISTICS ........................................................................................... 11. PACKAGE DIMENSIONS .......................................................................................................... 12. RECOMMENDED SOLDERING CONDITIONS ......................................................................... APPENDIX A DIFFERENCES BETWEEN THE PD75402A(A) AND PD75P402 ................... APPENDIX B DEVELOPMENT TOOLS ......................................................................................... APPENDIX C RELATED DOCUMENTS ........................................................................................
3
PD75402A(A)
1. PIN CONFIGURATION (TOP VIEW)
28-pin plastic DIP (600 mil), 28-pin plastic shrink DIP (400 mil)
Note
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD X1 X2 P12 /INT2 P10/INT0 P23 P22 /PCL P21 P20 P63 P62 P61 P60 P33
RESET P00 P01/SCK P02/SO/SB0 P03/SI P50 P51 P52 P53 P30 P31 P32 VSS
PD75402AC(A)/CT(A)- xxx
P00 - P03 P20 - P23 P30 - P33 P50 - P53 P60 - P63
: Port 0 : Port 2 : Port 3 : Port 5 : Port 6
SCK SO/SB0 SI PCL INT0 INT2 RESET VDD VSS NC
: Serial clock I/O : Serial output/input-output : Serial input : Clock output : External vectored interrupt input : External test input : Reset input : Power supply : Ground : No connection
P10 and P12: Port 1
X1 and X2 : Oscillating pins
Note When the PD75402A(A) shares the printed circuit board with the PD75P402, connect the NC pin directly to the VSS pin.
4
PD75402A(A)
44-pin plastic QFP (10 x 10 mm)
P02/SO/SB0
35
P03/SI
P53
P52
P51
P50
NC
NC
NC
NC
44 43 42 P30 P31 P32 NC VSS NC NC P33 P60 P61 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14
41
40
39
38
37
36
34 33 32 31 30 29
NC
P01/SCK P00 RESET NC NC NC NC VDD X1 X2 NC
Note
PD75402AGB(A)- xxx -3B4
28 27 26 25 24
15
16
17
18
19
20
21
23 22
P10/INT0
Note When the PD75402A(A) shares the printed circuit board with the PD75P402, connect the NC pin (pin 30) directly to the VSS pin.
P12/INT2
P22/PCL
P62
P63
P20
P21
P23
VSS
NC
NC
5
6
Basic interval timer INTBT Port 0 Program counter (11) ALU CY SP Port 1 2 P10, P12 4 P00 - P03 Port 2 SI SO/SB0 SCK Serial interface INTCSI ROM Program memory 1920 x 8 bits General register Decode and control 4 P20 - P23 Port 3 4 P30 - P33 RAM Data memory 64 x 4 bits Port 5 4 P50 - P53 INT0 INT2 Interrupt control Port 6 4 P60 - P63 fXX/2N Clock output control Clock divider Clock generator Standby control CPU Clock PCL X1 X2 VDD VSS RESET
2. BLOCK DIAGRAM
PD75402A(A)
PD75402A(A)
3.
3.1
PIN FUNCTIONS
PORT PINS
Dualfunction pin - SCK SO/SB0 SI INT0 2-bit input port (port 1) P10 connects with the built-in noise eliminator using a sampling clock. P12 connects with the built-in noise eliminator using an analog delay. P12 allows the connection of built-in pull-up resistor to be specified by software. 4-bit I/O port (port 2) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software.
Pin P00 P01 P02 P03 P10
I /O Input I/O I/O Input Input
Function 4-bit input port (port 0) P01 to P03 allow the connection of built-in pull-up resistors to be specified in units of three bits by software.
P12
INT2
P20 P21 P22 P23 P30 - P33
I/O
- - PCL -
I/O
-
Programmable 4-bit I/O port (port 3) Allow I/O specification bit by bit. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software. Can directly drive LED. 4-bit N-ch open-drain I/O port (port 5) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified bit by bit by mask option. Can directly drive LED. 4-bit I/O port (port 6) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software. Can directly drive LED.
P50 - P53
I/O
-
P60 - P63
I/O
-
Remarks 1. The PD75402A(A) cannot perform 8-bit I/O with two ports as a pair. 2. See Chapter 8 for each pin status during resetting.
7
PD75402A(A)
3.2 NON-PORT PINS
Pin INT0 I /O Input Dualfunction pin P10 Function Edge detection vectored interrupt request input pin (A detected edge can be selected by the mode register.) Connects with the built-in noise eliminator using a sampling clock. Edge detection external test input pin (A rising edge is detected.) Serial data input pin Serial data output pin Serial clock I/O pin Serial bus I/O pin Clock output pin Pin for connection to a crystal/ceramic resonator for system clock generation. An external clock is applied to X1, and its reverse phase to X2. System reset input pin, which connects with the built-in noise eliminator using an analog delay. Positive power supply pin Ground potential pin No connection
INT2 SI SO SCK SB0 PCL X1, X2
Input Input I/O I/O I/O I/O Input
P12 P03 P02/SB0 P01 P02/SO P22 -
RESET
Input
-
VDD VSS NC
Note
- - -
- - -
Remark See Chapter 8 for each pin status during resetting. Note Connect the NC pin directly to the VSS pin when the PD75402A(A) shares the printed circuit board with the PD75P402 in emulation. 3.3 PIN INPUT/OUTPUT CIRCUITS
The I/O circuits of the PD75402A(A) are roughly shown on the next and subsequent pages. Table 1-1 I/O Circuit Type of Pin
Pin P00 P01 /SCK P02 / SO/ SB0 P03 / SI P10 / INT0 P12 /INT2 I /O type
B F -A
Pin P20, P21, and P23 P22 /PCL P30 - P33 P50 - P53 P60 - P63 RESET
I/O type E-B
F -B
B -C B
E-B M E-B
B -C
B
Remark The types in circles have a Schmitt-triggered input.
8
PD75402A(A)
(1/2)
Type A (For type E-B) Type D (For type E-B, F-A) VDD Data P-ch IN Output disable N-ch P-ch OUT
VDD
N-ch
CMOS input buffer Type B
Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable P-ch
IN
Data Type D Output disable
IN/OUT
Type A
Schmitt trigger input with hysteresis Type B-C Type F-A
P.U.R.: Pull-Up Resistor
VDD VDD P.U.R. P.U.R. P.U.R. enable P.U.R. enable Data Type D Output disable IN
Type B
P-ch
P-ch
IN/OUT
P.U.R.: Pull-Up Resistor
P.U.R.: Pull-Up Resistor
9
PD75402A(A)
(2/2)
Type F-B VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch VDD P-ch IN/OUT P-ch Data Output disable N-ch (Withstand voltage: +10 V) P.U.R. enable (Mask option) Type M VDD
IN/OUT
Input buffer with an intermediate withstand voltage of +10 V P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor
3.4
SELECTION OF A MASK OPTION
The following mask options are provided for pins:
P50 - P53
1 Pull-up resistors connected (Either can be specified bit by bit.)
2 No pull-up resistors connected
10
PD75402A(A)
3.5 HANDLING UNUSED PINS
Pin P00 P01 - P03 P10, P12 Recommended connection method Connected to the VSS pin * * When a pull-up resistor is contained Connected to the VDD pin When a pull-up resistor is not contained Connected to the VSS or VDD pin When a pull-up resistor is contained Input mode : Connected to the VDD pin Output mode : Open When a pull-up resistor is not contained Input mode : Connected to the VSS or VDD pin Output mode : Open
P20 - P23 P30 - P33 P50 - P53 P60 - P63 NC
*
*
Open or directly connected to the VSS pin Note
Note When the PD75402A(A) shares the printed circuit board with the PD75P402, connect the NC pin directly to VSS pin. 3.6 NOTES ON USING THE P00 AND RESET PINS
The P00 and RESET pins have the test mode selecting function for testing the internal operation of the
PD75402A(A) (IC test), besides the functions shown in Sections 3.1 and 3.2.
Applying a voltage exceeding VDD to the P00 and/or RESET pin causes the PD75402A(A) to enter the test mode. When noise exceeding VDD comes in during normal operation, the device is switched to the test mode. For example, when the wiring from the P00 or RESET pin is too long, noise voltage induced on the wiring is applied to the pin, driving the voltage at the pin above VDD, which may cause malfunction. When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If noise yet arises, use an external part to suppress it as shown below. * Connect a diode with low VF (0.3 V or lower) between the pin and VDD.
VDD
VDD
* Connect a capacitor between the pin and VDD.
Diode with low VF P00, RESET
VDD
VDD
P00, RESET
11
PD75402A(A)
4. MEMORY CONFIGURATION
* Program memory (ROM): 1920 x 8 bits (000H to 77FH)
* 000H and 001H : Vector table which contains the program start address after reset * 002H to 009H : Vector table which contains the program start addresses when interrupts occur Data memory * Data area : 64 x 4 bits (000H to 03FH) * Peripheral hardware area: 128 x 4 bits (F80H to FFFH) Fig. 4-1 Program Memory Map
7 Address 000H 0 0 0 0 0 Reset start address (three high-order bits) 6 5 4 3 0
*
001H
Reset start address (eight low-order bits) INTBT start address (three high-order bits) Entry address specified in CALLF !faddr instruction
002H
0
0
0
0
0
003H
INTBT start address (eight low-order bits) INT0 start address (three high-order bits)
004H
0
0
0
0
0
005H
INT0 start address (eight low-order bits)
Branch address specified in BRCB !caddr instruction
008H
0
0
0
0
0
INTCSI start address (three high-order bits)
Relative branch address specified in BR $addr instruction -15 to -1, +2 to +16
009H
INTCSI start address (eight low-order bits)
77FH
12
PD75402A(A)
Fig. 4-2 Data Memory Map
General register area
000H 003H 004H
(4 x 4)
Data area Static RAM (64 x 4)
020H
Bank 0 (64 x 4)
Stack area
(32 x 4)
03FH
No memory
F80H
Peripheral hardware area
128 x 4
Bank 15
FFFH
13
PD75402A(A)
5.
5.1
PERIPHERAL HARDWARE FUNCTIONS
PORTS
The PD75402A(A) has the following three types of I/O port: * 6 CMOS input pins (PORT0 and PORT1) * 12 CMOS I/O pins (PORT2, PORT3, and PORT6) * 4 N-ch open-drain I/O pins (PORT5) Total: 22 pins Table 5-1 Functions of Ports
Port name PORT0 PORT1 PORT3 Note Function 4-bit Input Operation and feature Allows read and test at any time regardless of the operation modes of dual function pins. Allows input or output mode setting bit by bit. Allows input or output mode setting in units of 4 bits. 4-bit I/O (N-ch open-drain I/O with a withstand voltage of 10 V) Allows input or output mode setting in units of 4 bits. Remarks Also used for SO/SB0, SI, SCK, INT0, and INT2.
4-bit I/O
--
PORT2 PORT6 Note PORT5 Note
Port 2 is also used for PCL.
This port can incorporate a pull-up resistor as a mask option bit by bit.
Note PORT3, PORT5, and PORT6 can directly drive the LED.
14
PD75402A(A)
5.2 CLOCK GENERATOR
Operation of the clock generator is specified by the processor clock control register (PCC). The instruction execution time is variable. * 0.95 s, 1.91 s, 15.3 s (when fXX is 4.19 MHz.) Fig. 5-1 Block Diagram of the Clock Generator
X1 VDD System clock oscillator X2 fXX or fX * Basic interval timer (BT) * Clock output circuit * Serial interface * INT0 noise eliminator
1/16 to 1/512 Frequency divider 1/2 1/16 Oscillation stops. Frequency divider 1/4
* CPU * INT0 noise eliminator * Clock output circuit
Selector
PCC PCC0
Internal bus
PCC1 4 HALT* PCC2 HALT flipflop S
STOP*
PCC3 R All bits are cleared. Q
PCC2 is cleared.
STOP flipflop Q S
RESET input rising edge detection signal
RESET input falling edge detection signal R Standby release signal from interrupt control circuit
Remarks 1. fXX = Crystal/ceramic oscillated frequency 2. fX = External clock frequency 3. = CPU clock 4. An asterisk (*) indicates instruction execution. 5. PCC: Processor clock control register 6. One clock cycle (tCY) of is equal to one machine cycle of an instruction. characteristics of Chapter 10 for details of tCY. See AC
15
PD75402A(A)
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit, which outputs clock pulses from pin P22/PCL, is used for supplying clock pulses for peripheral LSIs or for remote control output. * Clock output (PCL): 1.05 MHz, 524 kHz, 65.5 kHz (when fXX is 4.19 MHz).
Fig. 5-2 shows the configuration of the clock output circuit. Fig. 5-2 Configuration of the Clock Output Circuit
From the clock generator Output buffer Selector P22/PCL f XX /26
PORT2.2
CLOM3 0 CLOM1 CLOM0 CLOM
Bit 2 of PMGB
Port 2 input/ output mode specification bit
P22 output latch
4 Internal bus
Remark The clock output circuit is designed not to output high-frequency pulses when clock output is switched between the enable and disable states.
16
PD75402A(A)
5.4 BASIC INTERVAL TIMER
The basic interval timer provides the following functions: * Interval timer operation that generates a reference time interrupt * Can be used as a watchdog timer for detecting program crashes * Reading the count value Fig. 5-3 Configuration of the Basic Interval Timer
From the clock generator fXX /25 MPX fXX /29
Clear
Clear
Basic interval timer (8-bit frequency divider)
Set
BT interrupt request flag IRQBT
BT
Vectored interrupt request signal
BTM3
BTM2
1
1
BTM
4
8 Internal bus
17
PD75402A(A)
5.5 SERIAL INTERFACE
The serial interface has the following modes: * Three-wire serial I/O mode (MSB is transferred first.) * SBI mode (MSB is transferred first.) The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of peripheral I/O devices. The SBI mode enables communication with two or more devices.
18
Fig. 5-4 Block Diagram of the Serial Interface
Internal bus 8 CSIM Bit test 8 8 Slave address register (SVA) (8) Match signal (8) RELT CMDT Bit manipulation SBIC Bit test
Address comparator P03/SI Selector
Shift register (SIO)
ACKE
ACKT
P02 /SO/SB0 Busy/ acknowledge output circuit
Bus-release/ command/ acknowledge detector
RELD CMDD ACKD
BSYE
(8)
SET CLR SO Iatch D Q
P01/SCK
Serial clock counter
INTCSI control circuit
INTCSI IRQCSI Set signal fXX/2 MPX
4
Serial clock control circuit
PD75402A(A)
External SCK
19
PD75402A(A)
6. INTERRUPT FUNCTION
The PD75402A(A) has three interrupt sources and each of them has the interrupt vector table. The PD75402A(A) is also provided with one edge-sensitive testable input signal. When a vectored interrupt request is issued, the PC and PSW are saved in the stack, and the contents of the vector table which corresponds to the issued vectored interrupt are set in the PC as a start address. The program branches to the interrupt service routine. These operations are performed automatically by the hardware. The flag is set by detecting the edge of the testable input signal, but a vectored interrupt request is not issued. During execution of the interrupt service routine, the PD75402A(A) does not accept the other interrupt requests. Unlike the other 75X series, the PD75402A(A) cannot handle multiple interrupts. The interrupt control circuit of the PD75402A(A) has the following functions. * Vectored interrupt function under hardware control which can determine whether to accept an interrupt by an interrupt enable flag (IExxx) and an interrupt master enable flag (IME). * Any interrupt start address can be set. * Test function of an interrupt request flag (IRQxxx) (Software can confirm that an interrupt occurs.) * Release of the standby (HALT) mode (An interrupt to be released by an interrupt enable flag can be selected from interrupts other than INT0.)
20
Fig. 6-1 Block Diagram of Interrupt Control Circuit
3 IM0 Interrupt enable flag (IExxx) IME IST0
Decoder
INT BT INT0/ P10
Note 1
VRQ1 IRQBT VRQ2 IRQ0 VRQ3 Priority control circuit Vector table address generator
Edge detection circuit INTCSI
IRQCSI
INT2/ P12
Note 2
Rising edge detection circuit
IRQ2
PD75402A(A)
Notes 1. Noise eliminator using the sampling clock 2. Noise eliminator using analog delay
Standby release signal
21
PD75402A(A)
7. STANDBY FUNCTION
To reduce the power consumption when the program is in the wait state, the PD75402A(A) has two standby modes, STOP and HALT. Table 7-1 Operation Statuses in the Standby Mode
STOP mode Instruction to be used to set mode Operation status Clock generator STOP instruction HALT mode HALT instruction
Oscillation of the system clock stops.
Only the CPU clock () stops, but oscillation continues. Operates. (IRQBT is set at every reference time interval.) Operable
Basic interval timer Serial interface
Operation stops.
Operable only when the external SCK input is selected for the serial clock. Operation stops.
Clock output circuit External interrupt CPU Release signal
Clocks other than CPU clock () can be output. INT2 pin is usable. INT0 pin cannot be used.
INT2 pin is usable. INT0 pin cannot be used. Operation stops. RESET input
RESET input or interrupt request signals enabled by the interrupt enable flags
22
PD75402A(A)
8. RESET FUNCTION
When a low level signal is input to the RESET input pin, the state changes to the system reset. Table 8-1 shows the statuses of the hardware. When the RESET signal rises from the low level to the high level, the reset state is released. The three loworder bits of the reset vector table whose address is 000H is set in bits 10 to 8 of the program counter (PC) and the contents of the reset vector table whose address is 001H is set in bits 7 to 0 of the PC. The program branches to that address and starts execution, i.e., the reset start address is programmable. Initialize contents of registers in a program if necessary. The RESET pin connects to the Schmitt-trigger circuit whose threshold level has hysteresis in the chip. This pin is also connected to the noise eliminator using an analog delay to eliminate narrow noise and prevent errors caused by noise. (See Fig. 8-1.) For the power-on reset operation, be sure to allow sufficient time for oscillation to settle between power on and acceptance of the reset signal (see Fig. 8-2). Fig. 8-1 Acceptance of the Reset Signal
RESET
Analog delay Elimination as noise.
The instruction which is stored at the reset Content of the reset branch address is executed. Analog Analog vector table is set delay delay to the PC (the initialization of the PC). This low level The reset is signal is accepted released. as the reset signal.
Fig. 8-2 Power-On Reset Operation
VDD
RESET Oscillation settling time The instruction which is stored at the reset branch address is executed.
Analog delay
Content of the reset vector table is set to the PC (the initialization of the PC).
The reset is released.
23
PD75402A(A)
Table 8-1 Hardware Statuses after Reset Operations
Hardware Program counter (PC) RESET input in standby mode Set the three low-order bits of address 000H in program memory in PC bits 10 to 8 and set the contents of address 001H in PC bits 7 to 0. Retained 0 0 Undefined Retained Note Retained Undefined 0 Retained 0 0 Retained 0 RESET input during operations Set the three low-order bits of address 000H in program memory in PC bits 10 to 8 and set the contents of address 001H in PC bits 7 to 0. Undefined 0 0 Undefined Undefined Undefined Undefined 0 Undefined 0 0 Undefined 0
PSW
Carry flag (CY) Skip flag (SK0 - SK2) Interrupt status flag (IST0)
Stack pointer (SP) Data memory (RAM) General register (X, A, H, L) Basic interval timer Serial interface Counter (BT) Mode register (BTM) Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator and clock output circuit Processor clock control register (PCC) Clock output mode register (CLOM) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt master enable flag (IME) INT0 mode register (IM0) Digital I/O port Output buffer Output latch I/O mode register (PMGA, PMGB) Pull-up resistor specification register (POGA) States of pins P00 - P03, P10, P12, P20 - P23, P30 - P33, P60 - P63 P50 - P53 * *
0
0
Interrupt
Reset (0) 0 0
Reset (0) 0 0
0 Off Cleared (0) 0
0 Off Cleared (0) 0
0
0
Used as inputs
Used as inputs
High level when pull-up resistor is built in High impedance when open drain is used in the internal circuit
* *
High level when pull-up resistor is built in High impedance when open drain is used in the internal circuit
Note Data in the data memory whose addresses are 38H to 3DH is not defined when the standby mode is released by the RESET input signal.
24
PD75402A(A)
9. INSTRUCTION SET
(1) Representation format and description method of operands An operand is described in the operand field of each instruction according to the description method corresponding to the operand representation format of the instruction refer to "RA75X Assembler Package User's Manual, Language" (EEU-1363) for details. When two or more elements are described in the description method field, select one of them. Upper-case letters, a number sign (#), and at mark (@), an exclamation mark (!), and a dollar sign ($) are keywords, so they can be used without alteration. Specify an appropriate numeric value or label for immediate data. The symbols of registers and flags can be used as labels instead of mem, fmem, and bit (refer to the "PD75402A User's Manual" (IEU-644) for details). Some labels, however, cannot be specified in fmem.
Representation format reg reg1 rp n4 n8 mem bit fmem addr caddr faddr PORTn IExxx X, A, H, L X, H, L XA, HL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label Note 2-bit immediate data or label FB0H - FBFH/FF0H - FFFH immediate data or label 11-bit immediate data or label 11-bit immediate data or label 11-bit immediate data or label PORT0 - PORT3, PORT5, PORT6 IEBT, IECSI, IE0, IE2 Description method
Note Only an even address can be written in mem when 8-bit data is processed. (2) Legend A H L X XA HL PC SP CY PSW IME PCC * (xx) xxH : A register, 4-bit accumulator : H register : L register : X register : Register pair (XA), 8-bit accumulator : Register pair (HL) : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Interrupt master enable flag : Processor clock control register : Address/bit delimiter : Contents addressed by xx : Hexadecimal data
PORTn: Port n (n = 0 to 3, 5, 6) IExxx : Interrupt enable flag
25
PD75402A(A)
(3) Explanation of the symbols in the addressing area field
*1 *2 *3 *4 *5 *6 *7
MB = 0 MB = 0 (00H - 3FH) MB = 15 (80H - FFH) MB = 15, fmem = FB0H - FBFH or FF0H - FFFH addr = 000H - 77FH addr = (Current PC) - 15 to (Current PC) - 1 or (Current PC) + 16 to (Current PC) + 2 caddr = 000H - 77FH faddr = 000H - 77FH Program memory addressing Data memory addressing
Remarks 1. MB indicates an accessible memory bank. 2. *4 to *7 indicate each addressable area. (4) Explanation of the machine cycle field S indicates the number of machine cycles required for a skip instruction to perform skipping. The following shows the values of S. * When the next instruction is not skipped, S is 0. * When the next instruction is skipped, S is 1. A machine cycle is equal to one cycle (= tCY) of CPU clock . A PCC setting determines the machine cycle. It can be set to one of three different periods.
26
PD75402A(A)
Instruction group Transfer instruction Number of bytes 1 2 2 1 1 2 2 2 2 1 2 2 1 1 1 1 1 1 1 1 1 Machine cycle 1 2 2 1 1 2 2 2 2 1 2 2 1 3 1+S 1+S 1 1 1 1 1 A n4 XA n8 HL n8 A (HL) (HL) A A (mem) XA (mem) (mem) A (mem) XA A (HL) A (mem) XA (mem) A reg1 XA (PC10-8 + XA)ROM A A + n4 A A + (HL) A, CY A + (HL) + CY *1 *1 *1 *1 *1 carry carry *1 *1 *2 *2 *2 *2 *1 *2 *2
Mnemonic MOV
Operand
Operation
Addressing area
Skip condition String A String A String B
A, #n4 XA, #n8 HL, #n8 A, @HL @HL, A A, mem XA, mem mem, A mem, XA
XCH
A, @HL A, mem XA, mem A, reg1
MOVT Arithmetic/ logical instruction ADDS
XA, @PCXA A, #n4 A, @HL
ADDC AND OR XOR
A, @HL A, @HL A, @HL A, @HL A
(HL) A A (HL) A A (HL)
AA CY A0, A3 CY, An-1 An
Accumulator manipulation instruction Increment/ decrement instruction Comparison instruction Carry flag manipulation instruction
RORC
NOT
A
2
2
AA
INCS
reg mem
1 2 1 2 1 1 1 1 1
1+S 2+S 1+S 2+S 1+S 1 1 1+S 1
reg reg + 1 (mem) (mem) + 1 reg reg - 1 Skip if reg = n4 Skip if A = (HL) CY 1 CY 0 Skip if CY = 1 CY CY *1 *2
reg = 0 (mem) = 0 reg = FH reg = n4 A = (HL)
DECS SKE
reg reg, #n4 A, @HL
SET1 CLR1 SKT NOT1
CY CY CY CY
CY = 1
27
PD75402A(A)
Instruction group Memory bit manipulation instruction Number of bytes 2 2 2 2 2 2 2 2 2 2 2 2 - Machine cycle 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2 2 2 - Addressing area *2 *3 *2 *3 *2 *3 *2 *3 *3 *3 *3 *3 *4 (mem.bit) = 1 (fmem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (fmem.bit) = 1 Skip condition
Mnemonic SET1
Operand
Operation (mem.bit) 1 (fmem.bit) 1 (mem.bit) 0 (fmem.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (fmem.bit) = 1 and clear
mem.bit fmem.bit
CLR1
mem.bit fmem.bit
SKT
mem.bit fmem.bit
SKF
mem.bit fmem.bit
SKTCLR AND1 OR1 XOR1 Branch instruction BR
fmem.bit CY, fmem.bit CY, fmem.bit CY, fmem.bit addr
(fmem.bit) CY CY (fmem.bit) CY CY (fmem.bit)
CY CY PC10-0 addr (The assembler selects an appropriate instruction from the BRCB !caddr and BR $addr instructions.) PC10-0 addr PC10-0 caddr (SP - 4)(SP - 1)(SP - 2) 0, PC10-0 (SP - 3) 0000 PC10-0 faddr, SP SP - 4 x, PC10-0 (SP)(SP + 3)(SP + 2) SP SP + 4 x, PC10-0 (SP)(SP + 3)(SP + 2) SP SP + 4, then skip unconditionally x, PC10-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6 (SP - 1)(SP - 2) rp, SP SP - 2 rp (SP + 1)(SP), SP SP + 2 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn PORT n A (n = 0 - 3, 5, 6) (n = 2, 3, 5, 6)
$addr BRCB Subroutine stack control instruction CALLF !caddr !faddr
1 2 2
2 2 2
*5 *6 *7
RET
1
3
RETS
1
3+S
Unconditionally
RETI
1
3
PUSH POP Interrupt control instruction EI
rp rp
1 1 2
1 1 2 2 2 2 2 2 2 2 1
IExxx DI IExxx
2 2 2 2 2 2 2 1
Input/ output instruction CPU control instruction
IN OUT HALT STOP NOP
A, PORTn PORTn, A
Set HALT mode (PCC.2 1) Set STOP mode (PCC.3 1) No operation
28
PD75402A(A)
10. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Ports other than port 5 Port 5 Built-in pull-up resistor Open drain Output voltage High-level output current Low-level output current VO IOH Each pin Total of all output pins IOL
Note
Conditions
Rated value -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11.0 -0.3 to VDD + 0.3 -15 -30 Peak value rms 30 15 20 10 100 60 100 60 -40 to +85
Unit V V V V V mA mA mA mA mA mA mA mA mA mA C
One pin of port 0, 3, 5, or 6
One pin of port 2
Peak value rms
Total of all pins of ports 0, 3, and 5 (excl. P33) Total of all pins of ports 2, 6, and P33 Operating temperature Storage temperature Topt
Peak value rms Peak value rms
Tstg
-65 to +150
C
Note Calculate rms with [rms] = [peak value] x duty. Caution Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values.
29
PD75402A(A)
CHARACTERISTICS OF THE OSCILLATION CIRCUIT (Ta = -40 to +85 C, V DD = 2.7 to 6.0 V)
Resonator Ceramic resonator Recommended constant Parameter Oscillator frequency (fXX) Note 1
C2
Conditions VDD = oscillation voltage range
Min. 2.0
Typ.
Max. 5.0 Note 3
Unit MHz
X1
X2
C1
Oscillation settling time
Note 2
After VDD reaches MIN. of the oscillation voltage range 2.0 4.19
4
ms
Crystal
X1
X2
Oscillator frequency (fXX) Note 1
5.0 Note 3
MHz
C1
C2
Oscillation settling time
Note 2
VDD = 4.5 to 6.0 V
10
ms
External clock
X1
X2
X1 input frequency (fX) Note 1 X1 input high/low level width (tXH, tXL)
2.0
5.0 Note 3
MHz
100
250
ns
PD74HCU04
Notes 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied or after the STOP mode is released. 3. When 4.19 MHz < fX 5.0 MHz, do not select PCC = 0011 as the instruction execution time. When PCC = 0011, one machine cycle falls short of 0.95 s, the minimum value for the standard. 5 Caution When the clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. * Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VSS. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator. CAPACITANCE (Ta = 25 C, V
Parameter Input capacitance Output capacitance I/O capacitance
DD
= 0 V)
Conditions f = 1 MHz 0 V for pins other than pins to be measured Min. Typ. Max. 15 15 15 Unit pF pF pF
Symbol CIN COUT CIO
30
PD75402A(A)
DC CHARACTERISTICS (Ta = -40 to +85 C, V DD = 2.7 to 6.0 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 Conditions Ports 2, 3, and 6 Ports 0 and 1, and RESET Port 5 Built-in pull-up resistor Open drain VIH4 Low-level input voltage VIL1 VIL2 VIL3 High-level output voltage Low-level output voltage VOH X1 and X2 Ports 2, 3, 5, and 6 Ports 0 and 1, and RESET X1 and X2 Ports 0, 2, 3, and 6 Ports 3, 5, and 6 Ports 0, 2, 3, 5, and 6 SB0 (Open drain) High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current High-level output leakage current Low-level output leakage current Built-in pull-up resistor ILIL1 ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 10 V VOUT = 0 V VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VIN = 10 V VIN = 0 V VIN = VDD VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A VDD = 4.5 to 6.0 V, IOL = 15 mA Min. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD - 0.5 0 0 0 VDD - 1.0 VDD - 0.5 0.6 2.0 Typ. Max. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V
VOL
VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A Pull-up resistor : 1 k or more VDD = 4.5 to 6.0 V Other than X1 and X2 X1 and X2 Port 5 (open drain) Other than X1 and X2 X1 and X2 Other than port 5 Port 5 (open drain)
0.4 0.5 0.2VDD
V V V
3 20 20 -3 - 20 3 20 -3
A A A A A A A A
k k k k mA mA
RL1
Ports 0, 1, 2, 3, and 6 (excl. P00 and P10) VIN = 0 V Port 5 VOUT = VDD - 2.0 V 4.19 MHz crystal resonance C1 = C2 = 22 pF STOP mode
15 30 15 10
40
80 300
RL2
40
70 60
Power supply current Note 1
IDD1
VDD = 5.0 V 10 % Note 2 VDD = 3.0 V 10 % Note 3 HALT mode VDD = 5.0 V 10 % VDD = 3.0 V 10 %
2.5 0.5 500 150 0.5 0.1
8 1.5 1500 450 20 10 5
IDD2
A A A A A
IDD3
VDD = 5.0 V 10 % VDD = 3.0 V 10 %
Ta = 25 C
0.1
Notes 1. This current excludes the current which flows through the built-in pull-up resistors. 2. Value when the processor clock control resistor (PCC) is set to 0011 and the PD75402A(A) is operated in the high-speed mode 3. Value when the PCC is set to 0000 and the PD75402A(A) is operated in the low-speed mode
31
PD75402A(A)
AC CHARACTERISTICS (Ta = -40 to +85 C, V DD = 2.7 to 6.0 V, VSS = 0 V)
Parameter CPU clock cycle time Note 1 (minimum instruction execution time = one machine cycle) Interrupt input high/low level width RESET low-level width Symbol tCY Conditions VDD = 4.5 to 6.0 V Min. 0.95 3.8 tINTH, tINTL INT0 INT2 tRSL
Note 2
Typ.
Max. 32 32
Unit
s s s s s
10 10
tCY vs. VDD
Notes 1. The cycle time of the CPU clock () (minimum instruction execution time) depends on the connected resonator frequency and the setting of the processor clock control register (PCC). The figure on the right side shows the cycle time tCY characteristics for the supply voltage VDD. 2. This value is 2tCY or 128/fXX according to the setting of the interrupt mode register (IM0).
Cycle time tCY [ s]
40 32 7 6 5 4 3 Guaranteed operating range
2
1
0.5 0 1 2 3 4 5 6 Supply voltage VDD [V]
32
PD75402A(A)
Serial transfer operation Three-wire serial I/O mode (SCK *** Internal clock output):
Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 4.5 to 6.0 V Min. 1600 3800 SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) Delay from SCK to SO output tKL1 tKH1 tSIK1 VDD = 4.5 to 6.0 V tKCY1/2 - 50 tKCY1/2 - 150 150 Typ. Max. Unit ns ns ns ns ns
tKSI1
400
ns
tKSO1
RL = 1 k, CL = 100 pF Note
VDD = 4.5 to 6.0 V
0 0
250 1000
ns ns
Note RL and CL are the resistance and capacitance of the SO output line load respectively. Three-wire serial I/O mode (SCK *** External clock input):
Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 4.5 to 6.0 V Min. 800 3200 SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) Delay from SCK to SO output tKL2 tKH2 tSIK2 VDD = 4.5 to 6.0 V 400 1600 100 Typ. Max. Unit ns ns ns ns ns
tKSI2
400
ns
tKSO2
RL = 1 k, CL = 100 pF Note
VDD = 4.5 to 6.0 V
0 0
300 1000
ns ns
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
33
PD75402A(A)
SBI mode (SCK *** Internal clock output (master)):
Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V Min. 1600 3800 SCK high/low level width SB0 setup time (referred to SCK) SB0 hold time (referred to SCK) Delay from SCK to SB0 output
Delay from SCK to SB0
Typ.
Max.
Unit ns ns ns ns ns
tKL3 tKH3 tSIK3
VDD = 4.5 to 6.0 V
tKCY3/2 - 50 tKCY3/2 - 150 150
tKSI3
tKCY3/2
ns
tKSO3
VDD = 4.5 to 6.0 V
0 0
250 1000
ns ns ns ns ns ns
tKSB tSBK tSBL tSBH
tKCY3 tKCY3 tKCY3 tKCY3
Delay from SB0 to SCK SB0 low-level width SB0 high-level width
SBI mode (SCK *** External clock input (slave)):
Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 4.5 to 6.0 V Min. 800 3200 SCK high/low level width SB0 setup time (referred to SCK) SB0 hold time (referred to SCK) Delay from SCK to SB0 output
Delay from SCK to SB0 Delay from SB0 to SCK
Typ.
Max.
Unit ns ns ns ns ns
tKL4 tKH4 tSIK4
VDD = 4.5 to 6.0 V
400 1600 100
tKSI4
tKCY4/2
ns
tKSO4
RL = 1 k, CL = 100 pF Note
VDD = 4.5 to 6.0 V
0 0 tKCY4 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns ns
tKSB tSBK tSBL tSBH
SB0 low-level width SB0 high-level width
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
34
PD75402A(A)
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD 0.2VDD
Measurement point
0.8VDD 0.2VDD
Clock Timing
1/fX tXL tXH
VDD - 0.5 V X1 input 0.4 V
Serial Transfer Timing Three-wire serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
35
PD75402A(A)
Serial Transfer Timing Bus release signal transfer:
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tSIK3, 4 tKSB tSBL tSBH tSBK tKSI3, 4
SB0
tKSO3, 4
Command signal transfer:
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tSIK3, 4 tKSB tSBK tKSI3, 4
SB0
tKSO3, 4
Interrupt Input Timing
tINTL
tINTH
INT0, INT2
RESET Input Timing
tRSL
RESET
36
PD75402A(A)
DATA HOLD CHARACTERISTICS AT LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (Ta = -40 to +85 C)
Parameter Data hold supply voltage Data hold supply current RESET setup time Oscillation settling time Symbol VDDDR Conditions Min. 2.0 Typ. Max. 6.0 Unit V
IDDDR
VDDDR = 2.0 V
0.1
10
A s
tSRS tOS After VDD reaches the oscillation voltage range when the ceramic resonator is connected After VDD reaches the oscillation voltage range when the crystal is connected
0 4
ms
10
ms
Data Hold Timing (STOP Mode Release by RESET)
HALT mode STOP mode Data hold mode Operating mode
VDD
VDDDR STOP instruction execution
tSRS
RESET tOS
37
PD75402A(A)
11. PACKAGE DIMENSIONS
28 PIN PLASTIC DIP (600 mil)
28 15
1 A
14
K L
J
I
G
H
F D N
M
C
B
M
R
NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R MILLIMETERS 38.10 MAX. 2.54 MAX. 2.54 (T.P.) 0.500.10 1.2 MIN. 3.60.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.25 0` 15 INCHES 1.500 MAX. 0.100 MAX. 0.100 (T.P.) +0.004 0.020 -0.005 0.047 MIN. 0.1420.012 0.020 MIN. 0.170 MAX. 0.226 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.01 0` 15 P28C-100-600A1-1
38
PD75402A(A)
28PIN PLASTIC SHRINK DIP (400 mil)
28 15
1
A I
14
K L
J
H G
F D N
M
C B
M
R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 28.46 MAX. 2.67 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 10.16 (T.P.) 8.6 0.25 +0.10 -0.05 0.17 0~15
INCHES 1.121 MAX. 0.106 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.400 (T.P.) 0.339 0.010 +0.004 -0.003 0.007 0~15 P28C-70-400A-1
39
PD75402A(A)
44 PIN PLASTIC QFP ( 10)
A B
33 34
23 22
detail of lead end
C
D
S Q R
44 1
12 11
F G H P
N
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
J I
M
K M L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 13.60.4 10.00.2 10.00.2 13.60.4 1.0 1.0 0.350.10 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.535 +0.017 -0.016 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.535 +0.017 -0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. P44GB-80-3B4-3
40
PD75402A(A)
PACKAGE DIMENSIONS OF THE 44-PIN CERAMIC QFP FOR ES (REF. DWG.) (UNIT: MM)
11.43 8.0
44 1
34 33
11 12 22
23
11.43 0.15
0.8
0.32
(Bottom)
Cautions 1. Find the location of pin 1 by checking the location of pin 17, which is connected to the metal cap. 2. The metal cap is connected to pin 17. The electrical level of the metal cap is VSS (GND). 3. The lead length has not been specified because leads are cut without any detailed specifications.
2.25
8.0
41
PD75402A(A)
12. RECOMMENDED SOLDERING CONDITIONS
The following conditions shall be met when soldering the PD75402A(A). For details of the recommended soldering conditions, refer to our document "SMD Surface Mount Technology Manual" (IEI-1207). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Table 12-1 Soldering Conditions for Surface-Mount Devices
PD75402AGB(A)-xxx-3B4: 44-pin plastic QFP (10 x 10 mm)
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 230 C Reflow time: 30 seconds or less (210 C or more) Number of reflow processes: 1 Peak package's surface temperature: 215 C Reflow time: 40 seconds or less (200 C or more) Number of reflow processes: 1 Solder temperature: 260 C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature: 120 C max. (measured on the package surface) Terminal temperature: 300 C or less Flow time: 3 seconds or less (for each side of device) Symbol IR30-00-1
VPS
VP15-00-1
Wave soldering
WS60-00-1
Partial heating method
--
Caution Do not apply more than a single process at once, except for "Partial heating method." Table 12-2 Soldering Conditions for Insertion-Mount Devices
PD75402AC(A)-xxx: 28-pin plastic DIP (600 mil) PD75402ACT(A)-xxx: 28-pin plastic shrink DIP (400 mil)
Soldering process Wave soldering (Only for leads) Partial heating method Soldering conditions Solder temperature: 260 C or less Flow time: 10 seconds or less Terminal temperature: 260 C or less Flow time: 10 seconds or less
Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does not come in contact with the main body of the package. Notice Other versions of the products are available. For these versions, the recommended reflow soldering conditions have been mitigated as follows: Higher peak temperature (235 C), two-stage, and longer exposure limit. Contact an NEC representative for details.
42
PD75402A(A)
APPENDIX A DIFFERENCES BETWEEN THE PD75402A(A) AND PD75P402
Product Item ROM I/O ports Input I/O N-ch I/O VPP, PROM programming pin Electrical characteristics Operating supply voltage Operating temperature Quality grade Special Standard 22 6 12
PD75402A(A)
Masked ROM
PD75P402
One-time PROM
16 (Pull-up resistors can be connected by software.) 4 (No pull-up resistors can be connected.)
4 (Pull-up resistors can be connected by mask option.) Not provided
Provided 5 V 10 %
2.7 to 6.0 V
-40 to +85 C
-10 to +70 C
43
PD75402A(A)
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for developing systems including the PD75402A(A)
IE-75000-RNote 1 IE-75001-R IE-75000-R-EMNote 2 Hardware EP-75402C-R EP-75402GB-R EV-9200G-44 PG-1500 PA-75P402CT
In-circuit emulator for the 75X series
Emulation board for the IE-75000-R and IE-75001-R Emulation probe for the PD75402AC(A) and PD75402ACT(A) Emulation probe for the PD75402AGB(A). A 44-pin conversion socket, the EV-9200G-44, is attached to the probe. PROM programmer PROM programmer adapter for the PD75P402C and PD75P402CT. Connected to the PG-1500. PROM programmer adapter for the PD75P402GB. Connected to the PG-1500. Host machine * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3) * IBM PC/AT TM (PC DOSTM Ver. 3.1)
PA-75P402GB IE control program Software PG-1500 controller RA75X relocatable assembler
Notes 1. Maintenance service only 2. Not contained in the IE-75001-R 3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A. Remark Refer to "75X Series Selection Guide" (IF-1027) for development tools manufactured by third parties.
44
PD75402A(A)
APPENDIX C RELATED DOCUMENTS
5
Documents related to the device
Document name User's manual Application note 75X series selection guide Document No. IEU-644 IEA-638 IF-1027
Documents related to development tools
Document name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75402C-R User's Manual EP-75402GB-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual
Document No. EEU-1416 EEU-1294 EEU-701 EEU-702 EEU-1335 EEU-1346 EEU-1363 EEU-1291
Other related documents
Document name Package Manual SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Document No. IEI-1213 IEI-1207 IEI-1209 IEI-1203 IEI-1201 MEI-1202
Caution The above documents may be revised without notice. Use the latest versions when you design an application system.
45
PD75402A(A)
Cautions on CMOS Devices
1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. 2 CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate-level input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. 3 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first.
46
PD75402A(A)
[MEMO]
47
PD75402A(A)
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92. 6
MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.

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