 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SL4013B Dual D Flip-Flop High-Voltage Silicon-Gate CMOS The SL4013B consists of two identical, independent data-type flipflops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply ORDERING INFORMATION SL4013BN Plastic SL4013BD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM 2.5 V min @ 15.0 V supply FUNCTION TABLE Inputs Clock Data Reset Set L H X X PIN 14 =VCC PIN 7 = GND X X X X X L L L H L H L L L L H H Outputs Q L H Q L H H Q H L Q H L H X = don't care SLS System Logic Semiconductor SL4013B MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260 Unit V V V mA mW mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL4013B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 1 2 4 20 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 1 2 4 20 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 30 60 120 600 0.36 0.9 2.4 Ma -1.15 -0.36 -0.9 -2.4 Unit V VIL V VOH V VOL VIN=GND or VCC V IIN ICC VIN= GND or VCC VIN= GND or VCC A A IOL VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V Ma IOH Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V SLS System Logic Semiconductor SL4013B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200 k, Input t r=t f=20 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55C 3.5 8 12 300 130 90 300 130 90 400 170 120 200 100 80 25C 3.5 8 12 300 130 90 300 130 90 400 170 120 200 100 80 7.5 125C 1.75 4 6 600 260 180 600 260 180 800 340 240 400 200 160 Unit MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q (Figure 1) Maximum Propagation Delay, Set to Q or Reset to Q (Figure 2) Maximum Propagation Delay, Set to Q or Reset to Q (Figure 2) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance ns tPLH ns tPHL ns tTLH, tTHL ns CIN pF TIMING REQUIREMENTS(CL=50pF, RL=200 k, Input t r=t f=20 ns) VCC Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55C 140 60 40 180 80 50 40 20 15 5 5 5 500 30 6 25C 140 60 40 180 80 50 40 20 15 5 5 5 500 30 6 125C 280 120 80 360 160 100 80 40 30 10 10 10 1000 60 12 Unit ns tw Minimum Pulse Width, Set or Reset (Figure 2) ns tsu Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Maximum Input Rise or Fall Time, Clock (Figure 1) ns th ns tr, tf s SLS System Logic Semiconductor SL4013B Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/2 of the Device) SLS System Logic Semiconductor |
Price & Availability of SL4013B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |