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CALIFORNIA MICRO DEVICES
PAC DN017
Applications Parallel printer port protection ESD protection for sensitive electronic equipment.
18 CHANNEL ESD PROTECTION ARRAY WITH ZENER SUPPLY CLAMP
Features 18-channel ESD protection Integral Zener diode clamp to suppress supply rail transients 15KV ESD protection (HBM) 15KV contact discharge ESD protection per IEC 61000-4-2 Low loading capacitance, 7 pF typ. 24-pin QSOP package
Product Description The PAC DN017 is a diode array designed to provide 18 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (VP) or negative (VN) supply. In addition, there is an integral Zener diode between VP and VN to supress any voltage disturbance due to these ESD pulses. The PAC DN017 will protect against ESD pulses up to 15 KV Human Body Model, and 15KV contact discharge per International Standard IEC 61000-4-2. This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low loading capacitance for all signal lines. ABSOLUTE MAXIMUM RATINGS SCHEMATIC CONFIGURATION
Diode Forward DC Current (Note 1) 40mA Storage Temperature -65C to 150C Operating Temperature Range -20C to 85C DC Voltage at any Channel Input VN-0.5V to VP+0.5V
Note 1: Only one diode conducting at a time.
STANDARD SPECIFICATIONS Parameter Min. Operating Supply Voltage ( V P - V N ) Supply Current @ V P -V N = 5.5V 0.65 V D iode Forward Voltage, I F = 20mA, T = 25C Zener clamp reverse breakdown voltage @1mA, T = 25C ESD Protection Peak D ischarge Voltage at any Channel Input, in-system (Note 2) 000Human Body Model, Method 3015 (Note 3, 4) 15 KV 15 KV 000Contact D ischarge per IEC 61000-4-2 (Note 5) Channel Clamp Voltage @ 15KV ESD HBM, T = 25C 000Positive transients 000Negative transients Channel Leakage Current, T = 25C Channel Input Capacitance (Measured @ 1 MHz) VP = 5V, VN = 0V, V IN = 2 .5 V (Note 4) Package Power Rating
Note 2: Note 3: Note 4: Note 5:
Typ.
6.6V
Max. 5.5 V 20 A 0.95 V
(Notes 3, 4)
0.1 A 7pF
V P + 13.0 V V N - 13.0 V 1.0 A 12pF 1.0W
From I/O pins to VP or VN only. Bypass opacitor between VP and VN is not required. However, a 0.2 F ceramic chip capacitor bypassing VP to VN is recommended if the lowest possible channel clamp voltage is desired. Human Body Model per MIL-STD-883, Method 3015, CDischarge=100pF, RDischarge=1.5K, VP=5.0V, VN=GND. This parameter is guaranteed by characterization. Standard IEC 61000-4-2 with CDischarge=150pF, and RDischarge=330, VP=5V, VN=GND.
C0631199
(c)1999 California Micro Devices Corp. All rights reserved. P/Active(R) is a registered trademark and PAC is a trademark of California Micro Devices. 11/98
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
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CALIFORNIA MICRO DEVICES
Input Capacitance vs. Input Voltage
PAC DN017
CIN (pF)
VIN Typical variation of CIN with VIN (VP = 5V, VN = 0V, 0.1F chip capacitor between VP & VN)
STANDARD PART ORDE RING INFORMATION Package Ordering Part Number Style Part Marking
QSOP PACD N017Q
Pins
24
When placing an order please specify desired shipping: Tubes or Tape & Reel. Application Information See also California Micro Devices Application note AP209, Design Considerations for ESD protection. In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is represented by L1. The voltage VZ on the line being protected is: VZ = Forward voltage drop of D1 + L1 x d(Iesd)/dt + VSupply where Iesd is the ESD current pulse, and VSupply is the positive supply voltage.
Figure 1 An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(Iesd)/dt can be approximated by Iesd/t, or 30/(1x10-9). So just 10nH of series inductance (L1) will lead to a 300V increment in VZ!
(c) 1999 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
11/98
CALIFORNIA MICRO DEVICES
PAC DN017
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VZ equation above, the VSupply term, in reality, is given by (VDC + Iesd x Rout), where VDC and Rout are the nominal supply DC output voltage and effective output impedance of the power supply respectively. As an example, a Rout of 1 ohm would result in a 10V increment in VZ for a peak Iesd of 10A. To mitigate these effects, a Zener diode has been integrated into this Protection Array between VP and VN. This Zener diode clamps the maximum voltage of VP relative to VN at the breakdown voltage of the Zener diode. Although not strictly necessary, it is recommended that VP be bypassed to the ground plane with a high frequency bypass capacitor. This will lower the channel clamp voltage, and is especially effective when VP is much lower than the Zener breakdown voltage. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in VP. Typically a value in the 0.1 F to 0.2 F range is adequate for IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
(c)1999 California Micro Devices Corp. All rights reserved. 11/98
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
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