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| Order this document from Analog Marketing High Speed 8-Bit Analog-to-Digital Converter The MC10319 is an 8-bit high speed parallel flash A/D converter. The device employs an internal Grey Code structure to eliminate large output errors on fast slewing input signals. It is fully TTL compatible, requiring a + 5.0 V supply and a wide tolerance negative supply of - 3.0 to - 6.0 V. Three-state TTL outputs allow direct drive of a data bus or common I/O memory. The MC10319 contains 256 parallel comparators across a precision input reference network. The comparator outputs are fed to latches and then to an encoder network, to produce an 8-bit data byte plus an overrange bit. The data is latched and converted to 3-state LS-TTL outputs. The overrange bit is always active to allow for either sensing of the overrange condition or ease of interconnecting a pair of devices to produce a 9-bit A/D converter. Applications include video display and radar processing, high speed instrumentation and TV broadcast encoding. * Internal Grey Code for Speed and Accuracy, Binary Outputs MC10319 HIGH SPEED 8-BIT ANALOG-TO-DIGITAL FLASH CONVERTER SEMICONDUCTOR TECHNICAL DATA P SUFFIX PLASTIC PACKAGE CASE 709 * * * * * * * * * 8-Bit Resolution/9-Bit Typical Accuracy Easily Interconnected for 9-Bit Conversion 3-State LS-TTL Outputs with True/Complement Enable Inputs 25 MHz Sampling Rate Wide Input Range: 1.0 to 2.0 Vpp, between 2.0 V Low Input Capacitance: 50 pF Low Power Dissipation: 618 mW No Sample/Hold Required for Video Bandwidth Signals Single Clock Cycle Conversion VRM 1 GND 2 OVER- 3 RANGE D7 4 DW SUFFIX PLASTIC PACKAGE CASE 751F (SO-28L) PIN CONNECTIONS (P only) 24 VRT 23 VRB 22 GND 21 D0 20 EN 19 EN 18 CLOCK 17 VCC(D) 16 GND 15 VCC(A) 14 VIN 13 VEE Representative Block Diagram Analog Input Vin (14) VRT (24) Logic VCC(A) (15) Bias VEE (13) MC10319 VCC(D) (11, 17) Bias Over- Range (3) D7 (4) Output Latches and ECL-TTL Converters D6 (5) D5 (6) D4 (7) D3 (8) D2 (9) D1 (10) D0 (21) VRB (23) Clock (18) (19) Enable (20) Enable GND (2, 12, 16, 22) D6 5 D5 6 D4 7 D3 8 D2 9 D1 10 VCC(D) 11 GND 12 VRM (1) 256 Comparators Differential Latch Array Grey Code Translator ORDERING INFORMATION Device MC10319DW MC10319P (c) Motorola, Inc. 1996 Operating Temperature Range TA = 0 to +70C Package SO-28L Plastic Rev 0 MOTOROLA ANALOG IC DEVICE DATA 1 MC10319 ABSOLUTE MAXIMUM RATINGS Rating Supply Voltage Positive Supply Voltage Differential Digital Input Voltage (Pins 18 to 20) Analog Input Voltage (Pins 1, 14, 23, 24) Reference Voltage Span (Pin 24 to Pin 23) Applied Output Voltage (Pins 4 to 10, 21 in 3-State) Junction Temperature Storage Temperature Symbol VCC(A),(D) VEE VCC(D)- VCC(A) VI(D) VI(A) - - TJ Tstg Value + 7.0 - 7.0 - 0.3 to + 0.3 - 0.5 to + 7.0 - 2.5 to + 2.5 2.3 - 0.3 to + 7.0 + 150 - 65 to + 150 Unit Vdc Vdc Vdc Vdc Vdc Vdc C C Devices should not be operated at these values. The "Recommended Operating Limits" table provides guidelines for actual device operation. RECOMMENDED OPERATING LIMITS Characteristic Power Supply Voltage (Pin 15) Power Supply Voltage (Pins 11, 17) VCC(D) - VCC(A) Power Supply Voltage (Pin 13) Digital Input Voltages (Pins 18 to 20) Analog Input (Pin 14) Voltage @ VRT (Pin 24) Voltage @ VRB (Pin 23) VRT - VRB VRB - VEE Applied Output Voltage (Pins 4 to 10, 21 in 3-State) Clock Pulse Width - High Clock Pulse Width - Low Clock Frequency Operating Ambient Temperature Symbol VCC(A) VCC(D) VCC VEE VI(D) VI(A) VRT VRB VR - Vo tCKH tCKL fCLK TA Min + 4.5 - 0.1 - 6.0 0 - 2.1 - 1.0 - 2.1 + 1.0 1.3 0 5.0 15 0 0 Typ + 5.0 0 - 5.0 - - - - - - - 20 20 - - Max + 5.5 + 0.1 - 3.0 + 5.0 + 2.1 + 2.1 + 1.0 + 2.1 - 5.5 - - 25 + 70 Unit Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc ns MHz C ELECTRICAL CHARACTERISTICS (0 Characteristic t TA t 70C, VCC = 5.0 V, VEE = - 5.2 V, VRT = +1.0 V, VRB = - 1.0 V, unless noted.) Symbol Min Typ Max Unit N MON INL DNL DP DG PSRR - - 0.1 0 - - - - - - - - Guaranteed 1/4 - 1 1 1.0 1.0 - - 8.0 Bits Bits LSB LSB Deg. % LSB/V TRANSFER CHARACTERISTICS (fCKL = 25 MHz) Resolution Monotonicity Integral Nonlinearity Differential Nonlinearity Differential Phase (See Figure 16) Differential Gain (See Figure 16) Power Supply Rejection Ratio (4.5 V VCC 5.5 V, VEE = - 5.2 V) (- 6.0 V VEE - 3.0 V, VCC = + 5.0 V) tt tt 2 MOTOROLA ANALOG IC DEVICE DATA MC10319 ELECTRICAL CHARACTERISTICS - continued (0 t TA t 70C, VCC = 5.0 V, VEE = - 5.2 V, VRT = +1.0 V, VRB = - 1.0 V, unless otherwise noted.) Symbol Min Typ Max Unit A A pF pF LSB Characteristic ANALOG INPUTS (Pin 14) Input Current @ Vin = VRB (See Figure 5) Input Current @ Vin = VRT (See Figure 5) Input Capacitance (VRT - VRB = 2.0 V, See Figure 4) Input Capacitance (VRT - VRB = 1.0 V, See Figure 4) Bipolar Offset Error REFERENCE Ladder Resistance (VRT to VRB, TA = 25C) Temperature Coefficient Ladder Capacitance (Pin 1 open) ENABLE INPUTS (VCC = 5.5 V) (See Figure 6) Input Voltage - High (Pins 19 to 20) Input Voltage - Low (Pins 19 to 20) Input Current @ 2.7 V Input Current @ 0.4 V @ EN (0 IINL IINH Cin Cin VOS - 100 - - - - 0 60 36 55 0.1 - 150 - - - Rref TC Cref 104 - - 130 + 0.29 25 156 - - %/C pF VIHE VILE IIHE IIL1 IIL2 IIL3 VIKE 2.0 - - - 400 - 400 - 20 - 1.5 - - 0 - 100 - 100 - 2.0 - 1.3 - 0.8 20 - - - - V V A A A A V t EN t 5.0 V) Input Current @ 0.4 V @ EN (EN = 0 V) Input Current @ 0.4 V @ EN (EN = 2.0 V) Input Clamp Voltage (IIK = - 18 mA) CLOCK INPUTS (VCC = 5.5 V) Input Voltage High Input Voltage Low Input Current @ 0.4 V (See Figure 7) Input Current @ 2.7 V (See Figure 7) Input Clamp Voltage (IIK = - 18 mA) DIGITAL OUTPUTS High Output Voltage (IOH = - 400 A, VCC = 4.5 V, See Figure 8) Low Output Voltage (IOL = 4.0 mA, See Figure 9) Output Short Circuit Current* (VCC = 5.5 V) Output Leakage Current (0.4 VO 2.4 V, See Figure 3, VCC = 5.5 V, D0 to D7 in 3-State Mode) Output Capacitance (D0 to D7 in 3-State Mode) *Only one output is to be shorted at a time, not to exceed 1 second. VIHC VILC IILC IIHC VIKC 2.0 - - 400 - 100 - 1.5 - - - 80 - 20 - 1.3 - 0.8 - - - Vdc Vdc A A Vdc VOH VOL ISC ILK 2.4 - - - 50 3.0 0.35 35 - 9.0 - 0.4 - + 50 - V V mA A tt Cout - pF POWER SUPPLIES VCC(A) Current (4.5 V t VCC(A) t 5.5 V) (Outputs unloaded) t VCC(D) t 5.5 V) (Outputs unloaded) VEE Current (- 6.0 t VEE t - 3.0 V) VCC(D) Current (4.5 V Power Dissipation (VRT - VRB = 2.0 V) (Outputs unloaded) ICC(A) ICC(D) IEE PD 10 50 - 14 - 17 90 - 10 618 25 133 - 6.0 995 mA mA mA mW MOTOROLA ANALOG IC DEVICE DATA 3 MC10319 TIMING CHARACTERISTICS (TA = 25C, VCC = + 5.0 V, VEE = - 5.2 V, VRT = + 1.0 V, VRB = - 1.0 V, see System Timing Diagram, Figure 1.) Characteristic INPUTS Min Clock Pulse Width - High Min Clock Pulse Width - Low Max Clock Rise, Fall Time Clock Frequency OUTPUTS New Data Valid from Clock Low Aperture Delay Hold Time Data High to 3-State from Enable Low* Data Low to 3-State from Enable Low* Data High to 3-State from Enable High* Data Low to 3-State from Enable High* Valid Data from Enable High (Pin 20 = 0 V)* Valid Data from Enable Low (Pin 19 = 5.0 V)* Output Transition Time* (10% to 90%) *See Figure 2 for output loading. Symbol Min Typ Max Unit tCKH tCKL tR,F fCLK - - - 0 5.0 15 100 30 - - - 25 ns ns ns MHz tCKDV tAD tH tEHZ tELZ tEHZ tELZ tEDV tEDV ttr - - - - - - - - - - 19 4.0 6.0 27 18 32 18 15 16 8.0 - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns PIN FUNCTION DESCRIPTION Pin Function F i VRM GND OVR D7-D0 VCC(D) VEE Vin VCC(A) CLK EN EN VRB VRT P Suffix 1 2, 12 16, 22 3 4 to 10, 21 11, 17 13 14 15 18 19 20 23 24 DW Suffix 1 2, 13, 17 18, 25, 26 3 4 to 10, 24 11, 12 19, 20 14 15 16 21 22 23 27 28 Description D ii The midpoint of the reference resistor ladder. Bypassing can be done at this point to improve performance at high frequencies. Digital ground. The pins should be connected directly together, and through a low impedance path to the power supply. Overrange output. Indicates Vin is more positive than VRT 1/2 LSB. This output does not have 3-state capability. Digital Outputs. D7 (Pin 4) is the MSB. D (Pin 21 or 24) is the LSB. LS-TTL compatible with 3-state capability. Power supply for the digital section. + 5.0 V, 10% required. Reference to digital ground. Negative power supply. Nominally - 5.2 V, it can range from - 3.0 to - 6.0 V, and must be more negative than VRB by V. Reference to analog ground. u1.3 Signal voltage input. This voltage is compared to the reference to generate a digital equivalent. Input impedance is nominally 16 to 33K in parallel with 36 pF. Power supply for the analog section. + 5.0 V, 10% required. Reference to analog ground. Clock input. TTL compatible. Enable input. TTL compatible, a logic 1 (and EN at a logic 0) enables the data outputs. A logic 0 puts the outputs in a 3-state mode. Enable input. TTL compatible, a logic 0 (and EN at a logic 1) enables the data outputs. A logic 1 puts the outputs in a 3-state mode. The bottom (most negative point) of the internal reference resistor ladder. The top (most positive point) of the internal reference resistor ladder. 4 MOTOROLA ANALOG IC DEVICE DATA MC10319 Figure 1. System Timing Diagram tCKH Clock 1.5 V 1.5 V tCKL 3.0 V 1.5 V 1.5 V tAD Vin Sample 1 tCKDV tH D7-D0, OR Old Data Sample 1 Sample 2 tAD Sample 2 tCKDV and tH measured at output levels of 0.8 and 2.4 V. 3.0 V EN 0.9 V 0.9 V 3.0 V 0.9 V tEHZ High Data Output 0.5 V tELZ Low Data Output 0.8 V 3-State tEDV 0.4 V Outputs Active tEDV 0.8 V tEDV 2.4 V 0.5 V tEDV 0.4 V tEDV 0.9 V tEDV 2.4 V EN Figure 2. Data Output Test Circuit VCC LEAKAGE CURRENT ( A) 200 Figure 3. Output 3-State Leakage Current 1.0 k D0 - D7 100 50 0 - 50 - 100 Pin 19 = 0 V 0 1.0 0C C1 3.0 k Diodes = 1N914 or equivalent, C1 15 pF - 200 - 1.0 t TA t 70C 5.0 6.0 7.0 2.0 3.0 4.0 APPLIED VOLTAGE (VOLTS) MOTOROLA ANALOG IC DEVICE DATA 5 MC10319 Figure 4. Input Capacitance @ Vin (Pin 14) 100 Iin, INPUT CURRENT ( A) 80 25C 60 0C C, CAPACITANCE (pF) 80 Figure 5. Input Current @ Vin (Pin 14) 40 70C 60 VRT - VRB = 1.0 V 20 40 0.1 V VRB VRT - VRB = 2.0 V 0 20 VRT Vin, INPUT VOLTAGE (VOLTS) - 2.5 VRB Vin, INPUT VOLTAGE (VOLTS) VRT + 2.5 Figure 6. Input Current @ Enable, Enable 10 0 - 10 Iin, INPUT CURRENT ( A) - 30 - 50 - 70 - 90 - 110 - 130 0 1.0 Vin, INPUT VOLTAGE (VOLTS) 2.0 5.5 + 70C 25C 0C Pin 19 Current 2 V < Pin 20 < 5 V Pin 19 (Pin 20 = 0 V) Pin 20 (0 < Pin 19 < 5 V) 40 20 0 - 20 - 40 70C - 60 25C - 80 0C - 100 - 120 0 1.0 Figure 7. Clock Input Current Iin, INPUT CURRENT ( A) 2.0 3.0 4.0 5.0 6.0 Vin, INPUT VOLTAGE (VOLTS) Figure 8. Output Voltage versus Output Current 0.5 VOH ,OUTPUT VOLTAGE (VOLTS) 5.0 VOL, OUTPUT VOLTAGE (VOLTS) 0.4 Figure 9. Output Voltage versus Output Current 0 and 70C 0.3 25C 4.0 0.2 0.1 4.5 V < VCC < 5.5 V 0 0 2.0 4.0 IOL, OUTPUT CURRENT (mA) 6.0 8.0 3.0 0 - 100 - 200 - 300 - 400 IOH, OUTPUT CURRENT (A) 6 MOTOROLA ANALOG IC DEVICE DATA MC10319 Figure 10. Supply Current versus Temperature ICC , SUPPLY CURRENT, PINS 11, 15, 17 (mA) 112 110 IEE, SUPPLY CURRENT, PIN 13 (mA) -12 Figure 11. Supply Current versus Temperature -11 108 -10 106 -9.0 VEE = - 5.2 V -8.0 104 102 0 VCC = 5.0 V 20 40 60 TA, AMBIENT TEMPERATURE (C) 70 0 20 40 60 TA, AMBIENT TEMPERATURE (C) 70 Figure 12. Differential Linearity Error Figure 13. Integral Linearity Error 1/2 LSB 1/2 LSB 0 0 - 1/2 LSB VRT = 2.0 V, VRB = 0 V Fs = 25 MHz 0 32 64 96 128 160 192 224 256 - 1/2 LSB VRT = 2.0 V, VRB = 0 V Fs = 25 MHz 0 32 64 96 128 160 192 224 256 Figure 14. Differential Linearity Error Figure 15. Integral Linearity Error 1/2 LSB 1/2 LSB 0 0 - 1/2 LSB VRT = 2.0 V, VRB = 0 V Fs = 12.5 MHz 0 32 64 96 128 160 192 224 256 - 1/2 LSB VRT = 2.0 V, VRB = 0 V Fs = 12.5 MHz 0 32 64 96 128 160 192 224 256 MOTOROLA ANALOG IC DEVICE DATA 7 MC10319 DESIGN GUIDELINES Introduction The MC10319 is a high speed, 8-bit, parallel ("flash") type analog-to-digital converter containing 256 comparators at the front end. See Figure 17 for a block diagram. The comparators are arranged such that one input of each is referenced to evenly spaced voltages, derived from the reference resistor ladder. The other input of the comparators is connected to the input signal (Vin). Some of the comparators differential outputs will be "true," while other comparators will have "not true" outputs, depending on their relative position. Their outputs are then latched, and converted to an 8-bit Grey code by the Differential Latch Array. The Grey code ensures that any input errors due to cross talk, feed-thru, or timing disparities result in glitches at the output of only a few LSBs, rather than the more traditional 1/2 scale and 1/4 scale glitches. The Grey code is then translated to an 8-bit binary code, and the differential levels are translated to TTL levels before being applied to the output latches. Enable inputs at this final stage permit the TTL outputs (except overrange) to be put into a high impedance (3-state) condition. Reference The reference resistor ladder is composed of a string of equal value resistors to provide 256 equally spaced voltages for the comparators (see Figure 17 for the actual configuration). The voltage difference between adjacent comparators corresponds to 1 LSB of the input range. The first comparator (closest to VRB) is referenced 1/2 LSB above VRB, and 256th comparator (for the overrange) is referenced 1/2 LSB below VRT. The total resistance of the ladder is nominally 130 , 20%, requiring 15.4 mA @ 2.0 V, and 7.7 mA @ 1.0 V. There is a nominal warm-up change of + 9.0% in the ladder resistance due to the + 0.29%/C temperature coefficient. The minimum recommended span [VRT - VRB] is 1.0 V. A lower span will allow offsets and nonlinearities to become significant. The maximum recommended span is 2.1 V due to power limitations of the resistor ladder. The span may be anywhere within the range of - 2.1 to + 2.1 V with respect to ground, and VRB must be at least 1.3 V more positive than VEE. The reference voltages must be stable and free of noise and spikes, since the accuracy of a conversion is directly related to the quality of the reference. In most applications, the reference voltages will remain fixed. In applications involving a varying reference for modulation or signal scrambling, the modulating signal may be applied to VRT, or VRB, or both. The output will vary inversly with the reference signal, introducing a nonlinearity into the transfer function. The addition of the modulating signal and the dc level applied to the reference must be such that the absolute voltage at VRT and VRB is maintained within the values listed in the Recommended Operating Limits. The RMS value of the span must be maintained V. VRM (Pin 1) is the midpoint of the resistor ladder, excluding the Overrange comparator. The voltage at VRM is: ANALOG SECTION Signal Input The signal voltage to be digitized (Vin) is applied simultaneously to one input of each of the 256 comparators through Pin 14. The other inputs of the comparators are connected to 256 evenly spaced voltages derived from the reference ladder. The output code depends on the relative position of the input signal and the reference voltages. The comparators have a bandwidth of MHz, which is more than sufficient for the allowable (Nyquist Theorem) input frequency of 12.5 MHz. The current into Pin 14 varies linearly from 0 (when Vin = VRB) to 60 A (when Vin = VRT). If Vin is taken below VRB or above VRT, the input current will remain at the value corresponding to VRB and VRT respectively (see Figure 5). However, Vin must be maintained within the absolute range of 2.5 V (with respect to ground) - otherwise excessive currents will result at Pin 14, due to internal clamps. The input capacitance at Pin 14 is typically 36 pF if [VRT - VRB] is 2.0 V, and increases to 55 pF if [VRT - VRB] is reduced to 1.0 V (see Figure 4). The capacitance is constant as Vin varies from VRT down to 0.1 V above VRB. Taking Vin to VRB will show an increase in the capacitance of 50%. If Vin is taken above VRT, or below VRB, the capacitance will stay at the values corresponding to VRT and VRB, respectively. The source impedance of the signal voltage should be maintained below 100 (at the frequencies of interest) in order to avoid sampling errors. u50 p2.1 V RT ) VRB * 1 2 LSB 2.0 In most applications, bypassing this pin to ground (0.1 F) is sufficient to maintain accuracy. In applications involving very high frequencies, and where linearity is critical, it may be necessary to trim the voltage at the midpoint. A means for accomplishing this is indicated in Figure 18. Power Supplies VCC(A) is the positive power supply for the comparators, and VCC(D) is the positive power supply for the digital portion. Both are to be + 5.0 V, 10%, and the two are to be within 100 mV of each other. There is indirect internal coupling between VCC(D) and VCC(A). If they are powered separately, and one supply fails, there will be current flow through the MC10319 to the failed supply. 8 MOTOROLA ANALOG IC DEVICE DATA MC10319 ICC(A) is nominally 17 mA, and does not vary with clock frequency or with Vin. It does vary linearly with VCC(A). ICC(D) is nominally 90 mA, and is independent of clock frequency. It does vary, however, by 6 to 7 mA as Vin is changed, with the lowest current occurring when Vin = VRT. It varies linearly with VCC(D). VEE is the negative power supply for the comparators, and is to be within the range - 3.0 to - 6.0 V. Additionally, VEE must be at least 1.3 V more negative than VRB. IEE is a nominal - 10 mA, and is independent of clock frequency, Vin, and VEE. For proper operation, the supplies must be bypassed at the IC. A 10 F tantalum, in parallel with a 0.1 F ceramic is recommended for each supply to ground. The comparator output latches provide the circuit with an effective sample-and-hold function, eliminating the need for an external sample-and-hold. Enable Inputs The two Enable inputs are TTL compatible, and are used to change the data outputs (D7-D0) from active to 3-state. This capability allows cascading two MC10319s into a 9-bit configuration, flip-flopping two MC10319s into a 50 MHz configuration, connecting the outputs directly to a data bus, multiplexing multiple converters, etc. See the Applications Information section for more details. For the outputs to be active, Pin 19 must be a Logic "1", and Pin 20 must be a Logic "0". Changing either input will put the outputs into the high impedance mode. The Enable inputs affect only the state of the outputs - they do not inhibit a conversion. The input current into Pins 19 and 20 is shown in Figure 6, and the input/output timing is shown in Figure 1 and 20. Leaving either pin open is equivalent to a Logic "1", although good design practice dictates that an input should never be left open. The Overrange output (Pin 3) is not affected by the Enable inputs as it does not have 3-state capability. Outputs The Data outputs are TTL level outputs with high impedance capability. Pin 4 is the MSB (D7), and Pin 21 is the LSB (D0). The eight outputs are active as long as the Enable inputs are true (Pin 19 = high, Pin 20 = low). The timing of the outputs relative to the Clock input and the Enable inputs is shown in Figures 1 and 20. Figures 8 and 9 indicate the output voltage versus load current, while Figure 3 indicates the leakage current when in the high impedance mode. The output code is natural binary, depicted in the table below. The Overrange output (Pin 3) goes high when the input, Vin, is more positive than VRT - 1/2 LSB. This output is always active - it does not have high impedance capability. Besides being used to indicate an input overrange, it is additionally used for cascading two MC10319s to form a 9-bit A/D converter (see Figure 27). DIGITAL SECTION Clock The Clock input is TTL compatible with a typical frequency range of 0 to 30 MHz. There is no duty cycle limitations, but the minimum low and high times must be adhered to. See Figure 7 for the input current requirements. The conversion sequence is shown in Figure 19, and is as follows: * On the rising edge, the data output latches are latched with old data, and the comparator output latches are released to follow the input signal (Vin). * During the high time, the comparators track the input signal. The data output latches retain the old data. * On the falling edge, the comparator outputs are latched with the data immediately prior to this edge. The conversion to digital occurs within the device, and the data output latches are released to indicate the new data within 20 ns. * During the clock low time, the comparator outputs remain latched, and the data output latches remain transparent. A summary of the sequence is that data present at Vin just prior to the Clock falling edge is digitized and available at the data outputs immediately after that same falling edge. Table 1. Output Code VRT, VRB (V) Output Code FFH FFH FFH FEH FFH 80H 00H 01H 00H uVRT - 1/2 LSB Input I 2.048 V, 0 V VRT - 1/2 LSB VRT - 1 LSB VRT - 1-1/2 LSB Midpoint VRB + 1/2 LSB u2.044V 2.044 V 2.040 V 2.036 V 1.024 V 4.0 mV V + 1.0 V, - 1.0 V u0.9961 V 0.9961 V 0.992 V 0.988 V 0.000 V - 0.9961 V 1.0 V + 1.0 V, 0 V u0.9980 V 0.9980 V 0.9961 V 0.9941 V 0.5000 V 1.95 mV V Overrange O 1 01 0 0 0 0 0 tVRB t0 t- t0 MOTOROLA ANALOG IC DEVICE DATA 9 MC10319 APPLICATIONS INFORMATION Power Supplies, Grounding The PC board layout, and the quality of the power supplies and the ground system at the IC are very important in order to obtain proper operation. Noise, from any source, coming into the device on VCC, VEE, or ground can cause an incorrect output code due to interaction with the analog portion of the circuit. At the same time, noise generated within the MC10319 can cause incorrect operation if that noise does not have a clear path to ac ground. Both the VCC and VEE power supplies must be decoupled to ground at the IC (within 1I max) with a 10 F tantalum and a 0.1 F ceramic. Tantalum capacitors are recommended since electrolytic capacitors simply have too much inductance at the frequencies of interest. The quality of the VCC and VEE supplies should then be checked at the IC with a high frequency scope. Noise spikes (always present when digital circuits are present) can easily exceed 400 mV peak, and if they get into the analog portion of the IC, the operation can be disrupted. Noise can be reduced by inserting resistors and/or inductors between the supplies and the IC. If switching power supplies are used, there will usually be spikes of 0.5 V or greater at frequencies of 50 to 200 kHz. These spikes are generally more difficult to reduce because of their greater energy content. In extreme cases, 3-terminal regulators (MC78L05ACP, MC7905.2CT), with appropriate high frequency filtering, should be used and dedicated to the MC10319. The ripple content of the supplies should not allow their magnitude to exceed the values in the Recommended Operating Limits table. The PC board tracks supplying VCC and VEE to the MC10319 should preferably not be at the tail end of the bus distribution, after passing through a maze of digital circuitry. The MC10319 should be close to the power supply, or the connector where the supply voltages enter the board. If the VCC and VEE lines are supplying considerable current to other parts of the boards, then it is preferable to have dedicated lines from the supply or connector directly to the MC10319. The four ground pins (2, 12, 16, and 22) must be connected directly together. Any long path between them can cause stability problems due to the inductance (at 25 MHz) of the PC tracks. The ground return for the signal source must be noise free. Reference Voltage Circuits Since the accuracy of the conversion is directly related to the quality of the references, it is imperative that accurate and stable voltages be provided to VRT and VRB. If the reference span is 2.0 V, then 1/2 LSB is only 3.9 mV, and it is desireable that VRT and VRB be accurate to within this amount, and furthermore, that they do not drift more than this amount once set. Over the temperature range of 0 to 70C, a maximum temperature coefficient of 28 ppm/C is required. The voltage supplies used for digital circuits should preferably not be used as a source for generating VRT and VRB, due to the noise spikes (50 to 400 mV) present on the supplies and on their ground lines. Generally 15 V, or 12 V, are available for analog circuits, and are usually clean compared to supplies used for digital circuits, although ripple may be present in varying amounts. Ripple is easier to filter out than spikes, however, and so these supplies are preferred. Figure 21 depicts a circuit which can provide an extremely stable voltage to VRT at the current required (the maximum reference current is 19.2 mA @ 2.0 V). The MC1403 series of reference sources has very low temperature coefficients, good noise rejection, and a high initial accuracy, allowing the circuit to be built without an adjustment pot if the VRT voltage is to remain fixed at one value. Using 0.1% wirewound resistors for the divider provides sufficient accuracy and stability in many cases. Alternately, resistor networks provide high ratio accuracies, and close temperature tracking. If the application requires VRT to be changed periodically, the two resistors can be replaced with a 20 turn, cermet potentiometer. Wirewound potentiometers should not be used for this type of application since the pot's slider jumps from winding to winding, and an exact setting can be difficult to obtain. Cermet pots allow for a smooth continuous adjustment. In Figure 21, R1 reduces the power dissipation in the transistor, and can be carbon composition. The 0.1 F capacitor in the feedback path provides stability in the unity gain configuration. Recommended op amps are: LM358, MC34001 series, LM308A, LM324, and LM11C. Offset drift is the key parameter to consider in choosing an op amp, and the LM308A has the lowest drift of those mentioned. Bypass capacitors are not shown in Figure 21, but should always be provided at the input to the 2.5 V reference, and at the power supply pins of the op amp. Figure 22 shows a simpler and more economical circuit, using the LM317LZ regulator, but with lower initial accuracy and temperature stability. The op amp/current booster is not needed since the LM317LZ can supply the current directly. In a well controlled environment, this circuit will suffice for many applications. Because of the lower initial accuracy, an adjustment pot is a necessity. Figure 23 shows two circuits for providing the voltage to VRB. The circuits are similar to those of Figures 21 and 22, and have similar accuracy and stability. The output transistor is a PNP in this case since the circuit must sink the reference current. 10 MOTOROLA ANALOG IC DEVICE DATA MC10319 VIDEO APPLICATIONS The MC10319 is suitable for digitizing video signals directly without signal conditioning, although the standard 1.0 Vpp video signal can be amplified to a 2.0 Vpp signal for slightly better accuracy. Figure 24 shows the input (top trace) and reconstructed output of a standard NTSC test signal, sampled at 25 MSPS, consisting of a sync pulse, 3.58 MHz color burst, a 3.58 MHz signal in a Sin2x envelope, a pulse, a white level signal, and a black level signal. Figure 25 shows a Sin2x pulse that has been digitized and reconstructed at 25 MSPS. The width of the pulse is 450 ns at the base. Figure 26 shows an application circuit for digitizing video. 9-Bit A/D Converter Figure 27 shows how two MC10319s can be connected to form a 9-bit converter. In this configuration, the outputs (D7 to D0) of the two 8-bit converters are paralleled. The outputs of one device are active, while the outputs of the other are in the 3-state mode. The selection is made by the Overrange output of the lower MC10319, which controls Enable inputs on the two devices. Additionally, this output provides the 9th bit. The reference ladders are connected in series, providing the 512 steps required for 9 bits. The input voltage range is determined by VRT of the upper MC10319, and VRB of the lower device. A minimum of 1.0 volt is required across each converter. The 500 pot (20 turn cermet) allows for adjustment of the midpoint since the reference resistors of the two MC10319s may not be identical in value. Without the adjustment, a non-equal voltage division would occur, resulting in a nonlinear conversion. If the references are to be symmetrical about ground (e.g., 1.0 V), the adjustment can be eliminated, and the midpoint connected to ground. The use of latches on the outputs is optional, depending on the application. 50 MHz, 8-Bit A/D Converter Figure 28 shows how two MC10319s can be connected together in a flip-flop arrangement in order to have an effective conversion speed of 50 MHz. The 74F74 D-type flip-flop provides a 25 MHz clock to each converter, and at the same time, controls the Enables so as to alternately enable and disable the outputs. The Overranges do not have 3-state capability, and so cannot be paralleled. Instead they are OR'd together. The use of latches is optional, and depends on the application. Data should be latched, or written to RAM (in a DMA operation), on the high-to-low transition of the 50 MHz clock. Negative Voltage Regulator In the cases where a negative power supply is not available (neither the - 3.0 to - 6.0 V, nor a higher negative voltage from which to derive it), the circuit of Figure 29 can be used to generate - 5.0 V from the + 5.0 V supply. The PC board space required is small ( 2.0 in2), and it can be located physically close to the MC10319. The MC34063A is a switching regulator, and in Figure 29 is configured in an inverting mode of operation. The regulator operating specifications are also given. Figure 16. Differential Phase and Gain Test HDS-1250 12-Bit D/A D3 D0 Video Signal (See Below) Clock MC10319 DUT 8 74F374 Latch 8 1.024 Vpp to Analyzer 120 100 571.4 mV (40 IRE) 60 285.7 mV 20 0 - 20 IRE Video Input Signal 1. 2. 3. 4. Input waveform: 571.4 mVpp, sine wave @ 3.579545 MHz, dc levels as shown above. MC10319 clock at 14.31818 MHz (4x) asynchronous to input. Differential gain: peak-to-peak output @ each IRE level compared to that at 0 IRE. Differential phase: Phase @ each IRE level compared to that @ 0 IRE. VRT 80 2.000 V 1.429 V (100 IRE) 40 VRB MOTOROLA ANALOG IC DEVICE DATA 11 MC10319 Figure 17. Representative Block Diagram ( + 5.0 V ) VCC(A) VRT VRB 24 23 R/2 15 256 R 255 R 254 VRT VRB R 129 VRM 1 0.1 R R Vin 14 R D I F F E R E N T I A L L A T C H A R R A Y ECL-to-TTL Converter and Latches 11,17 ( + 5.0 V ) VCC(D) 3 OR 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 TTL Outputs Grey Code Grey Code to Binary Converter S T A T E Binary C I R C U I T 9 10 21 128 R 3 R Reference Resistor Ladder R 2 R R/2 1 13 2,12,16, 22 18 Enable Clock (0 to 25 MHz) Enable 19 20 + 130 W 256 + 0.508 W VEE (- 3.0 to - 6.0 V) 12 MOTOROLA ANALOG IC DEVICE DATA MC10319 Figure 18. Adjusting VRM for Improved Linearity + 5.0 V 10 F + 5.0 V 0.1 VCC(A) VCC(D) Figure 21. Precision VRT Voltage Source R1 = 100 for + 5.0 V R1 = 620 for + 15 V + 5.0 to + 40 V In 2.5 V Reference (See Table) EN EN MC10319 25 MHz Clock VRT 500 0.1 VRB Input Signal - 5.2 V 10 F 0.1 VRB Vin VEE GND CLK VRT VRM D0 OR D7 Output Data Out 0.1 R1 1.5 k + or 1.0 k - 620 0.1 2N2222A to VRT GND 2.0 k 2.5 V References Line Regulation TC (ppm/C) max Vout for 0 to + 70C Initial Accuracy MC1403 0.5 mV 40 7.0 mV 1% MC1403A 0.5 mV 25 4.4 mV 1% Figure 19. Conversion Sequence Clock Figure 22. Voltage Source for VRT Pin Comparator outputs latched. (Valid data available after tCKDV) Latches Comparator outputs, opens data output latches. Data outputs latched, releases Comparator Latches. 200 510 + 5.0 to + 40 V LM317LZ Adj. 1.25 to 2.00 V Out 240 1.0 F 10 F In to VRT LM317LZ Figure 20. Enable to Output Critical Timing EN 0.9 V 12 0.9 V 21 3-State Line Regulation TC (ppm/C) max Vout for 0 to + 70C Initial Accuracy 1.0 mV 60 8.4 mV 4% D0 - D7 EN 0.9 V 12 0.9 V 16 Valid Data D0 - D7 Timing @ D7 to D0 measured where waveform starts to change. Indicated time values are typical @ 25_C, and are in ns. MOTOROLA ANALOG IC DEVICE DATA 13 MC10319 Figure 23. Voltage Sources for VRB Pin 0.1 2.5 V Regulator 1.0 k 2.0 k OR 1.5 k R1 - + 2N2907A 100 620 to VRB - 5.0 to - 40 V In LM337MT Adj. Out (- 1.25 to - 2.00 V) 120 to VRB 10 F 1.0 F 270 -2.5 V R2 0.1 - 5.0 to - 40 V R1 = 100 for - 5.0 V R1 = 620 for - 15 V R2 = 620 for - 5.0 V R1 = 3.0 k for - 15 V 2.5 V Reference Line Regulation TC (ppm/C) max Vout for 0 to + 70C Initial Accuracy LM337MT 1.0 mV 48 6.7 mV 4% Figure 24. Composite Video Waveform 500 mV INPUT OUTPUT 200 mV 5.0 s Figure 25. SIN2 x Waveform 500 mV INPUT OUTPUT 200 mV 100 ns 14 MOTOROLA ANALOG IC DEVICE DATA MC10319 Figure 26. Application Circuit for Digitizing Video + 5.0 V 10 F 14.3 MHz Clock + 15 V + 2.5 V Regulator 0.1 1.5 k + - 1.0 k 0.1 0.1 620 1.0 k - A1 + - 1.0 V 2N2907A Vin 620 1/2 W - 5.2 V 10 F 0.1 VEE GND A1 620 2N2222A + 1.0 V Iref VRT 0.1 VRM 620 1/2 W 0.1 + 5.0 V EN EN CLK VCC(A) VCC(D) OR MC10319 D7 Output Data - 2.5 V Regulator VRB D0 1.5 k - 2.5 V 3.0 k - 15 V 0.1 MC34080 + - 0.01 2.0 k Offset 1.0 k 1.0 k 3.0 pF 1.0 k 2.0 k - + MC34080 50 Video Input (1.0 Vpp) u10 F 25 NOTES: 1) 2) 3) 4) 5) MC34080is powered from 15 V supplies. MC34083 (Dual) may be used. Bypass capacitors required at power supply pins of all ICs. Ground plane required over all parts of circuit board. Care in layout around MC34080is necessary for good frequency response. A1 = MC34002. MOTOROLA ANALOG IC DEVICE DATA 15 MC10319 Figure 27. 9-Bit A/D Converter GND EN 0 to 25 MHz Clock + 2.0 V 0.1 CLK VRT VRM VRB OR D7 MC10319 D0 EN + 5.0 V 10 F 0.1 - 5.2 V CLK VEE VCC(D) VCC(A) 10 F 0.1 OR D8 D7 Vin V EE VCC(D) VCC(A) 500 0.1 0.1 VRT VRM EN OR - 2.0 V VRB CLK MC10319 D7 Vin + 5.0 V Vin EN GND D0 Latches (Optional) D0 16 MOTOROLA ANALOG IC DEVICE DATA MC10319 Figure 28. 50 MHz 8-Bit A/D Converter GND 50 MHz Clock CK D Q Q + 1.0 V 0.1 EN CLK VRT VRM VRB Vin VEE + 5.0 V VCC(D) VCC(A) 10 F 0.1 - 5.2 V EN VEE VRT VRM 0.1 - 1.0 V VRB OR VCC(D) VCC(A) 10 F 0.1 74F32 OR EN OR D7 74F74 MC10319 (#1) D0 MC10319 CLK (#2) D7 D7 Vin + 5.0 V Vin EN GND D0 Latches (Optional) D0 50 MHz Clock Q D0 - D7 (#1) D0 - D7 (#2) Valid Data Vin (4.5 to 5.5 V) 100 F Figure 29. - 5.0 V Regulator Test 2.2 Line Regulation Load Regulation 6 7 8 1 2 4 470 pF 1N5819 540 H Output Ripple Short Circuit Iout Efficiency 4.5 V Vin Iout = 10 mA t t 5.5 V, Vin = 5.0 V, 8.0 mA t Iout t 20 mA Vin = 5.0 V, Iout = 20 mA Vin = 5.0 V, R1 = 0.1 Vin = 5.0 V, Iout = 50 mA Conditions Results 0.16% 0.4% 2.0 mVpp 140 mA 52% MC34063A 5 3 3.0 k 1.0 k Vout - 5.0 V/20 mA 470 F 470 F 1.0 H MOTOROLA ANALOG IC DEVICE DATA 17 MC10319 GLOSSARY Aperture Delay - The time difference between the sampling signal (typically a clock edge) and the actual analog signal converted. The actual signal converted may occur before or after the sampling signal, depending on the internal configuration of the converter. Bipolar Input - A mode of operation whereby the analog input (of an A/D), or output (of a DAC), includes both negative and positive values. Examples are - 1.0 to + 1.0 V, - 5.0 to + 5.0 V, - 2.0 to + 8.0 V, etc. Bipolar Offset Error - The difference between the actual and ideal locations of the 00H to 01H transition, where the ideal location is 1/2 LSB above the most negative reference voltage. Bipolar Zero Error - The error (usually expressed in LSBs) of the input voltage location (of an A/D) of the 80H to 81H transition. The ideal location is 1/2 LSB above zero volts in the case of an A/D setup for a symmetrical bipolar input (e.g., - 1.0 to + 1.0 V). Differential Nonlinearity - The maximum deviation in the actual step size (one transition level to another) from the ideal step size. The ideal step size is defined as the Full Scale Range divided by 2n (n = number of bits). This error must be within 1 LSB for proper operation. ECL - Emitter coupled logic. Full Scale Range (Actual) - The difference between the actual minimum and maximum end points of the analog input (of an A/D). Full Scale Range (Ideal) - The difference between the actual minimum and maximum end points of the analog input (of an A/D), plus one LSB. Gain Error - The difference between the actual and expected gain (end point to end point), with respect to the reference, of a data converter. The gain error is usually expressed in LSBs. Grey Code - Also known as reflected binary code, it is a digital code such that each code differs from adjacent codes by only one bit. Since more than one bit is never changed at each transition, race condition errors are eliminated. Integral Nonlinearity - The maximum error of an A/D, or DAC, transfer function from the ideal straight line connecting the analog end points. This parameter is sensitive to dynamics, and test conditions must be specified in order to be meaningful. This parameter is the best overall indicator of the devices performance. Line Regulation - The ability of a voltage regulator to maintain a certain output voltage as the input to the regulator is varied. The error is typically expressed as a percent of the nominal output voltage. Load Regulation - The ability of a voltage regulator to maintain a certain output voltage as the load current is varied. The error is typically expressed as a percent of the nominal output voltage. LSB - Least Significant Bit. It is the lowest order bit of a binary code. Monotonicity - The characteristic of the transfer function whereby increasing the input code (of a DAC), or the input signal (of an A/D), results in the output never decreasing. MSB - Most Significant Bit. It is the highest order bit of a binary code. Natural Binary Code - A binary code defined by: N = An2n + . . . + A323 + A222 + A121 + A020 where each "A" coefficient has a value of 1 or 0. Typically, all zeroes correspond to a zero input voltage of an A/D, and all ones correspond to the most positive input voltage. Nyquist Theorem - See Sampling Theorem. Offset Binary Code - Applicable only to bipolar input (or output) data converters, it is the same as Natural Binary, except that all zeros correspond to the most negative input voltage (of an A/D), while all ones correspond to the most positive input. Power Supply Sensitivity - The change in a data converters performance with changes in the power supply voltage(s). This parameter is usually expressed in percent of full scale versus V. Quantitization Error - Also known as digitization error or uncertainty. It is the inherent error involved in digitizing an analog signal due to the finite number of steps at the digital output versus the infinite number of values at the analog input. This error is a minimum of 1/2 LSB. Resolution - The smallest change which can be discerned by an A/D converter, or produced by a DAC. It is usually expressed as the number of bits (n), where the converter has 2n possible states. Sampling Theorem - Also known as the Nyquist Theorem. It states that the sampling frequency of an A/D must be no less that 2x the highest frequency (of interest) of the analog signal to be digitized in order to preserve the information of that analog signal. Unipolar Input - A mode of operation whereby the analog input range (of an A/D), or output range (of a DAC), includes values of a signal polarity. Examples are 0 to + 2.0 V, 0 to - 5.0 V, 2.0 to 8.0 V, etc. Unipolar Offset Error - The difference between the actual and ideal locations of the 00H to 01H transition, where the ideal location is 1/2 LSB above the most negative input voltage. 18 MOTOROLA ANALOG IC DEVICE DATA MC10319 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 709-02 ISSUE C NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 24 13 B 1 12 A N K H G F D SEATING PLANE C L M J DW SUFFIX PLASTIC PACKAGE CASE 751F-04 (SO-28L) ISSUE E -A- 28 15 14X -B- 1 14 P 0.010 (0.25) M B M 28X D M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.01 10.55 0.25 0.75 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 0.010 (0.25) TA S B S M R C X 45 _ 26X G K -T- SEATING PLANE F J MOTOROLA ANALOG IC DEVICE DATA 19 MC10319 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 20 *MC10319/D* MOTOROLA ANALOG IC DEVICE DATA MC10319/D |
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