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Ordering number : EN*5937
CMOS IC
LC75386NE
Electronic Volume and Tone Control for Car Stereo Systems
Preliminary Overview
The LC75386NE is an electronic volume and tone control IC that can implement a wide range of functions including volume, balance, fader, bass and treble controls, loudness, input switching, and input gain control with a minimal number of external components.
Features
* On-chip buffer amplifiers minimize the number of external components required. * The low level of switching noise generated from internal switches due to fabrication in a CMOS process minimizes switching noise when no input signals are present. * The use of built-in zero-cross switching circuits minimizes switching noise when input signals are present. * Built-in VDD/2 reference voltage generation circuit * All controls are controlled from CCB serial data input.
Functions
* Volume: 0 to -79 dB ( in 1-dB steps) and - for a total of 81 settings. A balance function can be implemented by controlling the left and right channel volume settings independently. Fader: The rear or the front outputs can be attenuated over 16 settings. (0 to -2 dB in 1-dB steps, -2 to -20 dB in 2 dB steps, -20 to -30 dB in 10-dB steps, -45 dB, -60 dB, and - for a total of 16 settings.) Bass and treble: Control over a 12-dB range in 2-dB steps in each band. Input gain: The input signal can be amplified from 0 to +18.75 dB (in 1.25-dB steps). Input switching: One of 6 inputs can be selected for each of the left and right channels. (Five are single-ended inputs, and one is a differential input.) Loudness: Taps are output from the -32-dB positions of the 2-dB step volume ladder resistors, and loudness operation can be implemented by attaching external capacitors.
*
Package Dimensions
unit: mm 3159-QFP64E
[LC75386NE]
* * *
*
SANYO: QFP64E
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51298RM (OT) No. 5937-1/20
LC75386NE Pin Assignment
Top view
No. 5937-2/20
LC75386NE Equivalent Circuit and Application Circuit Diagram
No. 5937-3/20
LC75386NE
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Operating temperature Storage temperature Symbol VDD max VIN max Topr Tstg VDD All input pins Conditions Ratings 11 VSS - 0.3 to VDD + 0.3 -40 to +85 -50 to +125 Unit V V C C
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Supply voltage High-level input voltage Low-level input voltage Input amplitude Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VIN ToW Tsetup Thold fopg CL CL, DI, CE CL, DI, CE CL VDD CL, DI, CE CL, DI, CE Conditions Ratings min 6.0 4.0 VSS VSS 1 1 1 500 typ max 10.5 VDD 1.0 VDD Unit V V V Vp-p s s s kHz
Electrical Characteristics at Ta = 25C, VDD = 9 V, VSS = 0 V Input Block
Parameter Input resistance Minimum input gain Maximum input gain Inter-step setting error Left/right balance Symbol Rin Ginmin Ginmax ATerr BAL Applicable pins L1 to L4, L6, R1 to R4, R6 L1 to L4, L6, R1 to R4, R6 Conditions Ratings min 35 -1 +16.5 typ 50 0 +18.75 max 65 +1 +21 0.6 0.5 Unit k dB dB dB dB
Volume Control Block
Parameter Input resistance Inter-step setting error Left/right balance Symbol Rvr ATerr BAL Applicable pins LVRIN, RVRIN, Loudness off Conditions Ratings min 158 typ 226 max 294 0.5 0.5 Unit k dB dB
Tone Control Block
Parameter Inter-step setting error Bass control range Treble control range Left/right balance Symbol ATerr Gbass Gtre BAL max. boost/cut max. boost/cut 9 9 12 12 Applicable pins Conditions Ratings min typ max 1.0 15 15 0.5 Unit dB dB dB dB
No. 5937-4/20
LC75386NE Fader Control Block
Parameter Input resistance Symbol Rfed Applicable pins LFIN, RFIN 0 dB to -2 dB Inter-step setting error ATerr -2 dB to -20 dB -20 dB to -30 dB -30 dB to -60 dB Left/right balance BAL Conditions Ratings min 25 typ 50 max 100 0.5 1 2 3 0.5 Unit k dB dB dB dB dB
Overall Characteristics
Parameter Symbol THD1 THD2 CT CT Vomin1 Vomin2 VN1 VN2 IDD IIH IIL VCL CL, DI, CE, VIN = 9 V CL, DI, CE, VIN = 0V THD = 1%, RL = 10 k, All flat, fIN = 1 kHz -10 2.5 2.9 Conditions VIN = -10 dBV, f = 1 kHz VIN = -10 dBV, f = 10 kHz VIN = 1 Vrms, f = 1 kHz VIN = 1 Vrms, f = 1 kHz VIN = 1 Vrms, f = 1 kHz VIN = 1 Vrms, f = 1 kHz, INMUTE, Fader: - All flat, IHF-A filter All flat, 20 Hz to 20 kHz bandpass filter 80 80 80 90 Ratings min typ 0.004 0.006 88 88 88 95 5 7 33 10 15 40 10 max 0.01 0.01 Unit % % dB dB dB dB V V mA A A Vrms
Total harmonic distortion Inter-input crosstalk Left/right crosstalk Maximum attenuation
Output noise voltage Current drain High-level input current Low-level input current Maximum input voltage
Control System Timing and Data Format The LC75386NE is controlled by inputting stipulated data serially to the CL, DI, and CE pins. The data consists of a total of 52 bits, of which 8 bits are the address and 44 bits are the actual control data.
Note*: The minimum value is determined by the value of the capacitor connected to the TIM pin (pin 20). If the value of the capacitor is CTIM and the minimum value is TDmin, then: TDmin = 3 x 103 x CTIM If CTIM is 0.033 F, then: TDmin = 3 x 103 x 0.033 x 10-6 100 s
No. 5937-5/20
LC75386NE * Address Code (B0 to A3) The LC75386NE has an 8-bit address code and can be used on a bus shared with other Sanyo ICs. Address Code
(LSB) B0 1 B1 0 B2 0 B3 0 A0 0 A1 0 A2 0 A3 1 (81HEX)
* Control code allocation Input Switching Control
D0 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D2 0 0 0 0 1 1 1 1 L1 (R1) L2 (R2) L3 (R3) L4 (R4) L5 (R5) L6 (R6) IC test values: These values must not be used during normal operation.
D3
IC test bit: This bit must be set to 0.
Input Gain Control
D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 dB +1.25 dB +2.50 dB +3.75 dB +5.00 dB +6.25 dB +7.50 dB +8.75 dB +10.0 dB +11.25 dB +12.5 dB +13.75 dB +15.0 dB +16.25 dB +17.5 dB +18.75 dB
No. 5937-6/20
LC75386NE Volume Control
D8 D9 D10 D11 D12 D13 D14 D15 1 dB step 0 1 0 dB -1 dB 2 dB step 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -22 dB -24 dB -26 dB -28 dB -30 dB -32 dB -34 dB -36 dB -38 dB -40 dB -42 dB -44 dB -46 dB -48 dB -50 dB -52 dB -54 dB -56 dB -58 dB -60 dB -62 dB -64 dB -66 dB -68 dB -70 dB -72 dB -74 dB -76 dB -78 dB Mute 1 0 1 1 1 1 1 1 1 1 1 1 0 0 - Inmute
No. 5937-7/20
LC75386NE Tone Control
D16 D24 0 1 0 1 0 1 0 1 0 1 0 1 0 D17 D25 1 0 0 1 1 0 0 0 1 1 0 0 1 D18 D26 1 1 1 0 0 0 0 0 0 0 1 1 1 D19 D27 0 0 0 0 0 0 0 1 1 1 1 1 1 Bass Treble +12 dB +10 dB +8 dB +6 dB +4 dB +2 dB 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB
D20 0
D21 0
D22 0
D23 0 These bits must be set to 0
Fader Volume Control
D28 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D29 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D30 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D31 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 dB -1 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -30 dB -45 dB -60 dB -
Channel Selection Control
D32 0 1 0 1 D33 0 0 1 1 Initial setup mode: rapid charging RCH LCH Left and right together
No. 5937-8/20
LC75386NE Fader Rear/Front Control
D34 0 1 Rear Front
Loudness Control
D35 0 1 Off On
Zero Cross Control
D36 0 1 D37 0 1 Data written when a zero crossing is detected Zero cross detection disabled (Data is written when CE falls)
Zero Cross Signal Detection Block Control
D38 0 1 0 1 D39 0 0 1 1 D40 0 0 0 0 D41 0 0 0 0 Selector Volume Tone Fader
Test Mode Control
D42 0 D43 0 This bit is used for IC testing and must be set to 0
No. 5937-9/20
LC75386NE Pin Descriptions
Pin No. 54 53 52 51 55 59 60 61 62 58 Pin name L1 L2 L3 L4 L6 R1 R2 R3 R4 R6 * Single-ended inputs Function Notes
50 49 63 64
L5M L5P R5M R5P * Differential inputs
48 1
LSEL0 RSEL0
* Input selector outputs
47 2
LVRIN RVRIN
* 2-dB step volume control inputs * Input signals must be provided from a low-impedance circuit.
46 3
LCT RCT
* Loudness connections. Connect the high-band compensation CR circuit between LCT (RCT) and LVRIN (RVRIN), and connect the low-band compensation CR circuit between LCT (RCT) and Vref.
45 4
LCOM RCOM
* 2-dB step volume control outputs * Connect these pins to Vref through coupling capacitors to reduce switching noise.
43 6
LTIN RTIN
* Equalizer inputs
Continued on next page. No. 5937-10/20
LC75386NE
Continued from preceding page.
Pin No. 42 41 40 7 8 9 36 35 34 13 14 15 39 38 37 10 11 12 Pin name LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3 LF3C1 LF3C2 LF3C3 RF3C1 RF3C2 RF3C3 NC NC NC NC NC NC * Unused pins. These pins are not connected to any part of the IC. * Connections for the capacitors that form the filters used for tone circuit high band. Connect capacitors between: LF3C1 (RF3C1) and LF3C2 (RF3C2), and between LF3C2 (RF3C2) and LF3C3 (RF3C3). * Connections for the capacitors that form the filters used for tone circuit low band. Connect capacitors between: LF1C1 (RF1C1) and LF1C2 (RF1C2), and between LF1C2 (RF1C2) and LF1C3 (RF1C3). Function Notes
33 16
LTOUT RTOUT
* Equalizer outputs
32 17
LFIN RFIN
* Fader block inputs * These pins must be driven by low-impedance circuits.
31 30 18 19
LFOUT LROUT RFOUT RROUT * Fader outputs. The front and rear signals are attenuated separately. The amount of the attenuation is the same in the left and right channels.
57
Vref
* A capacitor with a value of a few tens of F must be connected between Vref and AVSS (VSS) to reduce power supply ripple in the VDD/2 voltage generation block.
56
VDD
* Power supply
27
DVSS
* Logic system ground
29 22
LAVSS RAVSS
* Analog system ground
Continued on next page.
No. 5937-11/20
LC75386NE
Continued from preceding page.
Pin No. Pin Function Notes
28 21
LZCLP RZCLP
* Zero cross detector circuit band control
* Externally controlled muting input 23 MUTE * Setting this pin to the V SS level forcibly sets the fader volume block to the - setting.
* Time control for the zero cross circuit when no signal is present 20 TIM If there is no zero cross signal between the point the data is loaded and the point the time defined by this pin elapses, the data is loaded forcibly.
26 25
CL DI
* Serial data and clock input for chip control
24
CE
* Chip enable. Data is written to the internal latch when this pin is switched from high to low, and the analog switches operate.Transfer data becomes enable when this pin is at high level.
44 5
LVROUT RVROUT
* 1-dB step volume control outputs
No. 5937-12/20
LC75386NE Internal Equivalent Circuits Selector Block Equivalent Circuit
Total resistance: 50 k The right channel is identical. Unit (resistance: )
No. 5937-13/20
LC75386NE 2-dB Volume Control Block Equivalent Circuit
To the left channel 1-dB block
* Total resistance in the tap: 195 k
Initial settings switch The right channel is identical. Unit (resistance: )
* Total resistance in the tap: 30.847 k
No. 5937-14/20
LC75386NE 1-dB Volume Control Block Equivalent Circuit
From the left channel 2-dB block
Initial settings switch
Initial settings switch
Unit (resistance: ) Total resistance: 50 k The right channel is identical.
Tone Control Block Equivalent Circuit
Unit (resistance: )
No. 5937-15/20
LC75386NE External Capacitor Calculations The LC75386NE external capacitors are the structural components in semiconductor inductors, i.e. simulated inductors. This section presents the equivalent circuit and the formulas used to calculate the desired center frequencies. Semiconductor inductor equivalent circuit
Z0: Impedance at resonance
Sample calculation Specifications: 1. Center frequency: F0 = 100 Hz 2. Q at maximum boost: Q+12dB = 0.9 * Determine the sharpness, Q0, of the semiconductor inductor. (R1 + R4) Q0 = ---------- x Q+12dB 1.53999 R1 * Determine C1. C1 = 1/2 FOR1QO 1 (F) * Determine C2. C2 = QO/2 FOR2 0.036 (F) Note: See the tone control block equivalent circuit diagram in page 15 for the internal resistance.
No. 5937-16/20
LC75386NE Fader Volume Control Block Equivalent Circuit
When FADER = 1, S2 and S3 will be on. When FADER = 0, S1 and S4 will be on.
Unit (resistance: ) Total resistance: 50 k
If data corresponding to a - is send to the 1-dB step main volume, S1 and S2 will be set open and S3 and S4 will be turned on at the same time.
No. 5937-17/20
LC75386NE Usage Notes * Notes on data transfer when power is first applied -- The states of the internal analog switches are undefined when power is first applied. Until the control data has been set up, applications must mute signals appropriately. -- Applications should send initial setup data to quickly stabilize the bias levels in each block when power is first applied. * The period between initial setup mode and initial data setup -- Applications should transfer the initial setup data after the power-supply voltage VDD exceeds 6 V. -- Send initial data (that turns the rapid charging switches off) after the LCOM, RCOM, and VREF pin levels have stabilized.
Time until the capacitors connected to the LCOM and RCOM pins are charged to the VREF level.
1/2 VDD level
Data
Initial setup mode
Initial data (left channel)
Initial data (right channel)
These operations clear initial setup mode
* Procedure for transferring the initial setup data Quick charge mode is set up when D32 and D33 are set to 00. Since the other data (D0 to D31, and D34 to D43) is set up for the left and right channels at the same time, the states of the other blocks can be set at the same time. * Procedure for clearing the initial setup data Quick charge mode is cleared when D32 and D33 are set to a value other than 00, that is when normal left/right channel operation is specified. Operating Principles of the Zero Cross Switching Circuit The LC75386NE provides a function that switches the signal detection location of the zero cross comparator. This means an optimal location for block for data update can be selected. Basically, switching noise can be minimized by inputting the signal from immediately after the block that modifies the data to the zero cross comparator. Therefore, the detection location needs to be changed each time the IC control settings are changed.
Selector
Volume
Tone
Fader
Switch Zero cross comparator
Zero Cross Detection Circuit
No. 5937-18/20
LC75386NE Zero Cross Switching Control Zero cross switching is controlled by setting the zero cross control bits to zero cross detection mode (by setting both D36 and D37 to 0), specifying the detection block (with bits D38, D39, D40, and D41), and transferring the data. Since these control bits are latched immediately after the data is transferred, that is, on the falling edge of the CE signal, when volume and other setting data is changed, it is possible to also set the mode and the zero cross operation at the same time in a single data transfer operation. The example below shows a control pattern that can be used at the same time as the volume setting data is updated.
D36 0 D37 0 D38 1 D39 0 D40 0 D41 0
Zero cross detection mode setting
Volume block setting
Zero Cross Timer Setting When the level of the input signal is lower than the zero cross detector sensitivity setting, or when the input signal is a low-frequency signal, the system will remain in a state where it cannot detect a zero cross event for an extended period, and the IC will not be able to latch data during that period. The zero cross timer sets a period for forcibly latching the data when the IC is in a state such as this where a zero cross cannot be detected. For example, to set a time of 25 ms: T = 0.69 x C x R If C = 0.033 F, then: 25 x 10-3 R = ------------------ 1.1 M 0.69 x 0.033 x 10-6 This time is normally set to be in the range 10 to 50 ms. Notes on Serial Data Transfer * The CL, DI, and CE pin signal lines must be covered by the ground pattern, or shielded cables must be used for these lines, to prevent high-frequency noise from these signals from entering the audio signal. * The LC75386NE data format consists of 8 bits of address and 44 bits of data. Use the data transfer format shown in the figure below when transmitting data in multiples of 8 bits (i.e. when sending 48 bits of data). Data Transfer to the LC75386NE in 8-Bit Units
Dummy data
Input switching control
Test mode control
No. 5937-19/20
LC75386NE
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5937-20/20

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