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100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch
April 1989 Revised August 2000
100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch
General Description
The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the 100328 transparent. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is -2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100328 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 k pull-down resistors.
Features
s Identical performance to the 100128 at 50% of the supply current s Bi-directional translation s 2000V ESD protection s Latched outputs s FAST TTL outputs s 3-STATE outputs s Voltage compensated operating range = -4.2V to -5.7V s Available to industrial grade temperature range
Ordering Code:
Order Number 100328SC 100328PC 100328QC 100328QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40C to +85C)
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names E0-E7 T0-T7 OE LE DIR Description ECL Data I/O TTL Data I/O Output Enable Input Latch Enable Input Direction Control Input
All pins function at 100K ECL levels except for T0-T7.
FAST is a registered trademark of Fairchild Semiconductor Corporation.
(c) 2000 Fairchild Semiconductor Corporation
DS010219
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100328
Connection Diagrams
24-Pin DIP/SOIC
Functional Diagram
28-Pin PLCC
Truth Table
OE L L L H H H H H H DIR X L H L L L H H H LE L H H L L H L L H ECL Port LOW (Cut-Off) Input LOW (Cut-Off) L H X L H Latched L H L H X Z Input (Note 1)(Note 3) (Note 2)(Note 3) (Note 1)(Note 4) (Note 1)(Note 4) (Note 2)(Note 4) (Note 2)(Note 4) (Note 2)(Note 4)
Note: LE, DIR, and OE use ECL logic levels
TTL Port Z
Notes
Detail
Latched (Note 1)(Note 3)
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent.
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Absolute Maximum Ratings(Note 5)
Storage Temperature (TSTG) VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin ECL Input Voltage (DC) ECL Output Current (DC Output HIGH) TTL Input Voltage (Note 6) TTL Input Current (Note 6) Voltage Applied to Output in HIGH State 3-STATE Output Current Applied to TTL Output in LOW State (Max) ESD (Note 7) twice the rated IOL (mA)
-65C to +150C -7.0V to +0.5V -0.5V to +6.0V
VEE to +0.5V
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) 0C to +85C
Maximum Junction Temperature (TJ) +150C
-40C to +85C -5.7V to -4.2V +4.5V to +5.5V
-50 mA -0.5V to +6.0V -30 mA to +5.0 mA
-0.5V to +5.5V
Note 5: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 6: Either voltage limit or current limit is sufficient to protect inputs. Note 7: ESD testing conforms to MIL-STD-883, Method 3015.
2000V
Commercial Version TTL-to-ECL DC Electrical Characteristics (Note 8)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C, VTTL = +4.5V to +5.5V Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Cutoff Voltage -2000 VOHC VOLC VIH VIL IIH IIL VFCD IEE Output HIGH Voltage Corner Point HIGH Output LOW Voltage Corner Point LOW Input HIGH Voltage Input LOW Voltage Input HIGH Current Breakdown Test Input LOW Current Input Clamp Diode Voltage VEE Supply Current -159 -169 -75 -75 mA -700 -1.2 2.0 0 -1950 mV Min -1025 -1830 Typ -955 -1705 Max -870 -1620 Units mV mV Conditions VIN = VIH(Max) or VIL(Min) Loading with 50 to - 2V OE or DIR LOW, VIN = VIH(Max) or VIL(Min), Loading with 50 to -2V -1035 -1610 5.0 0.8 70 1.0 mV mV V V A mA A V VIN = VIH(Min) or VIL(Max) Loading with 50 to -2V Over VTTL, VEE, TC Range Over VTTL, VEE, TC Range VIN = +2.7V VIN = +5.5V VIN = +0.5V IIN = -18 mA LE LOW, OE and DIR HIGH Inputs OPEN VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V
Note 8: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
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100328
Commercial Version (Continued) ECL-to-TTL DC Electrical Characteristics (Note 9)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol VOH VOL VIH VIL IIH IIL IOZHT IOZLT IOS ITTL Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 3-STATE Current Output HIGH 3-STATE Current Output LOW Output Short-Circuit Current VTTL Supply Current -700 -150 -60 74 49 67 0.50 70 -1165 -1830 Min 2.7 2.4 Typ 3.1 2.9 0.3 0.5 -870 -1475 350 Max Units V V mV mV A A A A mA mA mA mA Conditions IOH = -3 mA, VTTL = 4.75V IOH = -3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIH (Max) VIN = VIL (Min) VOUT = +2.7V VOUT = +0.5V VOUT = 0.0V, VTTL = +5.5V TTL Outputs LOW TTL Outputs HIGH TTL Outputs in 3-STATE
DIP TTL-to-ECL AC Electrical Characteristics (Note 9)
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND TC = 0C TC = 25C Symbol Parameter Min Max Min Max tPLH tPHL tPLH tPHL tPZH tPHZ tPHZ tSET tHOLD tPW(H) tTLH tTHL OE to En (Cutoff to HIGH) OE to En (HIGH to Cutoff) DIR to En (HIGH to Cutoff) Tn to LE Tn to LE Pulse Width LE Transition Time 20% to 80%, 80% to 20% TN to En (Transparent) LE to En 1.1 1.7 1.3 1.5 1.6 1.1 1.1 2.1 0.6 1.6 3.5 3.6 4.2 4.5 4.3 1.1 1.7 1.5 1.6 1.6 1.1 1.1 2.1 0.6 1.6 3.6 3.7 4.4 4.5 4.3 TC = 85C Min 1.1 1.9 1.7 1.6 1.7 1.1 1.1 2.1 0.6 1.6 Max 3.8 3.9 4.8 4.6 4.5 ns ns ns ns ns ns ns ns ns Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Units Conditions
Note 9: The specified limits represent the "worst" case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
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Commercial Version (Continued) DIP ECL-to-TTL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF TC = 0C TC = 25C Symbol Parameter Min Max Min Max tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSET tHOLD tPW(H) OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En to LE En to LE Pulse Width LE 3.4 3.8 3.2 3.0 2.7 2.8 1.1 2.1 4.1 8.45 9.2 8.95 7.7 8.2 7.45 3.7 4.0 3.3 3.4 2.8 3.1 1.1 2.1 4.1 8.95 9.2 8.95 8.7 8.7 7.95 4.0 4.3 3.5 4.1 3.1 4.0 1.1 2.6 4.1 9.7 9.95 9.2 9.95 8.95 9.2 ns ns ns ns ns ns Figures 3, 5 Figures 3, 5 Figures 3, 6 Figures 3, 6 Figures 3, 4 Figures 3, 7 En to Tn (Transparent) LE to Tn 3.1 7.2 3.1 7.2 3.3 7.7 ns Figures 3, 4 2.3 5.6 2.4 5.6 TC = 85C Min 2.6 Max 5.9 ns Figures 3, 4 Units Conditions
SOIC and PLCC TTL-to-ECL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V Symbol tPLH tPHL tPLH tPHL tPZH tPHZ tPHZ tSET tHOLD tPW(H) tTLH tTHL tOSHL OE to En (Cutoff to HIGH) OE to En (HIGH to Cutoff) DIR to En (HIGH to Cutoff) Tn to LE Tn to LE Pulse Width LE Transition Time 20% to 80%, 80% to 20% Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path
Note 10: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design.
Parameter Tn to En (Transparent) LE to En
TC = 0C Min 1.1 1.7 1.3 1.5 1.6 1.0 1.0 2.0 0.6 1.6 Max 3.3 3.4 4.0 4.3 4.1
TC = 25C Min 1.1 1.7 1.5 1.6 1.6 1.0 1.0 2.0 0.6 1.6 Max 3.4 3.5 4.2 4.3 4.1
TC = 85C Min 1.1 1.9 1.7 1.6 1.7 1.0 1.0 2.0 0.6 1.6 Max 3.6 3.7 4.6 4.4 4.3
Units ns ns ns ns ns ns ns ns ns
Conditions Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 PLCC Only
200
200
200
ps
(Note 10) PLCC Only
200
200
200
ps
(Note 10) PLCC Only
650
650
650
ps
(Note 10) PLCC Only
650
650
650
ps
(Note 10)
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100328
Commercial Version (Continued) SOIC and PLCC ECL-to-TTL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = 0C Symbol Parameter Min Max tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSET tHOLD tPW(H) tOSHL OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En to LE En to LE Pulse Width LE Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path
Note 11: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
TC = 25C Min 2.4 3.1 3.7 4.0 3.3 3.4 2.8 3.1 1.0 2.0 4.0 Max 5.4 7.0 8.75 9.0 8.75 8.5 8.5 7.75
TC = 85C Min 2.6 3.3 4.0 4.3 3.5 4.1 3.1 4.0 1.0 2.5 4.0 Max 5.7 7.5 9.5 9.75 9.0 9.75 8.75 9.0
Units ns ns
Conditions Figures 3, 4 Figures 3, 4
En to Tn (Transparent) LE to Tn
2.3 3.1 3.4 3.8 3.2 3.0 2.7 2.8 1.0 2.0 4.0
5.4 7.0 8.25 9.0 8.75 7.5 8.0 7.25
ns ns ns ns ns ns
Figures 3, 5 Figures 3, 5 Figures 3, 6 Figures 3, 4 Figures 3, 4 Figures 3, 4 PLCC Only (Note 11) PLCC Only
600
600
600
ps
850
850
850
ps
(Note 11) PLCC Only
1350
1350
1350
ps
(Note 11) PLCC Only
950
950
950
ps
(Note 11)
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100328
Industrial Version PLCC TTL-to-ECL DC Electrical Characteristics (Note 12)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -40C to +85C, VTTL = +4.5V to +5.5V TC = -40C TC = 0C to +85C Symbol Parameter Units Min Max Min Max VOH VOL Output HIGH Voltage Output LOW Voltage Cutoff Voltage -1900 VOHC VOLC VIH VIL IIH IIL VFCD IEE Output HIGH Voltage Corner Point HIGH Output LOW Voltage Corner Point LOW Input HIGH Voltage Input LOW Voltage Input HIGH Current Breakdown Test Input LOW Current Input Clamp Diode Voltage VEE Supply Current -159 -169 -70 -70 -159 -169 -75 -75 mA -700 -1.2 2.0 0 -1950 mV -1085 -1830 -870 -1575 -1025 -1830 -870 -1620 mV mV Conditions VIN = VIH(Max) or VIL(Min) Loading with 50 to -2V OE or DIR LOW, VIN= VIH(Max) or VIL(Min), Loading with 50 to -2V -1095 -1565 5.0 0.8 70 1.0 -700 -1.2 2.0 0 -1035 -1610 5.0 0.8 70 1.0 mV mV V V A mA A V VIN = VIH(Min) or VIL(Max) Loading with 50 to -2V Over VTTL, VEE, TC Range Over VTTL, VEE, TC Range VIN = +2.7V VIN = +5.5V VIN = +0.5V IIN = -18 mA LE LOW, OE and DIR HIGH Inputs OPEN VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V
PLCC ECL-to-TTL DC Electrical Characteristics (Note 12)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -40C to +85C, CL = 50 pF, VTTL = +4.5V to +5.5V TC = -40C TC = 0C to +85C Symbol Parameter Units Min Max Min Max VOH VOL VIH VIL IIH IIH IOZHT IOZLT IOS ITTL Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 3-STATE Current Output HIGH 3-STATE Current Output LOW Output Short-Circuit Current VTTL Supply Current -700 -150 -60 74 49 67 0.50 70 -700 -150 -60 74 49 67 mA -1170 -1830 2.7 2.4 0.5 -870 -1480 425 0.50 70 -1165 -1830 2.7 2.4 0.5 -870 -1475 350 V V mV mV A A A A mA Conditions
IOH = -3 mA, VTTL = 4.75V IOH = -3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIH (Max) VIN = VIH (Min) VOUT = +2.7V VOUT = +0.5V VOUT = 0.0V, VTTL = +5.5V TTL Outputs LOW TTL Outputs HIGH TTL Outputs in 3-STATE
Note 12: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
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100328
Industrial Version (Continued) PLCC TTL-to-ECL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V Symbol tPLH tPHL tPLH tPHL tPZH tPHZ tPHZ tSET tHOLD tPW(H) tTLH tTHL OE to En (Cutoff to HIGH) OE to En (HIGH to Cutoff) DIR to En (HIGH to Cutoff) Tn to LE Tn to LE Pulse Width LE Transition Time 20% to 80%, 80% to 20% Tn to En (Transparent) LE to En Parameter TC = -40C Min 1.0 1.7 1.2 1.5 1.6 2.5 1.0 2.5 0.4 2.3 Max 3.3 3.4 4.0 4.5 4.1 TC = 25C Min 1.1 1.7 1.5 1.6 1.6 1.0 1.0 2.0 0.6 1.6 Max 3.4 3.5 4.2 4.3 4.1 TC = 85C Min 1.1 1.9 1.7 1.6 1.7 1.0 1.0 2.0 0.6 1.6 Max 3.6 3.7 4.6 4.4 4.3 ns Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Units Conditions
ns ns ns ns ns ns ns ns
PLCC ECL-to-TTL AC Electrical Characteristics
VEE = -4.2V to -5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSET tHOLD tPW(H) OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En to LE En to LE Pulse Width LE En to Tn (Transparent) LE to Tn Parameter TC = 0C Min 2.3 3.1 3.4 3.7 3.2 3.0 2.7 2.8 2.5 2.3 4.0 Max 5.4 7.4 8.3 9.0 9.0 7.5 8.0 7.3 TC = 25C Min 2.4 3.1 3.7 4.0 3.3 3.4 2.8 3.1 1.0 2.0 4.0 Max 5.4 7.0 8.75 9.0 8.75 8.5 8.5 7.75 TC = 85C Min 2.6 3.3 4.0 4.3 3.5 4.1 3.1 4.0 1.0 2.5 4.0 Max 5.7 7.5 9.5 9.75 9.0 9.75 8.75 9.0 Units ns ns ns ns ns ns ns ns Conditions Figures 3, 4 Figures 3, 4 Figures 3, 5 Figures 3, 5 Figures 3, 5 Figures 3, 4 Figures 3, 4 Figures 3, 4
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100328
Test Circuitry (TTL-to-ECL)
Note: * * * * Rt = 50 termination. When an input or output is being monitored by a scope, Rt is supplied by the scope's 50 resistance. When an input or output is not being monitored, an external 50 resistance must be applied to serve as Rt. TTL and ECL force signals are brought to the DUT via 50 coax lines. VTTL is decoupled to ground with 0.1 F to ground, VEE is decoupled to ground with 0.01 F and VCC is connected to ground. For ECL input pins, the equivalent force/sense circuitry is optional.
FIGURE 1. TTL-to-ECL AC Test Circuit
Switching Waveforms (TTL-to-ECL)
FIGURE 2. TTL to ECL Transition--Propagation Delay and Transition Times
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100328
Test Circuitry (ECL-to-TTL)
Note: * * * * Rt = 50 termination. When an input or output is being monitored by a scope, Rt is supplied by the scope's 50 resistance. When an input or output is not being monitored, an external 50 resistance must be applied to serve as Rt. The TTL 3-State pull up switch is connected to +7V only for ZL and LZ tests. TTL and ECL force signals are brought to the DUT via 50 coax lines. VTTL is decoupled to ground with 0.1 F, VEE is decoupled to ground with 0.01 F and VCC is connected to ground.
FIGURE 3. ECL-to-TTL AC Test Circuit
Switching Waveforms (ECL-to-TTL)
Note: DIR is LOW, and OE is HIGH
FIGURE 4. ECL-to-TTL Transition--Propagation Delay and Transition Times
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100328
Switching Waveforms (ECL-to-TTL)
(Continued)
Note: DIR is LOW, LE is HIGH
FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times
Note: OE is HIGH, LE is HIGH
FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time
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100328
Applications
FIGURE 7. Applications Diagram--MOS/TTL SRAM Interface Using 100328 ECL-TTL Latched Translator
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100328
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E
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100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 14 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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