? 1999 fairchild semiconductor corporation ds010943 www.fairchildsemi.com october 1991 revised november 1999 100310 low skew 2:8 differential clock driver 100310 low skew 2:8 differential clock driver general description the 100310 is a low skew 8-bit differential clock driver which is designed to select between two separate differen- tial clock inputs. the low output to output skew ( < 50 ps) is maintained for either clock input. a low on the select pin (sel) selects clkina, clkina and a high on the sel pin selects the clkinb, clkinb inputs. the 100310 is ideal for those applications that need the ability to freely select between two clocks, or to maintain the ability to switch to an alternate or backup clock should a problem arise with the primary clock source. a v bb output is provided for single-ended operation. features low output to output skew differential inputs and outputs allows multiplexing between two clock inputs voltage compensated operating range: ? 4.2v to ? 5.7v available to industrial grade temperature range (plcc package only) ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. logic symbol pin descriptions connection diagram 28-pin plcc truth table order number package number package description 100310QC v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square 100310qi v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square industrial temperature range ( ? 40 c to + 85 c) pin names description clkin n , clkin n differential clock inputs sel select clk 0 ? 7 , clk 0 ? 8 differential clock outputs v bb v bb output nc no connect clkina clkina clkinb clkinb sel clk n clk n hlxxlhl lhxxllh xxhlhhl xxlhhlh
www.fairchildsemi.com 2 100310 absolute maximum ratings (note 1) recommended operating conditions note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: esd testing conforms to mil-std-883, method 3015. commercial version dc electrical characteristics (note 3) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd, t c = 0 c to + 85 c note 3: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under ? worst case ? conditions. storage temperature (t stg ) ? 65 c to + 150 c maximum junction temperature (t j ) + 150 c pin potential to ground pin (v ee ) ? 7.0v to + 0.5v input voltage (dc) v ee to + 0.5v output current (dc output high) ? 50 ma esd (note 2) 2000v case temperature (t c ) commercial 0 c to + 85 c industrial ? 40 c to + 85 c supply voltage (v ee ) ? 5.7v to ? 4.2v symbol parameter min typ max units conditions v oh output high voltage ? 1025 ? 955 ? 870 mv v in = v ih (max) loading with v ol output low voltage ? 1830 ? 1705 ? 1620 mv or v il (min) 50 ? to ? 2.0v v ohc output high voltage ? 1035 mv v in = v ih loading with v olc output low voltage ? 1610 mv or v il (max) 50 ? to ? 2.0v v bb output reference voltage ? 1380 ? 1320 ? 1260 mv i vbb = ? 250 a v diff input voltage differential 150 mv required for full output swing v cm common mode voltage v cc ? 2.0 v cc ? 0.5 v v ih input high voltage ? 1165 ? 870 mv guaranteed high signal for all inputs v il input low voltage ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.50 av in = v il (min) i ih input high current 240 av in = v ih (max) i cbo input leakage current ? 10 av in = v ee i ee power supply current ? 100 ? 40 ma inputs open
3 www.fairchildsemi.com 100310 commercial version (continued) ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 4: t ps describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair ? s low-to-high and high-to-low prop- agation delays. with differential signal pairs, a low-to-high or high-to-low transition is defined as the transition of the tru e output or input pin. note 5: t oslh describes in-phase gate-to-gate differential propagation skews with all differential outputs going low-to-high; t oshl describes the same con- ditions except with the outputs going high-to-low. note 6: t ost describes the maximum worst case difference in any of the t ps , t oslh or t ost delay paths combined. note 7: the skew specifications pertain to differential i/o paths. symbol parameter t c = 0 ct c = + 25 ct c = + 85 c units conditions min typ max min typ max min typ max f max max toggle frequency clkin a/b to q n 750 750 750 mhz sel to q n 575 575 575 mhz t plh propagation delay, t phl clkin n to clk n differential 0.80 0.90 1.00 0.82 0.92 1.02 0.89 1.01 1.09 ns figure 3 single-ended 0.80 0.96 1.20 0.82 0.98 1.22 0.89 1.06 1.29 t plh propagation delay, 0.75 0.99 1.20 0.80 1.02 1.25 0.85 1.10 1.35 ns figure 2 t phl sel to output t ps lh-hl skew 10 30 10 30 10 30 ps (note 4)(note 7) t oslh gate-gate skew lh 20 30 20 50 20 50 (note 5)(note 7) t oshl gate-gate skew hl 20 50 20 50 20 50 (note 5)(note 7) t ost gate-gate lh-hl skew 30 60 30 60 30 60 (note 6)(note 7) t s setup time 300 300 300 ps sel to clkin n t h setup time 000ps sel to clkin n t tlh transition time 275 510 750 275 500 750 275 480 750 ps figure 4 t thl 20% to 80%, 80% to 20%
www.fairchildsemi.com 4 100310 industrial version dc electrical characteristics (note 8) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 8: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under ? worst case ? conditions. ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 9: t ps describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's low-to-high and hi gh-to-low prop- agation delays. with differential signal pairs, a low-to-high or high-to-low transition is defined as the transition of the tru e output or input pin. note 10: t oslh describes in-phase gate-to-gate differential propagation skews with all differential outputs going low-to-high; t oshl describes the same conditions except with the outputs going high-to-low. note 11: t ost describes the maximum worst case difference in any of the t ps , t oslh or t ost delay paths combined. note 12: the skew specifications pertain to differential i/o paths. symbol parameter t c = ? 40 ct c = 0 c to + 85 c units conditions min max min max v oh output high voltage ? 1085 ? 870 ? 1025 ? 870 mv v in = v ih (max) loading with v ol output low voltage ? 1830 ? 1575 ? 1830 ? 1620 mv or v il (min) 50 ? to ? 2.0v v ohc output high voltage ? 1095 ? 1035 mv v in = v ih loading with v olc output low voltage ? 1565 ? 1610 mv or v il (min) 50 ? to ? 2.0v v bb output reference voltage ? 1395 ? 1255 ? 1380 ? 1260 mv i vbb = ? 250 a v diff input voltage differential 150 150 mv required for full output swing v cm common mode voltage v cc ? 2.0 v cc ? 0.5 v cc ? 2.0 v cc ? 0.5 v v ih input high voltage ? 1170 ? 870 ? 1165 ? 870 mv guaranteed high signal for all inputs v il input low voltage ? 1830 ? 1480 ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.50 0.50 av in = v il (min) i ih input high current 240 240 av in = v ih (max) i cbo input leakage current ? 10 ? 10 av in = v ee i ee power supply current ? 100 ? 40 ? 100 ? 40 ma inputs open symbol parameter t c = ? 40 ct c = + 25 ct c = + 85 c units conditions min typ max min typ max min typ max f max max toggle frequency clkin a/b to q n 750 750 750 mhz sel to q n 575 575 575 mhz t plh propagation delay, t phl clkin n , to clk n differential 0.78 0.88 0.98 0.82 0.92 1.02 0.89 1.01 1.09 ns figure 3 single-ended 0.78 0.95 1.18 0.82 0.98 1.22 0.89 1.06 1.29 t plh propagation delay 0.70 0.99 1.20 0.80 1.02 1.25 0.85 1.10 1.35 ns figure 2 t phl sel to output t ps lh-hl skew 10 30 10 30 10 30 (note 9)(note 12) t oslh gate-gate skew lh 20 50 20 50 20 50 ps (note 10)(note 12) t oshl gate-gate skew hl 20 50 20 50 20 50 (note 10)(note 12) t ost gate-gate lh-hl skew 30 60 30 60 30 60 (note 11)(note 12) t s setup time 300 300 300 ps sel to clkin n t h setup time 000ps sel to clkin n t tlh transition time 275 510 750 275 500 750 275 480 750 ps figure 4 t thl 20% to 80%, 80% to 20%
5 www.fairchildsemi.com 100310 test circuit note: shown for testing clkin to clk1 in the differential mode. l1, l2, l3 and l4 = equal length 50 ? impedance lines. all unused inputs and outputs are loaded with 50 ? in parallel with 3 pf to gnd. scope should have 50 ? input terminator internally. figure 1. ac test circuit switching waveforms figure 2. propagation delay, sel to outputs figure 3. propagation delay, clkin/clkin to outputs figure 4. transition times
www.fairchildsemi.com 6 100310 low skew 2:8 differential clock driver physical dimensions inches (millimeters) unless otherwise noted 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square package number v28a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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