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| T2801 DECT Single-Chip Transceiver Description The T2801 is an RF IC for low-power DECT applications. The HP-VFQFP-N48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closedloop modulation concept. No mechanical tuning is necessary in production. Electrostatic sensitive device. Observe precautions for handling. Features D Supply-voltage range 3 V to 4.6 V (unregulated) D Auxiliary-voltage regulator on-chip D Low current consumption D Few low cost external components D No mechanical tuning required D Non-blindslot and blindslot operation D Unlimited multislot operation with advanced closedloop modulation D Supports multiple reference clocks (10.368 MHz/ 13.824 MHz/ 20.736 MHz) D TX preamplifier with 0 dBm output power at 1.9 GHz and ramp-signal generator for SiGe power amplifier Block Diagram MIXER IF_IN OUT IR MIXER RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET RAMP GEN D/A RSSI VCO TX / RX SWITCH GF TX_DATA DEMOD DAC RSSI IF_TANK IF AMP 1 IF AMP 2 BB_OUT DEMOD TANK CF PC TX_OUT TX DRIVER VCO REG AUX REG f :n PD MCC 3-WIRE BUS CLOCK DATA ENABLE RX_ON TX_ON PU_RX/TX PU_PLL CP PU_VCO f :n RC CTRL LOGIC VREG_VCO VS_VCO VREG VS_REG VTUNE GND_VCO PU_REG REG_CTRL CP I_CPSW LD REF_CLK Figure 1. Block diagram Ordering Information Extended Type Number T2801-PLH Package HP-VFQFP-N48 Taped and reeled Remarks Rev. A9, 11-Dec-01 1 (27) Preliminary Information T2801 Functional Block Description Name AUX REG BBF CP DAC DEMOD GF IF AMP1 IF AMP2 IR MIXER MCC Description Auxiliary voltage regulator Baseband filter Charge pump D/A converter for demodulator tuning Demodulator Gaussian filter for transmit data 1st intermediate frequency amplifier 2nd intermediate frequency amplifier Image rejection mixer Modulation compensation circuit PC PD RAMP GEN RC RSSI TX/RX SWITCH VCO VCO REG Name Description Programmable counter Phase detector Ramp-signal generator Reference counter Received signal-strength indicator Switches VCO signal to IR MIXER resp. TX DRIVER Voltage-controlled oscillator Voltage regulator for VCO TX DRIVER Buffer amplifier for TX_OUT MIXER_OUT2 MIXER_OUT1 Pinning VS_MIXER PU_RX/TX TX_DATA GND_PLL PU_PULL PU_VCO I_CPSW 48 CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP 1 2 3 4 5 6 7 8 9 10 11 12 13 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI RAMP_SET RX_ON TX_ON T2801 31 30 29 28 27 26 25 14 15 16 17 18 19 20 21 22 23 24 VREG_VCO DAC_DEC VS_VCO GND_VCO REG_DEC DEMOD_TANK1 Figure 2. Pinning 2 (27) DEMOD_TANK2 BB_OUT VTUNE BB_CF GND1 CP Rev. A9, 11-Dec-01 Preliminary Information T2801 Pin Description Pin 1 Symbol CLOCK Function 3-wire-bus: Clock input VS_PLL Configuration 7 2 DATA 3-wire-bus: Data input CLOCK DATA ENABLE 1,2,3 123 5k 5k 3 ENABLE 3-wire-bus: Enable input GND_PLL 43 4 REF_CLK Reference-frequency input VS_PLL 7 10k 10k REF_CLK 4 GND_PLL 43 5 LD Lock-detect output 100 LD 5 GND_PLL 43 6 PU_REG Power-up input for aux. voltage regulator PU_REG 6 25k 25k GND_PLL 43 Rev. A9, 11-Dec-01 3 (27) Preliminary Information T2801 Pin Description (continued) Pin 7 Symbol VS_PLL Function PLL supply voltage VS_PLL Configuration 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_REG 10 8 VREG Aux. voltage-regulator output REG_CTRL 9 9 REG_CTRL Aux. voltage-regulator control output VREG 8 10 VS_REG Aux. voltage-regulator supply voltage GND_PLL 43 11 GND_CP Charge-pump ground VS_CP 12 12 VS_CP Charge-pump supply voltage CP 13 13 CP Charge-pump output GND_CP 11 4 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Pin Description (continued) Pin 14 Symbol VS_VCO Function VCO voltage-regulator supply voltage Configuration VS_VCO 14 15 VREG_VCO VCO voltage-regulator control output VREG_VCO VREG VCO 15 16 GND_VCO VCO ground GND_VCO 16 17 VTUNE VCO tuning voltage input VREG_VCO 15 VTUNE 17 GND_VCO 16 18 GND1 Ground VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 Rev. A9, 11-Dec-01 5 (27) Preliminary Information T2801 Pin Description (continued) Pin 19 Symbol Function VS_MIXER 42 10k 10k Configuration DEMOD_TANK1 Demodulator tank circuit DEMOD_ TANK1 19 DEMOD_ TANK2 20 20 DEMOD_TANK2 Demodulator tank circuit GND1 18 21 DAC_DEC Decoupling PIN for VCO_DAC VREG_VCO 15 10k DAC_DEC 21 400 GND_VCO 16 22 REG_DEC Decoupling PIN for VCO_REG VREG_VCO 15 2k REG_DEC 22 42k GND_VCO 16 23 BB_CF Baseband filter corner-frequency control input VS_IF 33 BB_CF 23 GND1 18 6 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Pin Description (continued) Pin 24 Symbol BB_OUT Function Baseband filter output VS_IF 33 Configuration BB_OUT 24 GND1 18 25 RSSI Received signal-strength indicator output VS_IF 33 RSSI 25 13k GND2 28 26 IF_TANK1 IF tank circuit VS_IF 33 IF_TANK1 26 IF_TANK2 27 27 IF_TANK2 IF tank circuit GND2 28 28 GND2 Ground VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 Rev. A9, 11-Dec-01 7 (27) Preliminary Information T2801 Pin Description (continued) Pin 29 Symbol RF_IN1 Function RF input of image reject mixer VS_MIXER 42 Configuration 30 RF_IN2 RF input of image reject mixer RF_IN1 RF IN1 29 RF_IN2 RF IN2 30 GND2 28 31 GND3 Ground VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 32 TX_OUT TX driver amplifier output for PA TX_OUT 32 GND3 31 8 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Pin Description (continued) Pin 33 Symbol VS_IF Function IF amplifier supply voltage VS_PLL Configuration 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 34 IF_IN1 IF input of IF amplifier VS_IF 33 35 IF_IN2 IF input of IF amplifier IF_IN1 IF IN1 34 4.3k IF_IN2 IF IN2 35 GND2 28 36 RAMP_OUT Ramp-generator output for PA power ramping VS_MIXER 42 RAMP_OUT 36 GND2 28 Rev. A9, 11-Dec-01 9 (27) Preliminary Information T2801 Pin Description (continued) Pin 37 Symbol RAMP_SET Function Slew-rate setting of ramping signal VS_MIXER 42 Configuration RAMP_SET 37 56 GND2 25 38 RX_ON RX control input VS_IF 33 39 TX_ON TX control input RX_ON TX_ON 38, 39 5k 5k GND1 18 40 MIXER_OUT1 Mixer output to SAW filter VS_MIXER 42 MIXER_ OUT1 40 270 270 MIXER_ OUT2 41 41 MIXER_OUT2 Mixer output to SAW filter GND2 28 10 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Pin Description (continued) Pin 42 Symbol VS_MIXER Function Mixer supply voltage VS_PLL Configuration 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 43 GND_PLL PLL ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 44 PU_VCO VCO power-up input VS_VCO 14 PU_VCO 44 5k 5k GND_VCO 16 45 PU_RX/TX RX/TX power-up input PU_RX/TX 45 25k 25k GND1 18 Rev. A9, 11-Dec-01 11 (27) Preliminary Information T2801 Pin Description (continued) Pin 46 Symbol PU_PLL Function PLL power-up input Configuration 20k 10k 140k 10k 10k PU_ PLL 46 25k 25k GND_ PLL 43 47 TX_DATA TX data input of Gaussian filter and modulation-compensation circuit VS_PLL 7 TX_DATA 47 5k 5k GND_PLL 43 48 I_CPSW Charge pump switch input controls charge pump current VS_PLL 7 I_CPSW 48 5k GND_PLL 43 12 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Functional Description Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 ([55 MHz) and finally to an integrated baseband filter BB. For demodulator tuning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the on-chip varicap diode. Synthesizer The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). An 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequencydivided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC. Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typical +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, provides a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. Rev. A9, 11-Dec-01 13 (27) Preliminary Information T2801 PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO ext. loop filter Phase frequency detector PD fPD = 3.456 MHz PA driver Charge pump VCO Divider by 2 Mixer VCO DAC GF_DATA Modulation compensation MCC Gaussian filter GF Controlled phase shifting Reference counter RC REF_CLK 10.368MHz 13.824MHz 20.736MHz SRC 3 4 6 6.912 MHz 1.152 Mbit/s PLL reference Frequency REF_CLK Baseband controller TX_DATA Figure 3. 14 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 1 LO frequencies Mode TX fIF/MHz Channel C9 C8 ... C1 C0 C10 C11 ... C29 C30 RX 110.592 C9 C8 ... C1 C0 C10 C11 ... C29 C30 RX 112.320 C9 C8 ... C1 C0 C10 C11 ... C29 C30 fANT/MHz 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 fVCO/MHz 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1771.200 1772.928 ... 1785.024 1786.752 1788.480 1790.208 ... 1821.312 1823.040 1769.472 1771.200 ... 1783.296 1785.024 1786.752 1788.480 ... 1819.584 1821.312 SMC 34 34 ... 34 34 34 34 ... 34 34 32 32 ... 32 32 32 32 ... 32 32 32 32 ... 32 32 32 32 ... 32 32 SSC 1 2 ... 9 10 11 12 ... 30 31 1 2 ... 9 10 11 12 ... 30 31 0 1 ... 8 9 10 11 ... 29 30 Formula TX: RX: fANT = fVCO = 1.728 MHz x (32 x SMC + SSC) fANT = 1.728 MHz x (32 x SMC + SSC) + fIF Rev. A9, 11-Dec-01 15 (27) Preliminary Information T2801 Control Signals Table 2 Signal I_CPSW PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON Data Word 1 Bit D10 Data Word 1 Bit D9 Table 3 Function Controls the charge pump current Activates AUX voltage regulator supplying the complete transceiver. Activates VCO voltage regulator which supplies only the VCO. Activates RX/TX switch. Activates PLL circuits: PC, PD, CP, RC Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER Activates TX circuits: TX-DRIVER, RAMP GEN. Starts RAMP SIGNAL at RAMP OUT. Activates GF in TX mode. Activates MCC in TX mode. Mode PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON BB filter Demodulator IF amplifiers and RSSI IR mixer RX switch TX switch TX driver Ramp generator Programmable counter Voltage-controlled oscillator Gaussian filter Phase detector / charge pump Modulation compensation circuit Reference counter Typ. current consumption / mA @ VS = 3.2 V TX Mode 1 1 1 1 0 1 OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON ON 54 RX Mode 1 1 1 1 1 0 ON ON ON ON ON OFF OFF OFF ON ON OFF ON OFF ON 85 RSSI Only 1 1 1 1 1 1 OFF OFF ON ON ON OFF OFF OFF ON ON OFF ON OFF ON 80 16 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. After enable returning to high condition the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses arrived during enable-low condition. During enable low condition the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Dataword 2 holds setup information, which is adjusted during production. Data Word 1 MSB Data bits D22 D21 D20 D19 D18 SC D17 D16 D15 D14 D13 VCOS D12 1 D11 1 D10 GF D9 MCC D8 D7 GFCS D6 D5 D4 D3 D2 D1 CPCS D0 LSB Address bit A0 1 VCODAC RC MC Data Word 2 E10 E9 E8 E7 E6 E5 E4 MCCS E3 E2 E1 TEST E0 A0 0 DEMODDAC Data Word 1 Programs PLL Settings With the Reference Counter bits D21 - D22 RC (Reference Counter) D22 0 0 D21 0 1 SRC 3 4 REF_CLK 10.368 MHz 13.824 MHz D20 0 0 0 ... 1 1 1 SMC 32 33 34 35 1 1 1 1 1 1 0 1 1 1 0 1 D19 0 0 0 SC (Swallow Counter) D18 0 0 0 D17 0 0 1 D16 0 1 0 SSC 0 1 2 ... 29 30 31 1 0 6 20.736 MHz With the Main Counter bits D14 - D15 MC (Main Counter) D15 0 0 1 1 D14 0 1 0 1 With the Swallow Counter bits D16 - D20 Rev. A9, 11-Dec-01 17 (27) Preliminary Information T2801 VCO Select (RX/TX VCO) With bit D13 Used to switch between RX/TX VCO D13 0 1 VCOS (VCO Select) RX-VCO TX-VCO D5 VCO_DAC Adjustment With bit D3 - D5 Used to pretune the VCO frequency in case of production tolerances of the device. Tuning voltage in locked condition should be around 1.8 V at room temperature. This gives margin for ambient temperature changes. Pretune DAC Voltage D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 fVCO/% -5 ... ... ... ... ... ... 5 0 0 0 0 1 1 1 1 Gaussian Filter on/off With bit D10 GF is used only in TX mode D10 0 1 GF (Gaussian Filter) OFF ON Modulation Compensation Circuit on/off With bit D9 MCC is used only in TX mode D9 0 1 MCC (Modulation Compensation Circuit) OFF ON CPCS Adjustment With bit D0 - D2 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. CPCS (Charge-Pump Current Settings) GFCS Adjustment With bit D6 - D8 Only in TX mode effective for setting the frequency deviation of the modulation GFCS (Gaussian Filter Settings) D8 0 0 0 0 1 1 1 1 D7 0 0 1 1 0 0 1 1 D6 0 1 0 1 0 1 0 1 GFCS 60% 70% 80% 90% 100% 110% 120% 130% D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 CPCS -4 -3 -2 -1 0 1 2 3 18 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Data Word 2 Programs DEMODDAC Adjustment With bits E6 - E10 Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of external components and the T2801. Demod DAC Voltage E10 0 0 0 1 1 1 E9 0 0 0 1 1 1 E8 0 0 0 1 1 1 E7 0 0 1 0 1 1 E6 0 1 0 1 0 1 fIFcenter % -5 ... ... ... ... ... 5 1 0 1 X 1 1 1 1 0 0 1 1 0 1 0 1 TEST Mode Settings With bit E0 - E2 and D11 In normal operation Lock detect output is used. All other settings are for test only. D11 E2 1 0 1 X 0 0 0 0 E1 0 0 1 1 E0 0 1 0 1 Signal at lock detect output Lock detect RC out PC out CP mode Active Active Active MCCTEST: Active RC out divided by 2048 Lock detect RC out PC out GFTEST: RC out divided by 2 High imp. High imp. High imp. High imp. MCCS Adjustment With bits E3 - E5 Only in TX mode effective. Adjusts the modulation compensation circuit for closed loop modulation. This adjustment is done with a test sequence of a long stream of ,1` - ,0`. The correct setting is achieved, if the modulation is not affected by the PLL. MCCS (Modulation Compensation Settings) E5 0 0 0 0 1 1 1 1 E4 0 0 1 1 0 0 1 1 E3 0 1 0 1 0 1 0 1 MCCS 60% 70% 80% 90% 100% 110% 120% 130% Rev. A9, 11-Dec-01 19 (27) Preliminary Information T2801 3-Wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TPER TL TS TC TH TT 16525 TEC Figure 4. Description Clock period Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to data Time between two protocols Symbol TPER TS TH TC TL TEC TT Min. Value 125 60 60 60 200 0 250 Unit ns ns ns ns ns ns ns TX DATA Timing RefCLK TX_DATA TS TH Set-up time TX DATA Hold time TX DATA TS TH 10 ns 10 ns TS and TH must be considered for both (falling and rising) edges of RefCLK when using REF_CLK = 10.368 MHz. Figure 5. TX DATA timing Absolute Maximum Ratings All voltages refer to GND Parameter Supply voltage regulator Supply voltage Logic input voltage Junction temperature Storage temperature Pin 10 Pins 7, 12, 14, 33 and 42 Pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 Symbol VS_REG VS VIN Tjmax Tstg -40 Min. 3.2 3.0 - 0.3 Max. 4.7 4.7 VS 150 150 Unit V V V _C _C Thermal Resistance Parameter Junction ambient Symbol RthJA Value t.b.d. Unit K/W 20 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Operating Range Parameter Supply voltage regulator Supply voltage Ambient temperature Pins 10 Pins 7, 12, 14, 33 and 42 Symbol VS_REG VS Tamb Min. 3.2 3.0 -25 Typ. 3.6 3.0 Max. 4.6 4.6 +85 Unit V V _C Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameter IR mixer Input impedance Input matching Image rejection ratio DSB noise figure Conversion gain Input interception point IF amplifier Input impedance Lower cut-off frequency Upper cut-off frequency Power gain Bandwidth of external tank circuit Noise figure RSSI RSSI sensitivity RSSI compression RSSI dynamic range RSSI resolution RSSI rise time RSSI fall time Quiescent output current Maximum output current Test Conditions / Pins Pins 29, 30, 40 and 41 Pins 29 and 30 Pins 29 and 30 Pins 40 and 41 Pins 40 and 41 Rload = 200 Pins 40 and 41 Pins 26, 27, 34 and 35 Pins 34 and 35 Symbol Zin VSWRin IRR NFDSB= NFSSB Gconv IIP3 Zin fl3dB fu3dB Gp BW3dB NF Pins 25, 34 and 35 at IF_IN1, IF_IN2 Pins 34 and 35 at IF_IN1, IF_IN2 Pins 34 and 35 Slope of the RSSI has to be steady Pin = 30 to 100 dBV, Pin 25 Pin = 100 to 30 dBV, Pin 25 @ Pin < 20 dBV at IF_IN1, IF_IN2 Pin 25 @ Pin = 100 dBV at IF_IN1, IF_IN2 Pin 25 Pmin Pmax DR Acc tr tf Iout Iout 200 90 130 85 10 9 20 100 80 2 1 1 30 150 Min. Typ. 50 <2:1 20 10 11 -10 400 Max. Unit dB dB dB dBm MHz MHz dB MHz dB dBV dBV dB dB s s A A Pins 26 and 27 Rev. A9, 11-Dec-01 21 (27) Preliminary Information T2801 Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameter Test Conditions / Pins Symbol CCRR S Min. Typ. 10 0.5 Max. Unit dB V/MHz FM demodulator, BB-Filter Pins 19, 20, 23 and 24 Co-channel rejection ratio @ Pin = -75 dBm at IR-mixer input Sensitivity Quality factor of external tank circuit approx. 20, fres = FIF/2, Pin 24 Amplitude of recovered Nominal deviation of signal signal 288 kHz, Pin 24 Corner frequency Pin 23: C = 68 pF Output voltage DC range Pin 24 DAC for FM demodulator (internally connected) DEMOD_DAC range (see bus protocol E6 ... E10) VCO RX-VCO frequency range VCOS = `0' Bit D13 TX-VCO frequency range VCOS = `1' Bit D13 Tuning gain Frequency control voltage Pin 17 range VCO_DAC range (see bus protocol D3 ... D5) PLL Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter External reference input AC coupled sinewave frequency Pin 4 External reference input voltage Scaling factor reference counter Charge pump Output current Output current Current scaling AC coupled sinewave Pin 4 A fc VoutDC DfIFcenter fvco fvco Gtune Vtune fvco,DAC SPSC SMC SSC fREF_CLK 1750 1860 1 450 680 Vs-1 5 1840 1950 40 0.4 5 32 / 33 32 / 33 / 34 / 35 0 31 10.368 13.824 20.736 50 3/4/6/8 250 2.8 mVss kHz V % MHz MHz MHz/V V % MHz MHz MHz mVRMS VREF_CLK SRC Pin 13 VCP = VVS_CP / 2, I_CPSW = `1' Pin 48 VCP = VVS_CP / 2, I_CPSW = `0' Pin 48 ICP = ICP_nom + CPCS * ICP_step (see bus protocol D0 ... D2) ICP_nom ICP_nom ICP_step 6.5 1.2 0.2 mA mA mA Leakage current IL 100 pA 22 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameter Test Conditions / Pins Symbol fTXFCLK GFFM_nom GFCS Min. Typ. 13.824 350 60 130 Max. Unit MHz kHz % Gaussian transmit filter (Gaussian shape BT = 0.5) Tx data filter clock 12 taps in filter Frequency deviation Frequency deviation scaling GFFM = GFFM_nom * GFCS (see bus protocol D6 ... D8) Modulation compensation circuit Oversampling Digital sum variation Current scaling factor (see bus protocol E3 ... E5) VCO switch and TX driver Pin 32 Power gain @ Pin = -40 dBm Output impedance Pin 32 Maximum output power Pin 32 Gain compression @ TX_RF_OUT, Pin 32 Output interception point Pin 32 Ramp generator Pins 36 and 37 Minimum output voltage According to RAMP_SET input Maximum output voltage According to RAMP_SET input Rise time Cramp = 270 pF at Pin 37 Fall time Cramp = 270 pF at Pin 37 Lock detect and test mode output Pin 5 Lock detect output, locked = `1', unlocked = `0' test mode output test modes (see bus protocol E0 ... E2) Leakage current VOH = 4.6 V Saturation voltage IOL = 0.5 mA Auxiliary regulator Pins 8, 9 and 10 Output voltage VSREG = 3 V Pin 8 Supply voltage rejection VPin10 = VDC + 0.1 Vpp fPin10 = 0.1 to 10 kHz CPin8 = 100 nF VCO regulator Pins 14, 15 and 12 Output voltage VSVCO = 3 V Pin 15 3-wire bus Clock OVS DSV MCCS Gp Zout Pmax P1dB OIP3 Vmin Vmax tr tf LD 6 60 30 100 3 1 10 0.2 1.95 5 5 85 130 % dB dBm dBm dBm V V s s 0 IL VSL VREG SVR 2.9 3.0 t.b.d. 5 0.4 3.1 A V V dB VREG_VCO fClock 2.6 2.7 2.8 6.912 V MHz Rev. A9, 11-Dec-01 23 (27) Preliminary Information T2801 Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameter Test Conditions / Pins Symbol Min. Typ. Max. Unit Logic input levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, I_CPSW) Pins 1, 2, 3, 38, 39, 44, 47 and 48 High input level = `1' ViH 1.5 Low input level = `0' ViL 0.5 High input current = `1' IiH -5 5 Low input current = `0' IiL -5 5 Standby control Pins 6, 45 and 46 Power up PU_REG = `1` Pin 6 VPU_REG PU_RX/TX = `1` Pin 45 VPU_RX/TX 2.0 PU_PLL = `1` Pin 46 VPU_PLL High input level Standby PU_REG = `0` PU_RX/TX = `0` PU_PLL = `0` Low input level Power up PU_REG = `1` PU_RX/TX = `1` PU_PLL = `1` High input current Standby PU_xxxx = `0' Low input current Settling time VS = 0 active operation Settling time standby active operation Settling time active operation standby Power supply Total supply current pp y VPU = 3 V VPU = 5.5 V VPU = 3 V VPU = 5.5 V Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF 0.7 V V A A V V Pin 6 Pin 45 Pin 46 IPU_REG IPU_RX/TX IPU_PLL 20 60 100 200 30 80 125 300 40 100 150 400 0.1 1 A A A A A A s s s mA mA mA mA A A Standby current Supply current CP VPU = 0 V Pin 6, VPU = 0.5 V Pins 45, 46 Switched from VS = 0 to VS = 3V Switched from PU = `0' to PU = `1' Switched from PU = `1' to standby Pins 7, 10, 12, 14, 33 and 42 RX RSSI only TX TX (MCC, GF active) PU_RX/TX = GND VVS_CP = 3 V, PLL in lock condition Pin 13 IPU,OFF tsoa tssa tsas IS IS IS IS IS ICP < 10 < 10 <2 85 82 54 58 1 1 10 24 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Application Circuit RAMP_OUT 33 pF 180 nH 100 nH SAW Filter TFS 112B 33 pF 18 pF 15 pF 68 pF RAMP_OUT 36 IF_IN2 35 IF_IN1 34 VS_IF 33 TX_OUT 32 GND3 31 RF_IN2 30 RF_IN1 29 GND2 28 IF_TANK2 27 IF_TANK1 26 RSSI 25 270 nH 15 pF 560 pF RX_ON TX_ON 37 38 39 40 41 42 43 44 45 46 47 48 RSSI TX_OUT RF_IN 1 CLOCK 2 DATA 3 ENABLE 4 REF_CLOCK 5 LD 6 PU_REG 7 VS_PLL 8 VREG 9 REG_CTRL 10 VS_REG 11 GND_CP 12 VS_CP PU_VCO PU_RX/TX PU_PLL TX_DATA I_CPSW RAMP_SET RX_ON TX_ON MIXER_OUT1 MIXER_OUT2 VS_MIXER GND_PLL PU_VCO PU_RX/TX PU_PLL TX_DATA I_CPSW T2801 BB_OUT BB_CF REG_DEC DAC_DEC DEMOD_TANK2 DEMOD_TANK1 GND1 VTUNE GND_VCO VREG_VCO VS_VCO CP 24 23 22 21 20 19 18 17 16 15 14 13 68 pF 2.2 nF 100 pF BB_OUT tbd tbd 22 nF 180 150 nF 56 pF 470 nF CLOCK DATA ENABLE REF_CLK LD PU_REG 220 pF 4.7 nF VCC BC808 or similar tantal tantal Figure 6. Application circuit Rev. A9, 11-Dec-01 25 (27) Preliminary Information T2801 Package Information 26 (27) Rev. A9, 11-Dec-01 Preliminary Information T2801 Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 8. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel products for any unintended or unauthorized application, the buyer shall indemnify Atmel against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 Rev. A9, 11-Dec-01 27 (27) Preliminary Information |
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