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Integrated Circuit Systems, Inc.
ICS9158-05
Advanced Information
Buffered Clock Generator for PentiumTM /TritonTM Systems
General Description
The ICS9158-05 is a low cost frequency generator designed specifically to clock Pentium systems using the Triton chip set. Three copies of the CPU clock are available at 50, 60, or 66.7 MHz. Five copies of the synchronous BUS clock run at half the CPU frequency. A 14.318 MHz REFCLK, 12 MHz, KEYBD, and 24 MHz FLOPPY clock are also provided. Each high drive output is capable of driving a 30pF load with better than 1V/ns typical slew and have a duty cycle of 505%. The synchronous outputs are skew controlled to within 250ps and CPU clocks lead BUS clocks by 2-5ns. Glitch-free start and stop of the CPU and BUS clocks is provided as well as a power-down mode with all clocks forced low and the internal oscillators and PLLs powered-down. Power-up time is less than 10ns. All frequency transitions are gradual and meet the Intel cycle-to-cycle timing specification for 486 and Pentium microprocessors.
Features
* * * * * * * * * * 3 CPU and 5 synchronous BUS clocks 50/60/66 MHz and glitch-free stop clock selections 250ps skew between all synchronous outputs Outputs drive up to 30pF load with 1V/ns slew 2-5ns early CPU clocks support Triton chip set Compatible with 486 and Pentium CPUs Consumes less than 10A in power-down mode On-chip loop filter components 3.0V - 5.5V supply range 24-pin SOIC package
Applications
* Ideal for RISC or CISC systems such as 486, Pentium, PowerPC,TM etc. requiring multiple CPU and synchronous BUS clocks.
Block Diagram
Pentium and Triton are trademarks of Intel Corporation. PowerPC is a trademark of Motorola Corporation
9158-05 Rev B 05/08/97
ADVANCE INFORMATION documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9158-05 Advanced Information
Pin Configuration Functionality
VDD = +5V10%, TA=0C to 70C unless otherwise stated
OE 1 1 1 1 1 0 PD# 1 1 1 1 0 X FS1 0 0 1 1 X X FS0 0 1 0 1 X X CPU Ratio 14/4xX1 14/3xX1 42/10xX1 (STOP) (PWR DOWN) X1,X2, REF (MHz) 14.318 14.318 14.318 14.318 Low CPU (0:2) (MHz) 50 66.7 60 Low *Low BUS (0:4) (MHz) 25 33.3 30 Low *Low Tristate
Tristate Tristate
24-Pin SOIC
PD# forces all outputs low and powers-down the oscillator and PLL circuitry, minimizing power consumption. In order to ensure glitch-free start and stop of the CPU and BUS clocks, PD# should be asserted after the CPU and BUS clocks have stopped, and be deasserted 10ms (maximum PLL lock time) prior to starting the clocks. OE 1 PD# 1 0 X FLOPPY (MHz) 24 Low Tristate DESCRIPTION 14.318 clock output. Crystal connection, which includes output crystal load capacitance. Crystal connection, which includes crystal load capacitance and feedback bias for a nominal 14.31818 MHz parallel-resonance 12pF crystal. Digital POWER SUPPLY. Digital GROUND. 12 MHz keyboard clock output. 24 MHz floppy disk clock output. BUS clock output. ANALOG GROUND. OUTPUT ENABLE. Tristates all outputs when low.* BUS clock output. Digital GROUND. CPU clock output. CPU clock output. Power-down input shuts off both PLL stages when low.* ANALOG power supply. CPU clock output. BUS clock output. Digital GROUND. Digital POWER SUPPLY. CPU clock output. BUS clock output. Clock frequency select #1.* Clock frequency select #0.* KEYBD (MHz) 12 Low Tristate
Pin Descriptions for ICS9158-05
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 PIN NAME REFCLK X2 X1 VDD GND KEYBD FLOPPY BUS0 AGND OE BUS1 GND CPU0 CPU1 PD# AVDD BUS2 BUS3 GND VDD CPU2 TYPE OUT OUT IN PWR PWR OUT OUT OUT PWR IN OUT PWR OUT OUT IN PWR OUT OUT PWR PWR OUT OUT IN IN
1 0
22 BUS4 23 FS1 24 FS0 * Input pin has internal pull-up to VDD.
2
ICS9158-05 Advanced Information
Absolute Maximum Ratings
AVDD, VDD referenced to GND . . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0C to +70C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +150C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 5V
VDD = +5V10%, TA =0C to 70C unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage1 Output Low Current Output High Current1 Supply Current Output Frequency Change over Supply and Temperature1 Short circuit current1 Pull-up resistor value1 Input Capacitance1 Load Capacitance1
1
SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IDD FD ISC RPU Ci CL
TEST CONDITIONS
MIN 2.0 -20 -5 2.4 45
TYP
MAX 0.8
UNITS V V A A V V mA mA mA % mA
VIN=0V (Pull-up) VIN=VDD IOL=20.0mA IOH=-30mA VOL=0.8V VOH=2.0V No load, 66 MHz With respect to typical frequency Each output clock Input pin Except X1, X2 Pins X1, X2
0.25 3.5 65 -55 67 0.002
5 0.4
-35 100 0.01
25
56 680 8 20
k pf pf
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS9158-05 Advanced Information
Electrical Characteristics (continued)
VDD = +5V10%, TA=0C to 70C unless otherwise stated
AC Characteristics
PARAMETER Output Rise time, 0.8 to 2.0V (Note 1) Rise time, 20% to 80% VDD (Note 1) Output Fall time, 2.0 to 0.8V1 Fall time, 80% to 20% VDD1 Duty cycle1 Jitter, one sigma1 Jitter, absolute Jitter, absolute Input Frequency Clock skew between CPU and 2XCPU outputs Frequency Transition Time1
SYMBOL tr tr tf tf dt tj1s tjab tjab fi Tsk tft
TEST CONDITIONS 30pf load 30pf load 30pf load 30pf load 30pf load As compared with clock period 25-66MHz clocks
MIN 45/55
TYP 1 2.5 0.5 1.5 48/52 0.5
MAX 1.5 3 1.5 2 55/45 2.0 5 250
UNITS ns ns ns ns % % % ps MHz
-5 -250
2
14.318 100 From 4 to 50 MHz 13 250 20
ps ms
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9158-05 Advanced Information
Electrical Characteristics at 3.3V
VDD = +3.3V10%, TA =0C to 70C unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage1 Output Low Current 1 Output High Current 1 Supply Current Output Frequency Change over Supply and Temperature1 Short Circuit Current 1 Pull-up Resistor Value 1 Input Capacitance 1 Load Capacitance1
SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IDD FD ISC RPU Ci CL
TEST CONDITIONS
MIN 2.0
TYP
MAX 0.8
UNITS V V A A V V mA mA mA % mA k pF pF
VIN=0V(Pull-up) VIN=VDD IOL=10mA IOH=-5mA VOL=0.2VDD VOH=0.7VDD No load, 66 MHz With respect to typical frequency Each output clock Input pin Except X1, X2 Pins X1, X2
AC Characteristics
-10 -5 0.1VDD 0.85VDD 20 30 -15 43 0.002 25 56 900 8 20 -10 65 0.01
PARAMETER Output Rise time, 0.8 to 2.0V1 Rise time, 20% to 80% VDD Output Fall time, 2.0 to 0.8V1 Fall time, 80% to 20% VDD1 Duty cycle1 Jitter, one sigma1 Jitter, absolute
1 1
SYMBOL tr tr tf tf dt tj1s tjab tjab fi Tsk tft
TEST CONDITIONS 30pF load 30pF 30pF 30pF 30pF load load load load
MIN 40/50
TYP 1 2.5 0.5 1.5 44/46 0.5 2 14.318 100
MAX 3.0 4.0 2.5 4.0 50/40 2.0 5 300
UNITS ns ns ns ns % % % ps MHz ps ms
As compared with clock period 25-66 MHz clocks
Jitter, absolute1 Input Frequency Clock skew window between CPU and 2XCPU outputs1 Frequency Transition time 1
250 20
From 4 to 50 MHz
13
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9158-05 Advanced Information
ICS9158-05 CPU Clock DecodingTable
(using 14.318 MHz input. All frequencies in MHz)
Frequency Transitions
A key feature of the ICS9158-05 is its ability to provide smooth, glitch-free frequency transitions on the CPU and BUS clocks when the frequency select pins are changed. The frequency transition rate does not violate the Intel 486 or Pentium specification of less than 0.1% frequency change per clock period.
VDD=5V10% or 3.3V10%, TEMP=0-70C
OE 1 1 1 1 1 0 PD# 1 1 1 1 0 X FS1 0 0 1 1 X X FS0 0 1 0 1 X X CPU Ratio 14/4xX1 14/3xX1 X1,X2, REF (MHz) 14.318 14.318 CPU (0:2) (MHz) 50 66.7 60 Low *Low Tristate BUS (0:4) (MHz) 25 33.3 30 Low *Low Tristate
42/10xX1 14.318 (STOP) 14.318 (PWR Low DOWN) Tristate
Using an Input Clock as a Reference
The ICS9158-05 is designed to accept a 14.318 MHz crystal as the input reference. With some external changes, it is possi-ble to use a crystal oscillator or other clock sources. Please see application note AAN04 for details on driving the ICS9158-05 with a clock.
PD# forces all outputs low and powers-down the oscillator and PLL circuitry, minimizing power consumption. In order to ensure glitch-free start and stop of the CPU and BUS clocks, PD# should be asserted after the CPU and BUS clocks have stopped, and be deasserted 10ms (maximum PLL lock time) prior to starting the clocks.
OE 1 1 0 PD# 1 0 X FLOPPY (MHz) 24 Low Tristate KEYBD (MHz) 12 Low Tristate
6
ICS9158-05 Advanced Information
24 Lead SOIC Ordering Information
ICS9158-05M
Example:
LEAD COUNT DIMENSION L
24L 0.604
ICS XXXX-PPP M
Package Type
M=SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device
7
ADVANCE INFORMATION documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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