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E2C0023-27-Y3 Semiconductor
Semiconductor MSC1218
GENERAL DESCRIPTION
This version: Nov. 1997 MSC1218 Previous version: Jul. 1996
63-Bit Triplex Controller/Driver with Digital Dimming Function
The MSC1218 is a Bi-CMOS driver for 1/3 duty vacuum fluorescent display tube. It contains a 64-bit shift register, a 63-bit latch, a 10-bit digital dimming circuit, and three grids. The MSC1218 has only three microcontroller interface signal lines: CS, D-IN, and CLOCK. The chip select function enables the D-IN and CLOCK lines to be shared with other peripheral circuits.
FEATURES
* Power supply Voltage : 8 to 18V (built-in 5V regulator for logic circuit) * Operating temperature : -40 to +85C * 21-segment driver outputs : IOH=-6mA at VOH=VDD-0.8V * 3-grid driver outputs : IOH=-16mA at VOH=VDD-0.8V * Built-in digital dimming circuit : 10-bit resolution * Built-in RC oscillation circuit : External R and C * Built-in Power-On-Reset circuit * Package: 32-pin plastic SSOP(SSOP32-P-430-1.00-K) (Product name: MSC1218GS-K)
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Semiconductor
MSC1218
BLOCK DIAGRAM
SEG21 VDD1 VDD2 5V REG. POR GND 21 63 CS Control Circuit DATA-IN CLOCK 64 63 59 58 43 42 63-bit Latch 63-bit data 49 48 64-bit Shift Register 10-bit data 10-bit Latch
SEG1 GRID3
GRID1
21-bit Segment Driver 5V POR 21 63 21-Segment Control 21 22 21 21 1 21-bit data 1
3-bit Grid Driver VDD=8 - 18V
VCC=5.0V (Regurator)
1
10-bit data OSC0 OSC1 OSC 10-bit Digital Diming
Timing Generator 64 bits=0: Digital Dimming Mode 64 bits=1: VF Data Input Mode
POR
INPUT AND OUTPUT CONFIGURATION
* Schematic Diagrams of Logic Portion Input * Schematic Diagrams of Driver Output Circuit Circuit
VDD (5V Reg.) VDD VDD
INPUT
OUTPUT
GND
GND
GND
GND
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Semiconductor
MSC1218
PIN CONFIGURATION (TOP VIEW)

SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 1 2 3 4 5 6 7 8 9 SEG10 SEG11 10 SEG12 11 SEG13 12 SEG14 13 SEG15 14 SEG16 15 SEG17 16 32-Pin Plastic SSOP
32 SEG 1 31 GRID1 30 GRID2 29 GRID3 28 VDD2 27 OSC0 26 OSC1 25 GND 24 DATA-IN 23 CLOCK 22 CS 21 VDD1 20 SEG21 19 SEG20 18 SEG19 17 SEG18
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Semiconductor
MSC1218
PIN DESCRIPTIONS
Pin 32, 1 - 20 29 - 31 24 23 27 26 22 21 28 25 Symbol SEG1 - 21 GRID1 - 3 D-IN CLOCK OSC0 OSC1 CS VDD1 VDD2 GND Type Decription O Output pins for segment signals for driving VF display tube (anode). O I I I O I -- -- Output pins for grid signals for driving VF display tube (grid). Serial data input pin (positive logic). Shift clock input pin. Serial data shifts at the rising edge of CLOCK. RC oscillator connecting pins. Oscillation frequency is 3.2MHz. Connect a resistor between the OSC1 and OSC0 pins and a capacitor between the OSC0 pin and the ground. Chip select input pin. Data transfer is inhibited when this pin is "H". Power supply pins. When using these pins, connect each of them to the power supply. Ground pin.
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Semiconductor
MSC1218
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Storage Temperature Power Dissipation Symbol VDD VIN TSTG PD Condition -- All input pins -- Ta = +85C Rating -0.3 to +20 -0.3 to +6.0 -65 to +150 400 Unit V V C mW
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage High Level Input Voltage (1) High Level Input Voltage (2) Low Level Input Voltage (1) Low Level Input Voltage (2) Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDD VIH1 VIH2 VIL1 VIL2 fC fOSC fFR Top Condition -- All inputs except OSC0 OSC0 All inputs except OSC0 OSC0 -- R = 4.7kW, C = 10pF fosc = 3.2MHz -- Min. 8 3.8 4.5 0 0 -- -- -- -40 Typ. -- -- -- -- -- -- 3.2 260 -- Max. 18 5.5 5.5 0.8 0.5 250 -- -- 85 Unit V V V V V kHz MHz Hz C
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MSC1218
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = -40 to +85C, VDD = 8 to 18V (Unless otherwise noted) ) Parameter High Level Input Voltage (1) (All inputs except OSC0) High Level Input Voltage (2) (All inputs except OSC0) Low Level Input Voltage (1) (OSC0) Low Level Input Voltage (2) (OSC0) High Level Input Current (All inputs) Low Level Input Current (All inputs) High Level Output Voltage (SEG1-20) High Level Output Voltage (GRID1-3) Low Level Output Voltage (1) (SEG1-20, GRID1-3) Low Level Output Voltage (2) (SEG1-20, GRID1-3) Low Level Output Voltage (3) (SEG1-20, GRID1-3) Current Consumption Symbol VIH1 VIH2 VIL1 VIL2 IIH IIL VOH1 VOH2 VOL1 VOL2 VOL3 VDD Condition -- External input only -- External input only VIH1 = 5.0V VIL = 0.0V VDD= 9.5V IOH1 = -6mA VDD= 9.5V IOH2 = -16mA VDD= 9.5V IOL1 = 500mA VDD= 9.5V IOL2 = 200mA VDD= 9.5V IOL3 = 2mA fOSC= 3.2MHz No load Min. 3.8 4.5 0.0 0.0 -5 -5 VDD-0.8 VDD-0.8 -- -- -- -- Max. 5.5 5.5 0.8 0.8 5 5 -- -- 2 1 0.3 10 Unit V V V V mA mA V V V V V V
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Semiconductor AC Characteristics
MSC1218
(Ta = -40 to +85C, VDD = 8 to 18V (Unless otherwise noted) ) Parameter Oscillation Frequency External Input Frequency to OSC0 Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Pulse Width CS Off Time CS Setup Time (CS - Clock) CS Hold Time (Clock - CS) CS-All Output Delay Time Slew Rate (All Drivers) Power - CS Time at Power-on Hold Time at Power-off Rise Time at Power-on Symbol fOSC fOSCI fC tCW tDS tDH tCSW tCSL tCSS tCSH tODS tR tPCS tPOF tPRZ Condition R=4.7kW, C=10pF External input only -- -- -- -- -- -- -- -- CI=100pF CI=100pF t=20% to 80% or 80% to 20% -- When mounted on the unit VDD = 0.0V When mounted on the unit Min. 2 2.7 -- 1.3 1 200 8 32 2 2 -- -- 300 5 -- Max. 4.4 3.7 250 -- -- -- -- -- -- -- 8 5 -- -- 100 Unit MHz MHz kHz ms ms ns ms ms ms ms ms ms ms ms ms
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MSC1218
TIMING DIAGRAM
1) Data Input Timing
tCSS CS fC CLOCK tDS DATA-IN VALID VALID tDH tCW tCW VALID VALID tCSW tCSH -3.8V -0.8V -3.8V -0.8V tCSL -3.8V -0.8V
2)
CS
Data Output Timing
tCSW tODS tODS tR -3.8V -0.8V -80% -20%
SEG1-21, GRID1-3
tR
tR
3)
VDD CS
Power-on Timing
tPRZ tPCS tPOF -80%VDD -0.0V -3.8V -0.8V
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Semiconductor
MSC1218
FUNCTIONAL DESCRIPTION
l Power-on Reset The built-in Power-on-Reset (POR) circuit initializes the internal circuits when power is applied. The following condition is established after POR. 1) Contents of the shift register and latches are "0". 2) Duty cycle of digital dimming is set to "0". 3) All the outputs are OFF. l Function Mode The function mode is selected according to the output of the last bit of the shift register. The function modes are as follows.
M0 (Last bit) 0 1 Function Digital dimming data input mode Display data input mode
l Digital Dimming Data Input When M0="0", the digital dimming data input mode is selected and the input data length is 16 bits. The digital dimming data input is valid only when the low level is applied to the CS pin. The digital dimming data that was input to DATA-IN is input into the shift register at the rising edge of the CLOCK. Data is automatically loaded to the latches from the shift register at the rising edge of CS. The digital dimming data consists of 10 bits. The output duty varies from 0/1024 (0%) to 1016/1624 (99%) for each grid. The 10-bit digital dimming data should be input starting with the LSB. [Data Configuration] Digital dimming data input mode Input data: 16bits Digital dimming data: 10 bits Mode selector: 1 bit
16 M0 15 * 14 * 13 * 12 * 11 * 10
MSB
9
8 D8
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
LSB
BIT (First In) INPUT DATA
D10 D9
MODE DATA (MSB) 0 0 0 0 0 0 0 0
DIMMING DATA INPUT DATA 0 0 0 0 0 0 0 0 0 0 (LSB) DUTY CYCLE 0 1 0/1024 1/1024
1
1
1
1
1
1
1
0
0
0
1016/1024
1
1
1
1
1
1
1
1
1
1
1016/1024
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Semiconductor [Input Configuration] l Dimming data
BYTE 1 2 B7 D8 M0 B6 D7 * B5 D6 * B4 D5 * B3 D7 * B2 D3 * B1 D2 B0 D1
MSC1218
D10 D9
l Display Data Input When M0="1", the display data input mode is selected and the input data length is 16 bits. The display data input is valid only when the low level is applied to the CS pin. The display data that was input to DATA-IN is input into the shift register at the rising edge of CLOCK. The data is automatically loaded to the latched from the shift register at the rising edge of CS. [Data Configuration] Display data input mode Input data: Display data: Mode selector:
64bits 63 bits 1 bit
64
63
62
61
33
32
31
30
4 D4
3 D3
2 D2
1 D1
BIT (First In) INPUT DATA
M0 D63 D62 D61 MODE DATA
D33 D32 D31 D30 DISPLAY DATA
[Input Configuration] Display data
BYTE 1 2 3 4 5 6 7 8 B7 D8 B6 D7 B5 D6 B4 D5 B3 D7 B2 D3 B1 D2 B0 D1
D16 D15 D14 D13 D12 D11 D10 D9 D24 D23 D22 D21 D20 D19 D18 D17 D32 D31 D30 D29 D28 D27 D26 D25 D40 D39 D38 D37 D36 D35 D34 D33 D48 D47 D46 D45 D44 D43 D42 D41 D56 D55 D54 D53 D52 D51 D50 D49 D64 D63 D62 D61 D60 D59 D58 D57
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Semiconductor [Configuration of Segment output and Shift Register]
Segment SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 GRID GRID GRID 1 2 3 D1 D22 D43 D2 D23 D44 D3 D24 D45 D4 D25 D46 D5 D26 D47 D6 D27 D48 D7 D28 D49 Segment SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 GRID GRID GRID 1 2 3 D8 D29 D50 D9 D30 D51 D10 D31 D52 D11 D32 D53 D12 D33 D54 D13 D34 D55 D14 D35 D56 Segment SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 GRID GRID GRID 1 2 3 D15 D36 D57 D16 D37 D58 D17 D38 D59 D18 D39 D60 D19 D40 D61 D20 D41 D62 D21 D42 D63
MSC1218
Output Timing
GRID1 GRID2 GRID3 GRID1-21
*1bit time=4fOSC
3072bit times (1 display cycle) VDD -GND -VDD GND -VDD 3bit times 5bit times 8bit times GND VDD -GND
1019bit times
1024bit times
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MSC1218
PACKAGE DIMENSIONS
(Unit : mm)
SSOP32-P-430-1.00-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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