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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Bus Transceivers and D Flip-Flops High-Performance Silicon-Gate CMOS The MC54/74HC646 is identical in pinout to the LS646. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These devices are bus transceivers with D flip-flops. Depending on the status of the Data-Source Selection pins, data may be routed to the outputs either from the flip-flops or transmitted real-time from the inputs (see Function Table and Application Information). The Output Enable and the Direction pins control the transceiver's function. Bus A and Bus B cannot be routed as outputs to each other simultaneously, but can be routed as inputs to the A and B flip-flops. Also, the A and B flip-flops can be routed as outputs to Bus A and Bus B. Additionally, when either or both of the ports are in the high-impedance state, these I/O pins may be used as inputs to the D flip-flops for data storage. The user should note that because the clocks are not gated with the Direction and Output Enable pins, data at the A and B ports may be clocked into the storage flip-flops at any time. * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 780 FETs or 195 Equivalent Gates MC54/74HC646 24 1 J SUFFIX CERAMIC PACKAGE CASE 758-02 24 1 N SUFFIX PLASTIC PACKAGE CASE 724-03 24 1 DW SUFFIX SOIC PACKAGE CASE 751E-04 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXDW Ceramic Plastic SOIC PIN ASSIGNMENT A-TO-B CLOCK A-TO-B SOURCE DIRECTION A0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC B-TO-A CLOCK B-TO-A SOURCE OUTPUT ENABLE B0 B1 B2 B3 B4 B5 B6 B7 LOGIC DIAGRAM 4 5 6 7 8 9 10 11 21 3 1 23 2 22 PIN 24 = VCC PIN 12 = GND 20 19 18 17 16 15 14 13 A1 A2 A DATA PORT A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 A3 A4 B DATA PORT A5 A6 A7 GND OUTPUT ENABLE DIRECTION FLIP-FLOP CLOCKS DATA SOURCE SELECTION INPUTS A-TO-B CLOCK B-TO-A CLOCK A-TO-B SOURCE B-TO-A SOURCE 10/95 (c) Motorola, Inc. 1995 3-1 REV 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I I III I I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) RECOMMENDED OPERATING CONDITIONS MC54/74HC646 Symbol Vin, Vout Symbol Symbol VCC VI/O Tstg ICC II/O VCC Vin PD TL VOH tr, tf Iin VOL TA VIH VIL Iin Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package DC Supply Current, VCC and GND Pins DC I/O Current, per Pin DC Input Current, per Pin DC I/O Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Input Rise and Fall Time (Figure 1) Operating Temperature, All Package Types DC Input Voltage, Output Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Maximum Input Leakage Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter Parameter Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 20 A Vin = VCC or GND (Pins 1, 2, 3, 21, 22, and 23) Vin = VIH or VIL |Iout| |Iout| Vin = VIH or VIL |Iout| |Iout| Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v v VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Test Conditions - 0.5 to VCC + 0.5 - 1.5 to VCC + 1.5 3-2 - 65 to + 150 - 0.5 to + 7.0 - 55 Min 2.0 Value v 6.0 mA v 7.8 mA v 6.0 mA v 7.8 mA 0 0 0 0 75 35 20 260 300 750 500 + 125 1000 500 400 VCC Max 6.0 VCC V 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Unit Unit mW mA mA mA _C _C _C ns V V V V V - 55 to 25_C 0.1 1.5 3.15 4.2 0.26 0.26 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 v 1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 v Unit A V V V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol ICC IOZ Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current Parameter Vin = VCC or GND Iout = 0 A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND, I/O Pins Test Conditions 3-3 VCC V 6.0 6.0 - 55 to 25_C 0.5 8 5.0 80 10 160 v 85_C v 125_C MC54/74HC646 MOTOROLA Unit A A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) MOTOROLA TIMING REQUIREMENTS (Input tr = tf = 6 ns) MC54/74HC646 Symbol Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL tPZL, tPZH tPLZ, tPHZ fmax CPD Cout tr, tf Cin tsu tw th Power Dissipation Capacitance (Per Channel)* Maximum Input Rise and Fall Times (Figure 1) Minimum Pulse Width, A-to-B Clock (or B-to-A Clock) (Figures 3 and 4) Minimum Hold Time, A-to-B Clock to Input A (or B-to-A Clock to Input B) (Figures 3 and 4) Minimum Setup Time, Input A to A-to-B Clock (or Input B to B-to-A Clock) (Figures 3 and 4) Maximum Three-State Output Capacitance (Output in High-Impedance State) Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 9) Maximum Propagation Delay, Direction or Output Enable to Output A or B (Figures 7, 8 and 10) Maximum Propagation Delay, Output Enable to Output A or B (Figures 7, 8 and 10) Maximum Propagation Delay, A-to-B Source to Output B (or B-to-A Source to Output A) (Figures 5, 6 and 9) Maximum Propagation Delay, A-to-B Clock to Output B (or B-to-A Clock to Output A) (Figures 3, 4 and 9) Maximum Propagation Delay, Input A to Output B (or Input B to Output A) (Figures 1, 2 and 9) Maximum Clock Frequency (50% Duty Cycle) (Figures 3, 4 and 9) Parameter Parameter 3-4 VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- -- - 55 to 25_C - 55 to 25_C 1000 500 400 100 20 17 175 35 30 175 35 30 170 34 29 220 44 37 170 34 29 6.0 30 35 80 16 14 15 10 60 12 10 5 5 5 Typical @ 25C, VCC = 5.0 V Guaranteed Limit Guaranteed Limit v 85_C v 125_C v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 1000 500 400 100 20 17 125 25 21 220 44 37 220 44 37 215 43 37 275 55 47 215 43 37 4.8 24 28 15 10 75 15 13 60 5 5 5 1000 500 400 120 24 20 150 30 26 265 53 45 265 53 45 255 51 43 330 66 56 255 51 43 4.0 20 24 15 10 90 18 15 5 5 5 MHz Unit Unit pF pF pF ns ns ns ns ns ns ns ns ns ns MC54/74HC646 FUNCTION TABLE -- HC646 Control Inputs Output Enable H Direc- tion X H, L, H, L, X X A-to-B Clock B-to-A Clock A-to-B Source B-to-A Source Data Port Status A Input: X L H X X Input: B Input: X X X L H Output: Storage Flip- Flop States QA no change L H X X QB no change X X L H Description of Operation The output functions of the A and B ports are disabled The ports may be used as inputs to the storage flip-flops. Data at the inputs are clocked into the flip-flops with the rising edge of the Clocks. The output mode of the B data port is enabled and behaves according to the following logic equation: B = [A * (A-to-B Source)] + [QA * (A-to-B Source)] X L H X H, L, X* L X L H L H no change no change no change no change 1.) When A-to-B Source is low, the data at the A data port are displayed at the B data port. The states of the storage flip-flops are not affected. 2.) When A-to-B Source is high, the states of the A storage flip-flops are displayed at the B data port. 3.) When A-to-B Source is low, the data at the A data port are clocked into the A storage flip-flops by a rising-edge signal on the A-to-B Clock. 4.) When A-to-B Source is high, the data at the A data port are clocked into the A storage flip-flops by a rising-edge signal on the A-to-B Clock. The states, QA, of the storage flip-flops propagate directly to the B data port. H X X QA no change no change X* L X L H L H L H no change no change H X L H QA QA L H no change no change L L Output: Input: The output mode of the A data port is enabled and behaves according to the following logic equation: A = [B * (B-to-A Source)] + [QB * (B-to-A Source)] no change no change no change no change 1.) When B-to-A Source is low, the data at the B data port are displayed at the A data port. The states of the storage flip-flops are not affected. 2.) When B-to-A Source is high, the states of the B storage flip-flops are displayed at the A data port. 3.) When B-to-A Source is low, the data at the B data port are clocked into the B storage flip-flops by a rising-edge signal on the B-to-A Clock. 4.) When B-to-A Source is high, the data at the B data port are clocked into the B storage flip-flops by a rising-edge signal on the B-to-A Clock. The states, QB, of the storage flip-flops propagate directly to the A data port. X* H, L, X L L H L H X H QB X no change no change X* X L L H L H no change no change L H X H QB QB L H no change no change L H * The clocks are not internally gated with either the Output Enables or the Source inputs. Therefore, data at the A and B ports may be clocked into the storage flip-flops at any time. High-Speed CMOS Logic Data DL129 -- Rev 6 3-5 MOTOROLA MC54/74HC646 TYPICAL APPLICATIONS BUS A A FLIP- FLOPS B FLIP- FLOPS BUS B BUS A A FLIP- FLOPS B FLIP- FLOPS BUS B CONTROL LOGIC CONTROL LOGIC (3) CONTROL PINS (21) (1) (23) (2) (22) (3) DIRECTION H (21) OUTPUT ENABLE L (1) A-TO-B CLOCK X (23) (2) (22) DIRECTION OUTPUT A-TO-B B-TO-A ENABLE CLOCK CLOCK X H CONTROL A-TO-B B-TO-A PINS SOURCE SOURCE X X B-TO-A A-TO-B B-TO-A CLOCK SOURCE SOURCE X L X Data Storage From A and/or B Bus Real-Time Transfer From Bus A to Bus B BUS A A FLIP- FLOPS B FLIP- FLOPS BUS B CONTROL LOGIC (3) CONTROL PINS DIRECTION L (21) OUTPUT ENABLE L (1) (23) (2) (22) A-TO-B B-TO-A CLOCK CLOCK X X A-TO-B B-TO-A SOURCE SOURCE X L Real-Time Transfer From Bus B to Bus A MOTOROLA 3-6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC646 TIMING DIAGRAMS AND SWITCHING DIAGRAMS -- HC646 VCC OUTPUT ENABLE GND VCC GND VCC A-TO-B SOURCE GND VCC B-TO-A SOURCE GND tr A DATA PORT 90% 50% 10% tPLH 90% 50% 10% tTLH tPHL tf VCC GND DIRECTION B DATA PORT tTHL Figure 1. A Data Port = Input, B Data Port = Output VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC B-TO-A SOURCE GND VCC A-TO-B SOURCE GND tr B DATA PORT 90% 50% 10% tPLH A DATA PORT 50% tPHL tf VCC GND Figure 2. A Data Port = Output, B Data Port = Input NOTE: = Don't Care State High-Speed CMOS Logic Data DL129 -- Rev 6 3-7 MOTOROLA MC54/74HC646 VCC OUTPUT ENABLE GND VCC DIRECTION GND B-TO-A SOURCE VCC GND VCC A-TO-B SOURCE GND VCC B-TO-A CLOCK GND VCC A DATA PORT 50% tsu th A-TO-B CLOCK tPLH B DATA PORT 50% 50% tw 1/fmax tPHL GND GND VCC Figure 3. A Data Port = Input, B Data Port = Output VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC A-TO-B SOURCE GND B-TO-A SOURCE VCC GND VCC A-TO-B CLOCK GND VCC B DATA PORT 50% tsu th B-TO-A CLOCK tPLH A DATA PORT 50% 50% tw 1/fmax tPHL GND GND VCC Figure 4. B Data Port = Input, A Data Port = Output MOTOROLA 3-8 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC646 VCC OUTPUT ENABLE GND VCC DIRECTION GND INTERNAL QA (FLIP-FLOP A) VCC GND VCC GND VCC 50% GND VCC GND VCC tPLH tPHL 3 B DATA PORT 1 50% 2 tPLH tPHL GND INTERNAL QB (FLIP-FLOP B) A-TO-B SOURCE B-TO-A SOURCE A DATA PORT NOTES: 1. B Data Port (output) changes from the level of the storage flip-flop, QA, to the level of A Data Port (input). 2. B Data Port (output) changes from the level of the A Data Port (input) to the level of the storage flip-flop, QA. 3. The A storage flip-flop, A-to-B Source, and A Data Port (input) have simultaneously changed states. Figure 5. A Data Port = Input, B Data Port = Output High-Speed CMOS Logic Data DL129 -- Rev 6 3-9 MOTOROLA MC54/74HC646 VCC OUTPUT ENABLE GND VCC GND VCC GND VCC GND VCC GND DIRECTION INTERNAL QA (FLIP-FLOP A) INTERNAL QB (FLIP-FLOP B) A-TO-B SOURCE B-TO-A SOURCE tPLH VCC 50% GND tPHL 50% 1 2 VCC GND 3 tPLH tPHL A DATA PORT B DATA PORT NOTES: 1. A Data Port (output) changes from the level of the storage flip-flop, QB, to the level of B Data Port (input). 2. A Data Port (output) changes from the level of the B Data Port (input) to the level of the storage flip-flop, QB. 3. The B storage flip-flop, B-to-A Source, and B Data Port (input) have simultaneously changed states for the purpose of this 3. example. A Data Port (output) is now displaying the voltage level of B Data Port (input). Figure 6. A Data Port = Output, B Data Port = Input PIN DESCRIPTIONS INPUTS/OUTPUTS A0 - A7 (Pins 4 - 11) and B0 - B7 (Pins 20 - 13) A and B data ports. These pins may function either as inputs to or outputs from the transceivers. CONTROL INPUTS Output Enable (Pin 21) Active-low output enable. When this pin is low, the outputs are enabled and function normally. When this pin is high, the A and B data ports are in high-impedance states. See the Function Table. Direction (Pin 3) Data direction control. When the Output Enable pin is low, this control pin determines the direction of data flow. When Direction is high, the A data ports are inputs and the B data ports are outputs. When Direction is low, the A data ports are outputs and the B data ports are inputs. A-to-B Clock, B-to-A Clock (Pins 1, 23) Clocks for the internal D flip-flops. With a low-to-high transition on the appropriate Clock pin, data on the A (or B) inputs are clocked into the internal A (or B) flip-flops. These clocks are not internally gated with the Output Enable or the Direction pins, therefore data at the A and B pins may be clocked into the storage flip-flops at any time. A-to-B Source, B-to-A Source (Pins 2, 22) Data-source selection pins. Depending upon the states of these pins (see the Function Table), data at the outputs may come either from the inputs or from the D flip-flops. MOTOROLA 3-10 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC646 VCC OUTPUT ENABLE GND VCC DIRECTION 50% GND tPHZ 90% DATA PORT A tPLZ DATA PORT A 10% tPZH DATA PORT B 50% tPZL DATA PORT B 50% tPZH VOH 50% HIGH IMPEDANCE tPZL HIGH IMPEDANCE 50% VOL tPHZ 90% tPLZ HIGH IMPEDANCE 10% VOL VOH HIGH IMPEDANCE DATA PORT A = INPUT DATA PORT B = OUTPUT DATA PORT A = OUTPUT DATA PORT B = INPUT Figure 7. VCC OUTPUT ENABLE 50% GND tPZL OUTPUT A OR B 50% tPZH OUTPUT A OR B 50% tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE Figure 8. TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* CL* * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 9. Test Circuit Figure 10. Test Circuit High-Speed CMOS Logic Data DL129 -- Rev 6 3-11 MOTOROLA MC54/74HC646 LOGIC DETAIL D C C Q HC648 VCC A Q HC646 HC646 HC648 CAB CAB SAB 20 B0 TAB A0 4 VCC TAB Q HC648 D B HC646 Q C C HC646 HC648 SBA CBA CBA TBA TBA A1 A2 A3 A4 A5 A6 A7 5 6 7 8 9 10 11 19 18 17 16 15 14 13 B1 B2 B3 B4 B5 B6 B7 TBA 3 21 TBA SBA SAB 22 2 B-TO-A SOURCE A-TO-B SOURCE DIRECTION OUTPUT ENABLE CBA CBA CAB 23 B-TO-A CLOCK TAB TAB CAB 1 A-TO-B CLOCK MOTOROLA 3-12 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC646 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 758-02 ISSUE A B 24 13 NOTES: 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. 5. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. DIM A B C D F G J K L N P INCHES MIN MAX 1.240 1.285 0.285 0.305 0.160 0.200 0.015 0.021 0.045 0.062 0.100 BSC 0.008 0.013 0.100 0.165 0.300 0.310 0.020 0.050 0.360 0.400 MILLIMETERS MIN MAX 31.50 32.64 7.24 7.75 4.07 5.08 0.38 0.53 1.14 1.57 2.54 BSC 0.20 0.33 2.54 4.19 7.62 7.87 0.51 1.27 9.14 10.16 L P 1 12 -A- J N C K G F D 24 PL 0.25 (0.010) M -T- SEATING PLANE TA M -A- 24 1 13 N SUFFIX PLASTIC PACKAGE CASE 724-03 ISSUE D NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. -B- 12 C -T- SEATING PLANE L K E G F D 24 PL NOTE 1 N J 0.25 (0.010) TA 24 PL M 0.25 (0.010) M M M TB M DIM A B C D E F G J K L M N INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 High-Speed CMOS Logic Data DL129 -- Rev 6 3-13 MOTOROLA MC54/74HC646 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E -A- 24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 -B- 12X P 0.010 (0.25) M B M 1 12 24X D 0.010 (0.25) M J TA S B S F R C -T- SEATING PLANE X 45 _ M 22X G K DIM A B C D F G J K M P R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 3-14 *MC54/74HC646/D* MC54/74HC646/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
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