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CMOS STATIC RAM 64K (8K x 8-BIT)
Integrated Device Technology, Inc.
IDT7164S IDT7164L
FEATURES:
* High-speed address/chip select access time -- Military: 20/25/30/35/45/55/70/85ns (max.) -- Commercial: 15/20/25/35/70ns (max.) * Low power consumption * Battery backup operation -- 2V data retention voltage (L Version only) * Produced with advanced CMOS high-performance technology * Inputs and outputs directly TTL-compatible * Three-state outputs * Available in: -- 28-pin DIP and SOJ * Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Address access times as fast as 15ns are available and the circuit offers a reduced power standby mode. When CS1 goes HIGH or CS2 goes LOW, the circuit will automatically go to, and remain in, a low-power stand by mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ; and 28-pin 600 mil DIP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0 V CC ADDRESS DECODER A12 65,536 BIT MEMORY ARRAY GND
0
7
I/O
0
I/O CONTROL
I/O 7
CS 1
CS 2
OE WE
CONTROL LOGIC
2967 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1996
2967/8
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IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
NC A 12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
V CC CS2 A8 A9 A 11
WE
TRUTH TABLE(1,2,3)
D28-1 D28-3 P28-1 P28-2 SO28-5
WE CS CS1
X X X X H H L H X
CS2 X L
OE
X X X X H L X
I/O High-Z High-Z High-Z High-Z High-Z DataIN
Function Deselected - Standby (ISB) Deselected - Standby (ISB) Deselected -Standby (ISB1) Deselected -Standby (ISB1) Output Disabled Write Data
2967 tbl 02
OE
A 10
CS1
I/O7 I/O6 I/O5 I/O4 I/O3
VHC VHC or VLC X L L L VLC H H H
DataOUT Read Data
DIP/SOJ TOP VIEW
2967 drw 02
NOTES: 1. CS2 will power-down CS1, but CS1 will not power-down CS2. 2. H = VIH, L = VIL, X = don't care. 3. VLC = 0.2V, VHC = VCC - 0.2V
PIN DESCRIPTIONS
Name A0-A12 I/O0-I/O7 Description Address Data Input/Output Chip Select Chip Select Write Enable Output Enable Ground Power
2967 tbl 01
CS1 WE OE
CS2
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Commercial Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5V 10% 5V 10%
2967 tbl 04
GND VCC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM
(2)
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Com'l. -0.5 to +7.0
Mil. -0.5 to +7.0
Unit V
TA TBIAS TSTG PT IOUT
0 to +70 -55 to +125 -55 to +125 1.0 50
-55 to +125 -65 to +135 -65 to +150 1.0 50
C C C W mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input HIGH Voltage Input LOW Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 -- Max. 5.5 0 0.8 Unit V V V
-- VCC + 0.5 V
NOTES: 2967 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
NOTE: 2967 tbl 05 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
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IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 8 Unit pF pF
NOTE: 2967 tbl 06 1. This parameter is determined by device characterization, but is not production tested.
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S15 7164L15 Symbol ICC1 Parameter Operating Power Supply Current, CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = 0(3) Dynamic Operating Current CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = fMAX(3) Standby Power Supply Current (TTL Level), CS1 VIH or CS2 VIL VCC = Max., Outputs Open, f = fMAX(3) Full Standby Power Supply Current (CMOS Level), f = 0(3), VCC = Max. 1. CS1 VHC and CS2 VHC, or 2. CS2 VLC Power Com'l. Mil. S L S L S L S L 110 100 180 150 20 3 15 0.2 -- -- -- -- -- -- -- -- 7164S20 7164L20 Com'l. 100 90 170 150 20 3 15 0.2 Mil. 110 100 180 160 20 5 20 1 7164S25 7164L25 Com'l. 90 80 170 150 20 3 15 0.2 Mil. 110 100 180 160 20 5 20 1 7164S30 7164L30 Com'l. -- -- -- -- -- -- -- -- Mil. 100 90 170 150 20 5 20 1 mA mA mA Unit mA
ICC2
ISB
ISB1
DC ELECTRICAL CHARACTERISTICS(1) (Continued)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S35 7164L35 Symbol ICC1 Parameter Operating Power Supply Current, CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = 0(3) Dynamic Operating Current CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = fMAX(3) Standby Power Supply Current (TTL Level), CS1 VIH, or CS2 VIL VCC = Max., Outputs Open, f = fMAX(3) Full Standby Power Supply Current (CMOS Level), f = 0(3), VCC = Max. 1. CS1 VHC and CS2 VHC, or 2. CS2 VLC Power Com'l. Mil. S L S L S L S L 90 80 150 130 20 3 15 0.2 100 90 160 140 20 5 20 1 7164S45 7164L45 Com'l. -- -- -- -- -- -- -- -- Mil. 100 90 160 130 20 5 20 1 7164S55 7164L55 Com'l. -- -- -- -- -- -- -- -- Mil. 100 90 160 125 20 5 20 1 7164S70(2)/85(4) 7164L70(2)/85(4) Com'l. 90 80 150 130 20 3 15 0.2 Mil. 100 90 160 120 20 5 20 1
2967 tbl 07
Unit mA
ICC2
mA
ISB
mA
ISB1
mA
NOTES: 1. All values are maximum guaranteed values. 2. 70 ns available in both military and commercial devices. 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 4. Also available: 100ns military devices.
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IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%)
IDT7164S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS1 = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. VOH Output High Voltage IOH = -4mA, VCC = Min. -- 2.4 MIL. COM'L. MIL. COM'L. Min. -- -- -- -- Max. 10 5 10 5 0.4 0.5 -- IDT7164L Min. -- -- -- -- -- -- 2.4 Max. 5 2 5 2 0.4 0.5 -- V
2967 tbl 08
Unit A A V
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ. (1) VCC @ Symbol VDR ICCDR tCDR(3) tR(3) |ILI|
(3)
Max. VCC @ 2.0V -- 200 60 -- -- 2 3.0V -- 300 90 -- -- 2 Unit V A ns ns A
2967 tbl 09
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Input Leakage Current
Test Condition -- MIL. COM'L. 1. CS1 VHC CS2 VHC, or 2. CS2 VLC
Min. 2.0 -- -- 0 tRC(2) --
2.0v -- 10 10 -- -- --
3.0V -- 15 15 -- -- --
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2967 tbl 10
5V 480 DATA OUT 255 30pF*
5V 480 DATA OUT 255 5pF*
2967 drw 03
2967 drw 04
Figure 1. AC Test Load
Figure 2. AC Test Load (for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances
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IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
7164S15(1) 7164L15(1) Symbol Read Cycle tRC tAA tACS1 tACS2
(3) (3) (4)
7164S20 7164L20 Min. Max.
7164S25 7164L25 Min. Max.
7164S30(2) 7164L30 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select-1 Access Tim Chip Select-2 Access Time Chip Select-1, 2 to Output in Low-Z Output Enable to Output Valid Output Enable to Output in Low-Z
(4)
15 -- -- -- 5 -- 0 -- -- 5 0 --
-- 15 15 20 -- 7 -- 8 7 -- -- 15
20 -- -- -- 5 -- 0 -- -- 5 0 --
-- 19 20 25 -- 8 -- 9 8 -- -- 20
25 -- -- -- 5 -- 0 -- -- 5 0 --
-- 25 25 30 -- 12 -- 13 10 -- -- 25
30 -- -- -- 5 -- 0 -- -- 5 0 --
-- 29 30 35 -- 15 -- 13 12 -- -- 30
ns ns ns ns ns ns ns ns ns ns ns ns
tCLZ1,2 tOE tOLZ(4)
tCHZ1,2 tOHZ tOH tPU tPD
(4) (4) (4)
Chip Select-1, 2 to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power Up Time Chip Deselect to Power Down Time
Write Cycle tWC tCW1, 2 tAW tAS tWP tWR1 tWR2 tWHZ tDW tDH1 tDH2 tOW
(4) (4)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time (CS1, WE) Write Recovery Time (CS2) Write Enable to Output in High-Z Data to Write Time Overlap Data Hold from Write Time (CS1, WE) Data Hold from Write Time (CS2) Output Active from End-of-Write
15 14 14 0 14 0 5 -- 8 0 5 4
-- -- -- -- -- -- -- 6 -- -- -- --
20 15 15 0 15 0 5 -- 10 0 5 4
-- -- -- -- -- -- -- 8 -- -- -- --
25 18 18 0 21 0 5 -- 13 0 5 4
-- -- -- -- -- -- -- 10 -- -- -- --
30 22 22 0 23 0 5 -- 13 0 5 4
-- -- -- -- -- -- -- 12 -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns
2967 tbl 11
NOTES: 1. 0 to +70C temperature range only. 2. -55C to +125C temperature range only. Also available: 100ns military devices. 3. Both chip selects must be active for the device to be selected. 4. This parameter is guaranteed by device characterization, but is not production tested.
6.1
5
IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Continued) (VCC = 5.0V 10%, All Temperature Ranges)
7164S35 7164L35 Symbol Read Cycle tRC tAA tACS1 tACS2
(3) (3) (4)
7164S45(2) 7164L45(2) Min. Max.
7164S55(2) 7164L55(2) Min. Max.
7164S70/85(2) 7164L70/85(2) Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select-1 Access Time Chip Select-2 Access Time Chip Select-1, 2 to Output in Low-Z Output Enable to Output Valid
(4) (4)
35 -- -- -- 5 -- 0 -- -- 5 0 --
-- 35 35 40 -- 18 -- 15 15 -- -- 35
45 -- -- -- 5 -- 0 -- -- 5 0 --
-- 45 45 45 -- 25 -- 20 20 -- -- 45
55 -- -- -- 5 -- 0 -- -- 5 0 --
-- 55 55 55 -- 30 -- 25 25 -- -- 55
70/85 -- -- -- 5 -- 0 -- -- 5 0 --
-- 70/85 70/85 70/85 -- 35/40 -- 30/35 30/35 -- -- 70/85
ns ns ns ns ns ns ns ns ns ns ns ns
tCLZ1,2 tOE tOLZ
Output Enable to Output in Low-Z Chip Select-1, 2 to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power Up Time Chip Deselect to Power Down Time
tCHZ1,2 tOHZ tOH tPU tPD
(4) (4) (4)
Write Cycle tWC tCW1, 2 tAW tAS tWP tWR1 tWR2 tWHZ tDW tDH1 tDH2 tOW
(4) (4)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time (CS1, WE) Write Recovery Time (CS2) Write Enable to Output in High-Z Data to Write Time Overlap Data Hold from Write Time (CS1, WE) Data Hold from Write Time (CS2) Output Active from End-of-Write
35 25 25 0 25 0 5 -- 15 0 5 4
-- -- -- -- -- -- -- 14 -- -- -- --
45 33 33 0 25 0 5 -- 20 0 5 4
-- -- -- -- -- -- -- 18 -- -- -- --
55 50 50 0 50 0 5 -- 25 0 5 4
-- -- -- -- -- -- -- 25 -- -- -- --
70/85 60/75 60/75 0 60/75 0 5 -- 30/35 0 5 4
-- -- -- -- -- -- -- 30/35 -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns
2967 tbl 11
NOTES: 1. 0 to +70C temperature range only. 2. -55C to +125C temperature range only. Also available: 100ns military devices. 3. Both chip selects must be active for the device to be selected. 4. This parameter is guaranteed by device characterization, but is not production tested.
6.1
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IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA tOH
OE
tOE tOLZ (5) CS2 tACS2 tCLZ2 (5) tCHZ2
(5)
CS1
tACS1 tCLZ1 DATA OUT
(5)
tOHZ (5) (5) tCHZ1 DATA VALID
2967 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
tRC ADDRESS tAA tOH DATA OUT DATA VALID
2967 drw 06
tOH
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
CS1
CS2 tACS2 tCLZ2 (5) tACS1 tCLZ1 (5) DATA OUT ICC POWER SUPPLY CURRENT ISB
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
tCHZ2 tCHZ1 DATA VALID
(5) (5)
tPU
tPD
2967 drw 07
6.1
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IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 6) WE
tWC ADDRESS
CS2
CS1
tAW tAS tWR1(3)
WE
(4)
tWP
(6)
tOW(7)
DATA OUT tWHZ (7) DATA IN tDW DATA VALID
2967 drw 08
tDH1, 2
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2) CS
tWC ADDRESS tAS CS2 tCW tWR1
(3)
tWR2
(3)
CS1
(5)
tAW
WE
tDW DATA IN tDH1,2
DATA VALID
2967 drw 09
NOTES: 1. WE, CS1 or CS2 must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2. 3. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals must not be applied. 5. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified tWP. 7. Transition is measured 200mV from steady state.
6.1
8
IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE V CC tCDR 4.5V V DR 2V V IH V IH
2967 drw 10
4.5V tR
CS
V DR
ORDERING INFORMATION
IDT 7164 Device Type X Power XX Speed XXX Package X Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B
Y TD D P TP
300 mil 300 mil 600 mil 600 mil 300 mil
SOJ (SO28-5) CERDIP (D28-3) CERDIP (D28-1) Plastic DIP (P28-1) Plastic DIP (P28-2)
15 20 25 30 35 45 55 70 85 S L
Commercial Only Military Only Speed in nanoseconds Military Only Military Only Military Only Standard Power Low Power
2967 drw 11
6.1
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