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June 2000
(R)
AS7C4098 AS7C34098
5V/3.3V 256K x 16 CMOS SRAM
Features
* AS7C4098 (5V version) * AS7C34098 (3.3V version) * Industrial and commercial temperature * Organization: 262,144 words x 16 bits * Center power and ground pins * High speed
- 10/12/15/20 ns address access time - 5/6/7/9 ns output enable access time
* Low power consumption: STANDBY
- 110 mW (AS7C4098)/max CMOS - 72 mW (AS7C34098)/max CMOS
* Individual byte read/write controls * 2.0V data retention * Easy memory expansion with CE, OE inputs * TTL- and CMOS-compatible, three-state I/O * 44-pin JEDEC standard packages * ESD protection 2000 volts * Latch-up current 200 mA
- 400-mil SOJ - 400-mil TSOP II
* Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns - 468 mW (AS7C34098)/max @ 12 ns
Logic block diagram
A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1-I/O8 I/O9-I/O16 WE Row Decoder VCC 1024 x 256 x 16 Array (4,194,304) GND
Pin arrangement
44-pin SOJ, TSOP II (400 mil) A0 A1 A2 A3 A4 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10
I/O buffer
Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17
UB OE LB CE
Selection guide
AS7C34098 -10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C4098 AS7C34098 AS7C4098 AS7C34098 10 5 - 160 - 20 AS7C4098 AS7C34098 -12 12 6 250 130 20 20 AS7C4098 AS7C34098 -15 15 7 220 110 20 20 AS7C4098 AS7C34098 -20 20 9 180 100 20 20 Unit ns ns mA mA mA mA
Shaded areas indicate preliminary information.
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Copyright (c)2000 Alliance Semiconductor. All rights reserved.
AS7C4098 AS7C34098
(R)
Functional description
The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices organized as 262,144 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t AA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/9 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 110 mW power consumption in CMOS standby mode. Both devices offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1-I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable ( OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1-I/O8, and UB controls the higher bits, I/O9-I/O16. All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V (AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP II packages.
Absolute maximum ratings
Parameter Voltage on V CC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with V CC applied DC current into outputs (low) Device AS7C4098 AS7C34098 Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 -0.50 - -65 -55 - Max +7.0 +5.0 VCC +0.50 1.5 +150 +125 20 Unit V V V W
C C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE H L L L WE X H X H OE X H X L LB X X H L H L L L L X H L
Key: X = Don't care, L = Low, H = High.
UB X X H H L L H L L
I/O1-I/O8 High Z High Z DOUT High Z DOUT DIN High Z DIN
I/O9-I/O16 High Z High Z High Z DOUT DOUT High Z DIN DIN
Mode Standby (I SB, ISB1) Output disable (I CC)
Read (ICC)
Write (ICC)
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AS7C4098 AS7C34098
Recommended operating conditions
Parameter AS7C4098 Supply voltage AS7C34098 AS7C34098 AS7C4098 Input voltage commercial industrial AS7C34098 Symbol VCC (10/12/15/20) VCC (-10) VCC (10/12/15/20) VIH VIH VIL Ambient operating temperature TA TA Min 4.5 3.15 3.0 2.2 2.0 -0.5* 0 -40 Typical 5.0 3.3 3.3 - - - - - Max 5.5 3.6 3.6 VCC + 0.5 VCC + 0.5 0.8 70 85 Unit V V V V V V
C C
* VIL min = -3.0V for pulse width less than t RC/2.
DC operating characteristics (over the operating range)
-10 Parameter Input leakage current Symbol |ILI| Test conditions VCC = Max VIN = GND to VCC VCC = Max CE = VIH or OE = VIH or WE = VIL VI/O = GND to VCC VCC = Max Min cycle, 100% duty CE = VIL, IOUT = 0mA VCC = Max CE = VIH, f = Max VCC = Max CE VCC - 0.2V, V IN VCC , - 0.2V or VIN 0.2V f = 0 IOL = 8 mA, V CC = Min IOH = -4 mA, VCC = Min AS7C4098 AS7C34098 AS7C4098 AS7C34098 AS7C4098 AS7C34098 -12 -15 -20 Min Max Min Max Min Max Min Max Unit - 1 - 1 - 1 - 1 A
Output leakage |ILO| current Operating power supply current
- - - - - - - - 2.4
1 - 160 - 60 - 20 0.4 -
- - - - - - - - 2.4
1 250 130 60 60 20 20 0.4 -
- - - - - - - - 2.4
1 220 110 60 60 20 20 0.4 -
- - - - - - - - 2.4
1
A
180 mA 100 mA 60 60 20 20 0.4 - mA mA mA mA V V
ICC ISB
Standby power supply current ISB1 Output voltage VOL VOH
Shaded areas indicate preliminary information.
Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE, UB, LB I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 6 8 Unit pF pF
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AS7C4098 AS7C34098
(R)
Read cycle (over the operating range)
-10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE Low to output in low Z CE High to output in higfch Z OE Low to output in low Z OE High to output in high Z LB, UB access time LB, UB Low to output in low Z LB, UB High to output in high Z Power up time Power down time
Shaded areas indicate preliminary information.
-12 Max - 10 10 5 - - 5 - 5 5 - 5 - 10 Min 12 - - - 3 3 - 0 - - 0 - 0 - Max - 12 12 6 - - 6 - 6 6 - 6 - 12 15 - - - 3 0 - 0 - - 0 - 0 -
-15 Min Max - 15 15 7 - - 7 - 7 7 - 7 - 15 20 - - - 3 0 - 0 - - 0 - 0 -
-20 Min Max - 20 20 9 - - 9 - 9 9 - 9 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 5 4, 5 4, 5 4, 5 4, 5 Notes
Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tBA tBLZ tBHZ tPU tPD
Min 10 - - - 3 0 - 0 - - 0 - 0 -
Key to switching waveforms
Rising input Falling input Undefined/don't care
Read waveform 1 (address controlled)
tRC Address tOH Data OUT Previous data valid tAA Data valid tOH
Read waveform 2 (CE, OE, UB, LB controlled)
tRC Address tAA OE tOE tOLZ CE tACE tLZ LB, UB tBLZ DataOUT tBA Data valid tBHZ tCHZ tOHZ tOH
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AS7C4098 AS7C34098
Write cycle (over the operating range)
-10 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width (OE = High) Write pulse width (OE = Low) Address hold from end of write Data valid to write end Data hold time Write enable to output in High-Z Output active from write end Byte enable Low to write end
Shaded areas indicate prelimin ary information.
-12 Min 12 8 8 0 8 12 0 6 - 5 - - 0 0 3 8 - 6 - - Max - - - - - - - Min 15 10 10 0 10 15 0 7 0 0 3 10 - - - - - - -
-15 Max - - - - - - - - - 7 - - Min 20 12 12 0 12 20 0 9 0 0 3 12
-20 Max - - - - - - - - - 9 - - Unit ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 4, 5 Note
Symbol tWC tCW tAW tAS tWP1 tWP2 tAH tDW tDH tWZ tOW tBW
Min 10 7 7 0 7 10 0 5 0 0 3 7
Max
Write waveform 1(WE controlled)
tWC Address tCW CE tBW LB, UB tAS WE tDW DataIN DataOUT Data undefined tWZ Data valid tOW High Z tDH tAW tWP tAH
Write waveform 2 (CE controlled)
tWC Address tAS CE tCW tAW tBW LB, UB tWP WE tDW Data IN DataOUT tCLZ High Z tWZ Data undefined Data valid tOW High Z tDH tAH
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AS7C4098 AS7C34098
(R)
Write waveform 3
tWC Address tAS CE tAW tBW LB, UB WE Data IN Data OUT High Z tWZ Data undefined tWP tDW Data valid tDH High Z tCW tAH
Data retention characteristics
Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR |ILI| Test conditions VCC = 2.0V CE VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V
Data retention mode VCC CE VCC tCDR VIH VDR VIH 168W VDR 2.0V VCC tR
Min 2.0 - 0 tRC -
Max - 500 - - 1
Unit V A ns ns A
Data retention waveform
AC test conditions
Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V.
+3.0V GND 90% 10% 2 ns Figure A: Input pulse 90% 10% Thevenin equivalent: DOUT +5V 480W DOUT 255W C(14) DOUT 350W +1.728V (5V and 3.3V) +3.3V 320W C(14)
GND Figure B: 5V Output load
GND Figure C: 3.3V Output load
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 14 During V CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. 2V data retention applies to commercial temperature range operation only. C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
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AS7C4098 AS7C34098
Typical DC and AC characteristics
Normalized supply current ICC, ISB vs. supply voltage VCC 1.4 1.2 Normalized ICC, ISB 1.0 0.8 0.6 0.4 0.2 0.0 MIN NOMINAL Supply voltage (V) Normalized access time tAA vs. supply voltage VCC MAX ISB Normalized ICC, ISB ICC 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 -10 35 80 125 Ambient temperature (C) Normalized access time tAA vs. ambient temperature T a ISB ICC Normalized supply current ICC, ISB vs. ambient temperature T a Normalized ISB1 (log scale) 625 25 5 1 0.2 0.04 -55 -10 35 80 125 Ambient temperature (C) Normalized supply current ISB1 vs. ambient temperature Ta
VCC = VCC(NOMINAL)
1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 MIN
1.5 1.4 Normalized access time
1.4 1.2
Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC
Ta = 25 C
1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 125 Ambient temperature (C) Output sink current IOL vs. output voltage VOL
Normalized ICC
1.3
VCC = V CC(NOMINAL)
1.0 0.8 0.6 0.4 0.2 0.0 0
VCC = VCC(NOMINAL) Ta = 25 C
NOMINAL Supply voltage (V) Output source current I OH vs. output voltage VOH
MAX
25 50 75 Cycle frequency (MHz)
100
Typical access time change tAA vs. output capacitive loading 35 30 Change in tAA (ns) VCC = V CC(NOMINAL)
140 Output source current (mA) 120 100 80 60 40 20 0 0
140 Output sink current (mA) 120 100 80 60 40 20 0 VCC 0
VCC = V CC(NOMINAL)PL Ta = 25 C
VCC = VCC(NOMINAL) Ta = 25 C
25 20 15 10 5 0
VCC Output voltage (V)
0
Output voltage (V)
250 500 750 Capacitance (pF)
1000
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AS7C4098 AS7C34098
(R)
Package dimensions
44 434241403938373635343332313029282726252423 c
44-pin TSOP II
e He
1 2 3 4 5 6 7 8 9 101112131415161718 19202122 d A2 A1 b e 44-pin SOJ Pin 1 B A A1 b Seating Plane E2 A2 c E D l 0-5
A
A A1 A2 b c d e He E l
44-pin TSOP II Min (mm) Max (mm) 1.2 0.05 0.95 1.05 0.25 0.45 0.15 (typical) 20.85 21.05 10.06 10.26 11.56 11.96 0.80 (typical) 0.40 0.60 44-pin SOJ 400 mil Min Max 0.128 0.148 0.025 1.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.120 1.130 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM
E1 E2
A A1 A2 B b c D E E1 E2 e
Ordering codes
Package Version 5V commercial SOJ 5V industrial 3.3V commercial 3.3V industrial 5V commercial TSOP II 5V industrial 3.3V commercial 3.3V industrial
NA: not available.
10 ns NA NA AS7C34098-10JC NA NA NA AS7C34098-10TC NA
12 ns AS7C4098-12JC AS7C4098-12JI AS7C34098-12JC AS7C34098-12JI AS7C4098-12TC AS7C4098-12TI AS7C34098-12TC AS7C34098-12TI
15 ns AS7C4098-15JC AS7C4098-15JI AS7C34098-15JC AS7C34098-15JI AS7C4098-15TC AS7C4098-15TI AS7C34098-15TC AS7C34098-15TI
20 ns AS7C4098-20JC AS7C4098-20JI AS7C34098-20JC AS7C34098-20JI AS7C4098-20TC AS7C4098-20TI AS7C34098-20TC AS7C34098-20TI
Part numbering system
AS7C SRAM prefix X Blank: 5V CMOS 3: 3.3V CMOS 4098 Device number -XX Access time J, T Packages: J: SOJ 400 mil T: TSOP II 400 mil X Temperature ranges: C: Commercial, 0C to 70C I: Industrial, -40C to 85C
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