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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78P014
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD78P014 is a member of the PD78014 subseries of 78K/0 series products. It uses a one-time-programmable (OTP) ROM or EPROM instead of the mask ROM of the PD78014. Because the PD78P014 can be programmed by users, it is ideally suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and timeto-market of a new product. Detailed information about product features and specifications can be found in the following document. Please make sure to read this document before starting design.
PD78014, 78014Y Series User's Manual : IEU-1343
FEATURES
* Pin compatible with mask ROM versions (except VPP pin) * Internal PROM: 32K bytesNote * PD78P014DW : Reprogrammable (ideal for system evaluation)
* PD78P014CW, 78P014GC-AB8 : Programmable once only (ideal for small-scale production) * Internal high-speed RAM: 1024 bytesNote * Buffer RAM: 32 bytes * Operable over same supply voltage range as mask ROM version (2.7 to 6.0 V) * Available for the QTOPTM microcomputer Note The internal PROM and internal high-speed RAM size can be set by means of the memory size switching register. Remark The QTOP microcomputer is the general term for a single-chip microcomputer with on-chip one-time PROM. NEC supports its program writing, marking, screening, and verification. Differences from mask ROM versions are as follows: * The same memory mapping as on a mask ROM version is possible by setting the memory size switching register. * There is no function for incorporating pull-up resistors by means of a mask option in P60 to P63 pins.
ORDERING INFORMATION
Part No. Package 64-pin plastic shrink DIP (750 mil) 64-pin ceramic shrink DIP (with window) (750 mil) 64-pin plastic QFP (14 x 14 mm) Internal ROM One-time PROM EPROM One-time PROM
PD78P014CW PD78P014DW PD78P014GC-AB8
In this document, the common parts of the one-time PROM version and EPROM version are represented by PROM.
The information in this document is subject to change without notice. Document No. IC-3098C (O. D. No. IC-8111C) Date Published January 1995 P Printed in Japan The mark 5 shows revised points.
(c)
1992
PD78P014
5
78K/0 SERIES DEVELOPMENT
PD78078Y Subseries PD78064Y Subseries PD78064 Subseries
100-pin package LCD controller/driver, UART added 16-bit timer/event counter function enhanced
PD78078 Subseries
100-pin package 8-bit timer/event counter added External expansion function enhanced
Products in Volume Production Products under Development Y subseries are products compatible with I C bus.
2
PD78098 Subseries PD78054Y Subseries PD78054 Subseries
80-pin package UART, D/A converter, real-time output port added 16-bit timer/event counter function enhanced 80-pin package IEBusTM controller added
PD78083 Subseries
42/44-pin package UART, A/D converter, 8-bit timer/event counter function
PD78014Y Subseries PD78014 Subseries
64-pin package A/D converter, 16-bit timer/event counter, SIO with automatic transmission/ reception function added Multiply/divide instructions added
PD78018FY Subseries PD78018F Subseries
64-pin package Capable of low voltage and high-speed operation
PD780208 Subseries PD78044A Subseries PD78024 Subseries PD78002Y Subseries PD78002 Subseries
64-pin package 64-pin package A/D converter, 16-bit timer/event counter, FIPTM controller/driver, multiply/divide instructions added 100-pin package FIP controller/driver function enhanced
PD78044 Subseries
80-pin package Automatic transmission/reception function added 6-bit up/down counter added FIP controller/driver function enhanced
2
PD78P014
OUTLINE OF FUNCTION
Item Internal memory * PROM * RAM Internal high-speed RAM : 1024 bytesNote Buffer RAM Memory space General registers Instruction cycle Main system clock selected Subsystem clock selected Instruction set 64K bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip instruction execution time cycle modification function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 10.0 MHz operation) 122 s (at 32.768 kHz operation) * 16-bit operation * Multiply/divide (8 bits x 8 bits,16 bits / 8 bits) * Bit manipulate (set, reset, test, Boolean operation) * BCD correction, etc. I/O ports Total * CMOS input * CMOS I/O A/D converter Serial interface Timer * 8-bit resolution x 8 channels * Operable over a wide power supply voltage range: VDD = 2.7 to 6.0 V * 3-wire/SBI/2-wire mode selectable * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Clock timer * Watchdog timer Timer output Clock output Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt Test input 3 (14-bit PWM output : 1) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation) 32.768 kHz (at subsystem clock 32.768 kHz operation) 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation) Internal : 8, External : 4 Internal : 1 Internal : 1 Internal : 1 External : 1 VDD = 2.7 to 6.0 V -40 to +85 C * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 14 mm) * 64-pin ceramic shrink DIP (with window) (750 mil) : 1 channel : 1 channel : 1 channel * 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function) : 1 channel : : : 53 2 47 4 : 32 bytes : 32K bytes
Note
Function
* N-channel open-drain I/O (15 V withstand voltage) :
Operating voltage range Operating temperature range Package
Note The capacity of the internal PROM and internal high-speed RAM can be set by means of the memory size switching register.
3
PD78P014
PIN CONFIGURATION (Top View)
(1) Normal operating mode 64-pin plastic shrink DIP (750 mil) 64-pin ceramic shrink DIP (with window) (750 mil)
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52
AVREF AVDD P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 VPP X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14
PD78P014CW PD78P014DW
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Cautions 1. VPP pin should be connected to VSS directly. 2. AVDD pin should be connected to VDD. 3. AVSS pin should be connected to VSS.
4
PD78P014
64-pin plastic QFP (14 x 14 mm)
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P27/SCK0
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P12/ANI2
P21/SO1
P23/STB
P20/SI1
AVREF
AVDD
P11/ANI1 P10/ANI0 AVSS P04/XT1 XT2 VPP X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
PD78P014GC-AB8
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS
P56/A14
P57/A15
P60
P61
P62
P63
P64/RD
P47/AD7
P52/A10
P53/A11
P54/A12
Cautions 1. VPP pin should be connected to VSS directly. 2. AVDD pin should be connected to VDD. 3. AVSS pin should be connected to VSS.
P55/A13
P65/WR
P50/A8
P51/A9
5
PD78P014
P00 to P04 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57
: Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5
AD0 to AD7 A8 to A15 RD WR WAIT ASTB X1, X2 XT1, XT2 RESET ANI0 to ANI7 AVDD AVSS AVREF VDD VPP VSS
: Address/Data Bus : Address Bus : Read Strobe : Write Strobe : Wait : Address Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock) : Reset : Analog Input : Analog Power Supply : Analog Ground : Analog Reference Voltage : Power Supply : Programming Power Supply : Ground
P60 to P67 : Port 6 INTP0 to INTP3 : Interrupt From Peripherals TI0 to TI2 TO0 to TO2 SB0, SB1 SI0, SI1 SO0, SO1 SCK0, SCK1 PCL BUZ STB BUSY : Timer Input : Timer Output : Serial Bus : Serial Input : Serial Output : Serial Clock : Programmable Clock : Buzzer Clock : Strobe : Busy
6
PD78P014
(2) PROM programming mode 64-pin plastic shrink DIP (750 mil) 64-pin ceramic shrink DIP (with window) (750 mil)
1 2 3 4 (L) 5 6 7 8 D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 (L) A10 A11 A12 A13 VSS 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52
VSS VDD
(L)
VSS (L) Open VPP (L) Open VDD
PD78P014CW PD78P014DW
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
(L)
A9 RESET (L) CE OE
(L)
A14
Cautions 1. (L) 2. VSS
: Connect to VSS individually via a pull-down resistor. : Connect to ground.
3. RESET : Set to low level. 4. Open : Do not make any connection.
7
PD78P014
64-pin plastic QFP (14 x 14 mm)
(L) (L)
54 53 52 51 50
64 D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 1 2 3 4 5 6
63
62
61
60
59
58
57
56
55
VDD
VSS
49 48 (L) 47 46 45 44 43 VSS (L) Open VPP (L) Open VDD
PD78P014GC-AB8
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
42 41 40 39 38 37 36 35 34
(L)
A9 RESET (L)
24
25
26
27
28
29
30
31
33 32
A10
A11
A12
A13
VSS
A7
A8
(L)
A14
(L)
Cautions 1. (L) 2. VSS
: Connect to VSS individually with a pull-down resistor. : Connect to ground.
3. RESET : Set to low level. 4. Open : Do not make any connection. A0 to A14 D0 to D7 CE OE : Address Bus : Data Bus : Chip Enable : Output Enable RESET VDD VPP VSS : Reset : Power Supply : Programming Power Supply : Ground
8
OE
CE
TO0/P30 PROGRAM COUNTER PORT0
BLOCK DIAGRAM
TI0/INTP0/P00
16-bit TIMER/ EVENT COUNTER
P00 P01-P03 P04
TO1/P31 PORT1 GENERAL REG. PORT2 RAM DATA MEMORY 1056x8 PORT3
TI1/P33
8-bit TIMER/ EVENT COUNTER 1
P10-P17
TO2/P32 DECODE AND CONTROL
TI2/P34
8-bit TIMER/ EVENT COUNTER 2
PROM PROGRAM MEMORY 32768x8
P20-P27
P30-P37
WATCHDOG TIMER
PORT4
P40-P47
WATCH TIMER
SI0/SB0/P25 ALU PSW SP
PORT5
P50-P57
SO0/SB1/P26
SERIAL INTERFACE 0
SCK0/P27 PORT6 P60-P67
SI1/P20 CLOCK GENERATOR SUB MAIN
SO1/P21 SCK1/P22 BUZZER OUTPUT CLOCK OUTPUT CONTROL CLOCK DIVIDER
STB/P23 BUSY/P24
SERIAL INTERFACE 1
STAND BY CONTROL
AD0/P40AD7/P47 A8/P50A15/P57
A/D CONVERTER
BUZ/P36
PCL/P35
P04/XT1 XT2
X1 X2
EXTERNAL ACCESS
RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET VDD VSS VPP
ANI0/P10 -ANI7/P17 AVDD AVSS AVREF
INTP0/P00 -INTP3/P03
INTERRUPT CONTROL
PD78P014
9
PD78P014
CONTENTS 1. 2. DIFFERENCES BETWEEN PD78P014 AND MASK ROM VERSION ................................................... 11 PIN FUNCTIONS ....................................................................................................................................... 12
2.1 2.2 2.3 Normal Operating Mode Pins ......................................................................................................................... 12 PROM Programming Mode Pins ..................................................................................................................... 15 Pin Input/Output Circuits and Connection of Unused Pins ........................................................................ 16
3. 4.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ................................................................... 18 PROM PROGRAMMING ........................................................................................................................... 19
4.1 4.2 4.3 Operating Modes .............................................................................................................................................. 19 PROM Write Procedure .................................................................................................................................... 20 PROM Read Procedure ..................................................................................................................................... 22
5. 6. 7. 8. 9.
ERASURE PROCEDURE (PD78P014DW ONLY) ................................................................................... 23 OPAQUE FILM FOR ERASURE WINDOW (PD78P014DW ONLY) ...................................................... 23 ONE-TIME PROM VERSION SCREENING .............................................................................................. 23 ELECTRICAL SPECIFICATIONS ............................................................................................................... 24 CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ........................................................................ 49
10. PACKAGE DRAWINGS ............................................................................................................................. 53 11. RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 56 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 57 APPENDIX B. RELATED DOCUMENTS ........................................................................................................59
10
PD78P014
1. DIFFERENCES BETWEEN PD78P014 AND MASK ROM VERSION
The PD78P014 incorporates one-time PROM which can be written to once only, or EPROM to which programs can be written, erased and rewritten. By setting the internal memory size switching register, it is possible to make the functions of this device, except for the PROM specification and mask option for pins P60 to P63, identical to those of a mask ROM version. The differences between PD78P014 and mask ROM versions are shown in Table 1-1.
Table 1-1. Differences Between PD78P014 and Mask ROM Version
Item IC pin VPP pin Mask option for pins P60 to P63
PD78P014
No Yes No mask option for incorporation of pullup resistor
Mask ROM Version Yes No Pull-up resistor incorporation possible by means of mask option
Caution In the PD78P014, the capacity of the internal PROM and internal high-speed RAM can be changed by using the internal memory size switching register. RESET input sets internal PROM to 32K bytes and internal high-speed RAM to 1K bytes.
11
PD78P014
2. PIN FUNCTIONS
2.1 Normal Operating Mode Pins (1) Port pins (1/2)
Alternate Pin Name P00 P01 P02 P03 P04
Note 1
I/O Input Input/ output Port 0 5-bit I/O port
Function Input only Input/output can be specified in 1-bit unit. When used as an input port, pull-up resistor can be used by software. Input only Port 1 8-bit input/output port. Input/output can be specified in 1-bit unit. When used as an input port, pull-up resistor can be used by software.Note 2
After Reset Input Input
Function INTP0/TI0 INTP1 INTP2 INTP3
Input Input/ output
Input Input
XT1 ANI0 to ANI7
P10 to P17
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
Input/ output
Port 2 8-bit input/output port. Input/output can be specified in 1-bit unit. When used as an input port, pull-up resistor can be used by software.
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 3 8-bit input/output port. Input/output can be specified in 1-bit unit. When used as an input port, pull-up resistor can be used by software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ -
Input/ output
Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, pull-up resistor can be used by software. (Test input flag (KRIF) is set to 1 by falling edge detection.)
Input
AD0 to AD7
Notes 1. When P04/XT1 pins are used as the input ports, set processor clock control register bit 6 (FRC) to 1. (Do not use the on-chip feedback resistor of the subsystem clock oscillation circuit.) 2. When P10/ANI0 to P17/ANI7 pins are used as the analog inputs for A/D converter, the pull-up resistor is automatically disabled.
12
PD78P014
(1) Port pins (2/2)
Pin Name P50 to P57
I/O Input/ output Port 5 8-bit input/output port. LED can be driven directly.
Function
After Reset Input
Alternate Function A8 to A15
Input/output can be specified in 1-bit unit. When used as an input port, pull-up resistor can be used by software.
P60 P61 P62 P63 P64 P65 P66 P67
Input/ output
Port 6 8-bit input/output port. Input/output can be specified in 1-bit unit.
N-ch open-drain input/ output port. LED can be driven directly.
Input
--
When used as an input port, pull-up resistor can be used by software.
RD WR WAIT ASTB
13
PD78P014
(2) Non port pins (1/2)
Altrnate Pin Name INTP0 INTP1 INTP2 INTP3 SI0 SI1 SO0 SO1 SB0 SB1 SCK0 SCK1 STB BUSY TI0 TI1 TI2 TO0 TO1 TO2 PCL BUZ AD0 to AD7 Output Output Input/ output Output Output Output Input/ output Input/ output Output Input Input Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input Falling edge detection external interrupt input. Serial interface serial data input. Input I/O Input Function External interrupt input with specifiable valid edge (rising edge, falling edge, or both rising and falling edges). After Reset Input Function P00/TI0 P01 P02 P03 P25/SB0 P20 P26/SB1 P21 P25/SI0 P26/SO0 Serial interface serial clock input/output. Input Input Input Input P27 P22 Serial interface automatic transmission/reception strobe output. Serial interface automatic transmission/reception busy input. Input of external count clock to 16-bit timer (TM0). Input of external count clock to 8-bit timer (TM1). Input of external count clock to 8-bit timer (TM2). 16-bit timer (TM0) output (alternate function with 14-bit PWM output). 8-bit timer (TM1) output. 8-bit timer (TM2) output. Clock output (for trimming main system clock or subsystem clock). Buzzer output. Low address/data bus when memory is expanded externally. Input Input Input Input P23 P24 P00/INTP0 P33 P34 P30 P31 P32 P35 P36 P40 to P47
A8 to A15 RD WR WAIT ASTB
High address bus when memory is expanded externally. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Input
P50 to P57 P64 P65
Input Output
Wait insertion at external memory access. Output of strobe which externally latches address information to be output to ports 4 and 5 when accessing external memory.
Input Input
P66 P67
14
PD78P014
(2) Non port pins (2/2)
Pin Name ANI0 to ANI7 AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD VPP VSS
I/O Input Input -- -- Input Input -- Input -- -- -- -- Positive power supply. A/D converter analog input.
Function
After Reset Input -- -- -- -- -- --
Alternate Function P10 to P17 -- -- -- -- -- -- P04 -- -- -- --
A/D converter reference voltage input. A/D converter analog power supply. Connect to VDD. A/D converter ground potential. Connect to VSS. System reset input. Main system clock oscillation crystal connection.
Subsystem clock oscillation crystal connection.
Input -- -- -- --
(High voltage application for program write/verify. Directly connected to VSS in normal operating mode.) Ground potential
2.2
PROM Programming Mode Pins
Pin Name RESET
I/O Input PROM programming mode setting.
Function
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal to the RESET pin, the PROM programming mode is set. VPP A0 to A14 D0 to D7 Input Input Input/ output CE OE VDD VSS Input Input -- -- PROM enable input/program pulse input. PROM read strobe input. Positive power supply. Ground potential. PROM programming mode setting and high voltage application for program write/verify. Address bus. Data bus.
15
PD78P014
2.3
Pin Input/Output Circuits and Connection of Unused Pins
The input/output circuit type of each pin and the recommended connection of unused pins are shown in Table 2-1. The configuration of each type of input/output circuit is shown in Figure 2-1. Table 2-1. Type of Pin Input/Output Circuits
Pin Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 to P17/ANI7 16 11 Input Input/output Connected to VSS . Input Output Input Output : Connect to VDD or VSS . : Leave open. : Connect to VDD or VSS . : Leave open. Input/Output Circuit Type 2 8-A I/O Input Input/output Recommended Connection for Used Pins Connect to VSS . Input Output : Connect to VSS . : Leave open.
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7
8-A 5-A 8-A 5-A 8-A 10-A
Input/output
5-A
Input/output
Input Output
: Connect to VDD or VSS . : Leave open.
8-A
5-A
5-E
Input/output
Input Output
: Connect to VDD or VSS . : Leave open. : Connect to VDD or VSS . : Leave open.
P50/A8 to P57/A15 P60 to P63 P64/RD P65/WR P66/WAIT P67/ASTB RESET XT2 AVREF AVDD AVSS VPP
5-A 13 5-A
Input/output
Input Output
2 16 --
Input -- Leave open. Connect to VSS . Connect to VDD. Connect to VSS .
--
Directly connect to VSS.
16
PD78P014
Figure 2-1. Pin Input/Output Circuits
VDD
Type 2
Type 10-A pullup enable
P-ch V DD
IN data
P-ch IN/OUT
Schmitt-Triggered Input with Hysteresis Characteristic
open-drain output disable
N-ch
Type 5-A pullup enable V DD data
V DD
Type 11 pullup enable data
VDD P-ch V DD P-ch IN/OUT
P-ch
P-ch IN/OUT
output disable Comparator + -
N-ch P-ch
output disable
N-ch
N-ch VREF (Threshold Voltage) input enable Type 5-E pullup enable V DD data P-ch IN/OUT output disable N-ch Middle-High Voltage Input Buffer VDD input enable Type 13
P-ch data output disable N-ch
IN/OUT
Type 8-A
VDD
Type 16
pullup enable V DD data P-ch
P-ch P-ch
feedback cut-off
IN/OUT output disable N-ch XT1 XT2
17
PD78P014
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register is used to prevent part of the internal memory from being used by software. Setting the internal memory size switching register (IMS) enables memory mapping identical to that of a mask ROM version with different internal memory (ROM and RAM) to be used. The IMS register is set by an 8-bit memory manipulation instruction. RESET input sets this register to C8H.
Figure 3-1. Internal Memory Size Switching Register Format
7 IMS
6
5
4 0
3
2
1
0
Address FFF0H
At Reset C8H
R/W W
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 4 K bytes 8 K bytes 16 K bytes 24 K bytes 32K bytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Internal High-Speed RAM Capacity Selection 768 bytes 640 bytes 512 bytes 384 bytes 256 bytes Setting prohibited 1024 bytes 896 bytes
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
The IMS set values to make the memory map identical to various mask ROM versions are shown in Table 3-1.
Table 3-1. Examples of Internal Memory Size Switching Register Settings
Target Mask ROM Version
IMS Set Value 82H 64H 42H
Target Mask ROM Version
IMS Set Value 44H C6H C8H
PD78001B PD78002B PD78011B
PD78012B PD78013 PD78014
18
PD78P014
4. PROM PROGRAMMING
The PD78P014 incorporates a 32K-byte PROM as program memory. When programming the PD78P014, the PROM programming mode is set by means of the VPP and RESET pins. For the connection of unused pins, see "PIN CONFIGURATION (2) PROM programming mode". 4.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PD78P014 enters the programming mode. This is one of the operating modes shown in Table 4-1 below according to the setting of the CE and OE pins. Also, the PROM contents can be read by setting the read mode. Table 4-1. PROM Programming Operating Modes
Pins Operating Mode Program write Program verify Program inhibit
RESET
VPP
VDD
CE
OE Data input
D0 to D7
L +12.5 V L +6 V H H L +5 V +5 V L H
H L H L H L/H
Data output High-impedance Data output High-impedance High-impedance
Read Output disable Standby
19
PD78P014
4.2
PROM Write Procedure
The PROM write procedure is as shown below, allowing high-speed writing. (1) Fix the RESET pin low. Supply +5 V to the VPP pin. Unused pins are handled as shown in "PIN CONFIGURATION (2) PROM programming mode". (2) Supply +6 V to the VDD pin and +12.5 V to the VPP pin. (3) Supply the initial address. (4) Supply the write data. (5) Supply a 1 ms program pulse (active low) to the CE pin. (6) Verify mode. If written, go to (8); if not written, repeat (4) through (6). When the write operation has been repeated 25 times, go to (7). (7) Halt write operation due to defective device. (8) Supply write data and supply (times repeated in (4) through (6)) x 3 ms program pulse (additional write). (9) Increment the address. (10) Repeat (4) through (9) until the final address. Timing for steps (2) through (8) above is shown in Figure 4-1. Figure 4-1. PROM Write/Verify Timing
Repe a t e d X T i m e s Write Verify Additional Write
A0-A1 4
Address Input
Hi- Z D0 -D7 +12 .5 V V PP VDD +6 V VDD V DD Data Input
Hi-Z
Data Output
Hi-Z Data Input
Hi-Z
3Xms
CE(Inp ut)
OE(In pu t)
20
PD78P014
Figure 4-2. Write Procedure Flowchart
(1)
Start write
(2)
Supply power supply voltage
(3)
Supply initial address
(4)
Supply write data
(5)
Supply program pulse
Write Not Possible (Less than 25 Times)
(6) Verify mode
Write Not Possible (25th Times)
Write OK (8) Additional write (3X ms pulse) X: Number of Write Repetitions
(9)
Address increment
(10) Final Address Final address
>Final Address Write completed
(7) Defective device
21
PD78P014
4.3 PROM Read Procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low. Supply +5 V to the VPP pin. Unused pins are handled as shown in "PIN CONFIGURATION (2) PROM programming mode". (2) Supply +5 V to the VDD and VPP pins. (3) Input address of data to be read to pins A0 through A14. (4) Read mode . (5) Output data to pins D0 through D7. Timing for steps (2) through (5) above is shown in Figure 4-3. Figure 4-3. PROM Read Timing
A0-A14
Address Input
CE (Input)
OE (Input)
D0-D7
Hi-Z
Data Output
Hi-Z
22
PD78P014
5. ERASURE PROCEDURE (PD78P014DW ONLY)
With the PD78P014DW, it is possible to erase (set to FFH) data written to the program memory, and rewrite the memory. The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or less. Usually, exposure is performed with ultraviolet light with a wavelength of 254 nm. The amount of exposing required for complete erasure is shown below. * * UV intensity x erasure time: 15 W*s/cm2 or more Erasure time: 15 to 20 minutes (using a 12,000 W/cm2 ultraviolet lamp. A longer erasure time may be required in case of deterioration of the ultraviolet lamp or dirt on the erasure window).
Erasure should be carried out with the ultraviolet lamp placed at a distance of 2.5 cm or less from the window. If the ultraviolet lamp is fitted with a filter, this should be removed before performing exposure.
6. OPAQUE FILM FOR ERASURE WINDOW (PD78P014DW ONLY)
An opaque film should be applied to the erasure window except when erasing the EPROM contents, in order to prevent the EPROM contents from being unintentionally erased by light other than from the erasure lamp, and the internal circuits other than EPROM from misoperation due to light.
7. ONE-TIME PROM VERSION SCREENING
One-time PROM versions (PD78P014CW and PD78P014GC-AB8) cannot be fully tested and shipped by NEC for reasons related to their structure. It is recommended that after writing the necessary data and storing at high temperature under the following conditions, screening should be conducted to verify the PROM.
Storage Temperature 125 C
Storage Time 24 hours
NEC provides charged services for one-time PROM writing, marking, screening, and verification, under the name "QTOP Microcomputer". Contact NEC for details.
5
23
PD78P014
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 C)
Parameter Supply voltage Symbol VDD VPP AVDD AVREF AVSS VI1 VI2 VI3 VO VAN Test Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to + 0.3 -0.3 to VDD + 0.3 -0.3 to +16 -0.3 to +13.5 -0.3 to VDD + 0.3 AVSS - 0.3 to AVREF + 0.3 -10 -15 -15 30 15 100 70 100 70 50 20 50 20 -40 to +85 -65 to +150 Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA C C
Input voltage
P00 P30 P64 P60 A9
to to to to
P04, P10 to P17, P20 to P27, P37, P40 to P47, P50 to P57, P67, X1, X2, XT2 P63 Open-drain PROM programming mode Analog input pins
Output voltage Analog input voltage Output current high
P10 to P17 1 pin
Total for P10 to P17, P20 to P27, P30 to P37 IOH Output current low Total for P01 to P03, P40 to P47, P50 to P57, P60 to P67 Peak value 1 pin R.m.s. value Total for P40 to P47, Peak value P50 to P55 R.m.s. value Total for P01 to P03, Peak value P56, P57, P60 to P67 R.m.s. value Total for P01 to P03, Peak value P64 to P67 R.m.s. value Total for P10 to P17, Peak value P20 to P27, P30 to P37 R.m.s. value
IOLNote
Operating temperature Storage temperature
Topt Tstg
Note The r.m.s. value should be calculated as follows: [R.m.s. value] = [Peak value] x Duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
24
PD78P014
Main System Clock Oscillator Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Recommended Circuit
Resonator Ceramic resonator
Parameter
Test Conditions VDD = Oscillation voltage range After VDD has reached MIN. of oscillation voltage range
MIN.
TYP.
MAX.
Unit
Vss X1
X2 R1
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
1
10
MHz
C1
C2
4
ms
Crystal resonator
Vss X1 C1
X2 C2
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 VDD = 4.5 to 6.0 V
1
8.38
10
MHz
10 30 1.0 10.0
ms
External clock
X1
X2
X1 input frequency (fX)Note 1 X1 input high-/lowlevel width (tXH/tXL)
MHz
PD74HCU04
42.5
500
ns
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times. 2. This is the time required for oscillation to stabilize after a reset or STOP mode release. Cautions 1. When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. * Do not connect to a ground pattern carrying a high current. * A signal should not be taken from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
25
PD78P014
Subsystem Clock Oscillator Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Crystal resonator Recommended Circuit
Vss XT1 XT2 R2 C3 C4
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 VDD = 4.5 to 6.0 V
32
32.768
35
kHz
1.2
2 s 10
External clock
XT1 XT2
XT1 input frequency (fXT)Note 1 XT1 input high-/lowlevel width (tXTH/tXTL)
32
100
kHz
5
15
s
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times. 2. Time required to stabilize oscillation after VDD reaches MIN. of oscillation voltage range. Cautions 1. When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. * Do not connect to a ground pattern carrying a high current. * A signal should not be taken from the oscillator. 2. The subsystem clock oscillator is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. When using the subsystem clock, special care is needed regarding the wiring method.
26
PD78P014
Recommended Oscillation Constants Main System Clock: Ceramic Resonator (Ta = -40 to +85 C)
Recommended Oscillator Constant Range C1 (pF) 100 100 100 100 C2 (pF) 100 100 100 100 R1 (k) 6.8 4.7 0 0 0 0 0 0 0 0 0 Oscillation Voltage MIN. (V) 2.8 2.8 2.8 2.7 2.7 2.7 2.7 2.7 2.7 3.0 3.0 MAX. (V) 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0
Manufacturer Murata Mfg.
Product Name CSB1000J CSBxxxxJ CSAx. xxxMK CSAx. xxMG093 CSTx. xxMG093 CSAx. xxMG CSTx. xxMGW CSAx. xxMGU CSTx. xxMGWU CSAx. xxMT CSTx. xxMTW
Frequency (MHz) 1.00 1.01 to 1.25 1.26 to 1.79 1.80 to 2.44
Incorporated Incorporated 30 2.45 to 4.18 4.19 to 6.00 6.01 to 10.0 30
Incorporated Incorporated 30 30
Incorporated Incorporated 30 30
Incorporated Incorporated
Remark x. xx, x. xxx and xxxx indicate frequency. Subsystem Clock: Crystal Resonator (Ta = -40 to +60 C)
Recommended Oscillator Constant Range C3 (pF) 10 C4 (pF) 10 R2 (k) 100 Oscillation Voltage MIN. (V) 2.7 MAX. (V) 6.0
Manufacturer
Product Name
Frequency (kHz) 32.768
Daishinku Corp.
DT-38 (1TA632E00, load capacitance 6.3 pF)
Capacitance (Ta = 25 C, VDD = VSS = 0 V)
Parameter Input capacitance Input/output capacitance Symbol CIN Test Conditions f = 1 MHz Unmeasured pins returned to 0 V P01 to P03, P10 to P17, f = 1 MHz Unmeasured P20 to P27, P30 to P37, P40 to P47, P50 to P57, pins returned to 0 V P64 to P67 P60 to P63 MIN. TYP. MAX. 15 Unit pF
15
pF
CIO
20
pF
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
27
PD78P014
DC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Input voltage high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage low VIL1 VIL2 VIL3 VIL4 VIL5 Output voltage high VOH1 Output voltage low VOL1 Test Conditions P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P64 to P67 MIN. 0.7 VDD TYP. MAX. VDD VDD 15 VDD VDD VDD 0.3 VDD 0.2 VDD 0.3 VDD 0.2 VDD 0.4 0.4 0.3 Unit V V V V V V V V V V V V V V V 0.4 2.0 V
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET 0.8 VDD P60 to P63 X1, X2 XT1/P04, XT2 VDD = 4.5 to 6.0 V Open-drain 0.7 VDD VDD - 0.5 VDD - 0.5 VDD - 0.3 P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P64 to P67 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET VDD = 4.5 to 6.0 V P60 to P63 X1, X2 VDD = 4.5 to 6.0 V XT1/P04, XT2 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A P50 to P57, P60 to P63 VDD = 4.5 to 6.0 V, IOL = 15 mA 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5
P01 to P03, P10 to P17, VDD = 4.5 to 6.0 V, P20 to P27, P30 to P37, I = 1.6 mA P40 to P47, P64 to P67 OL VDD = 4.5 to 6.0 V, VOL2 VOL3 Input leakage current high SB0, SB1, SCK0 IOL = 400 A P00 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET X1, X2, XT1/P04, XT2 P60 to P63 P00 P20 P40 P60 to to to to P03, P27, P47, P67, P10 to P17, P30 to P37, P50 to P57, RESET open-drain, pulled high (R = 1 k)
0.4
V
0.2 VDD 0.5
V V
ILIH1 VIN = VDD ILIH2 ILIH3
3
A
20 80
A A A
VIN = 15 V
Input leakage current low ILIL1 VIN = 0 V
-3
ILIL2
X1, X2, XT1/P04, XT2
-20
A
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
28
PD78P014
DC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Output leakage current high Output leakage current low Software pull-up resistor R2 Symbol ILOH1 ILOL VOUT = VDD VOUT = 0 V VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67 8.38 MHz crystal oscillation operating mode 8.38 MHz crystal oscillation HALT mode 32.768 kHz crystal oscillation operating mode 32.768 kHz crystal oscillation HALT mode XT1 = 0 V IDD5 STOP mode Feedback resistor used XT1 = 0 V STOP mode Feedback resistor not used Test Conditions MIN. TYP. MAX. 3 -3 Unit
A A
4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V VDD = 5.0 V 10%Note 1 VDD = 3.0 V 10%Note 2 VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10%
15 20
40
90 500
k k mA mA mA
Supply currentNote 3
IDD1 IDD2 IDD3 IDD4
9 1 1.4 550 90 50 25 5 1 0.5 0.1 0.05
27 3 4.2 1650 180 100 50 10 30 10 30 10
A A A A A A A A A
IDD6
Notes 1. High-speed mode operation (when processor clock control register is set to 00H). 2. Low-speed mode operation (when processor clock control register is set to 04H). 3. Not including AVREF currents or port currents Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
29
PD78P014
AC Characteristics (1) Basic operation (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Cycle time (Min. instruction execution time)
Symbol
Test Conditions VDD = 4.5 to 6.0 V
MIN. 0.48 1.91
TYP.
MAX. 64 64 64 64 125 4 275
Unit
s s s s s MHz kHz ns s s s s s
TCY
Operating with main system clock
TI input frequency TI input high-/low-level width Interrupt input high-/lowlevel width
fTI tTIH tTIL tINTH tINTL tRSL
Ta = -40 to +40 C VDD = 4.75 to 6.0 V Ta = -40 to +40 C Operating with subsystem clock VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INTP0 INTP1 to INTP3 KR0 to KR7
0.4 0.96 40 0 0 100 1.8 8/fsamNote 10 10 10
122
RESET low-level width
Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible between fX/2N+1, fX/64, and fX/128 (N = 0 to 4).
TCY
VS
VDD (At main system clock operation)
60
Cycle Time TCY [ s]
10 Operation Guaranteed Range (Ta = -40 to +85 C)
2.0
1.0 0.5 0.4
0
1
2
3
4
5
6
Supply Voltage VDD [V]
Caution When Ta = -40 to +40 C, the operation guaranteed range is extended to the dotted line.
30
PD78P014
(2) Read/write operation (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address
Symbol tASTH tADS tADH tADD1 tADD2 tRDD1
Test Conditions
MIN. 0.5tCY 0.5tCY - 30
MAX.
Unit ns ns ns
Load resistance 5 k
10 (2 + 2n)tCY - 50 5 (3 + 2n)tCY - 100 (1 + 2n)tCY - 25 (2.5 + 2n)tCY - 100 0 (1.5 + 2n)tCY - 20 (2.5 + 2n)tCY - 20 0.5tCY 1.5tCY 0.5tCY (0.5 + 2n)tCY + 10 100 5 (2.5 + 2n)tCY - 20 0.5tCY - 30 1.5tCY - 30 tCY - 10 tCY + 40 (2 + 2n)tCY
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data input time from RD tRDD2 Read data hold time RD low-level width tRDL2 tRDWT1 WAIT input time from RD tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD in external fetch Address hold time from RD in external fetch Write data output time from RD WR delay time from write data tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST tRDH tRDL1
tRDADH tRDWD VDD = 4.5 to 6.0 V tWDWR
tCY 10 0.5tCY - 120 0.5tCY - 170 VDD =4.5 to 6.0 V tCY tCY
tCY + 50
ns ns
0.5tCY 0.5tCY tCY + 60 tCY + 100 2.5tCY + 80 2.5tCY + 80
ns ns ns ns ns ns
Address hold time from WR RD delay time from WAIT WR delay time from WAIT
tWRADH tWTRD tWTWR 0.5tCY 0.5tCY
Remarks
1. 2. 3.
tCY = TCY/4 n indicates number of waits. CL = 100 pF (CL indicates the load capacitance of pins P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/ RD, P65/WR, P66/WAIT, P67/ASTB.)
31
PD78P014
(3) Serial interface (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter
Symbol tKCY1
Test Conditions VDD = 4.5 to 6.0 V
MIN. 800 3200
TYP.
MAX.
Unit ns ns ns ns ns ns
SCK cycle time
SCK high-/low-level width SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK
tKH1 tKL1 tSIK1 tKSI1
VDD = 4.5 to 6.0 V
tKCY1/2 - 50 tKCY1/2 - 150 100 400
VDD = 4.5 to 6.0 V tKSO1 C = 100 pFNote
300 1000
ns ns
Note C is the load capacitance of SO output line. (b) 3-wire serial I/O mode (SCK...External clock input)
Parameter Symbol tKCY2 3200 SCK high-/low-level width SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKH2 tKL2 tSIK2 tKSI2 VDD = 4.5 to 6.0 V tKSO2 C = 100 pFNote 1000 When using the external device expansion function When using the 16-bit timer output function When not using the 16-bit timer output function 160 ns ns VDD = 4.5 to 6.0 V 400 1600 100 400 300 ns ns ns ns ns ns Test Conditions VDD = 4.5 to 6.0 V SCK cycle time MIN. 800 TYP. MAX. Unit ns
5
5
SCK rise and fall times (For serial interface channel 0)
tR2 tF2
5
When not using the external device expansion function
700
ns
1000
ns
5
5
SCK rise and fall times (For serial interface channel 1)
tR2 tF2
When using the external device expansion function When not using the external device expansion function
160
ns
1000
ns
Note C is the load capacitance of SO output line.
32
PD78P014
(c)
SBI mode (SCK...Internal clock output)
Parameter Symbol tKCY3 3200 ns ns ns ns ns ns 250 1000 ns ns ns ns ns ns tKH3 tKL3 tSIK3 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKCY3/2 - 50 tKCY3/2 - 150 100 300 tKSI3 VDD = 4.5 to 6.0 V tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns
SCK cycle time
SCK high-/low-level width SB0, SB1 setup time (to SCK) SB0, SB1 hold time (from SCK) SB0, SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width
tKSO3
R = 1 k, C = 100 pFNote
tKSB tSBK tSBH
tSBL
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
33
PD78P014
(d)
SBI mode (SCK...External clock input)
Parameter Symbol tKCY4 3200 ns ns ns ns ns ns 300 1000 ns ns ns ns ns ns tKH4 tKL4 tSIK4 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 300 tKSI4 VDD = 4.5 to 6.0 V tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 When using the external device expansion function When using the 16-bit timer output function When not using the 16-bit timer output function Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns
SCK cycle time
SCK high-/low-level width SB0, SB1 setup time (to SCK) SB0, SB1 hold time (from SCK) SB0, SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width
tKSO4
R = 1 k, C = 100 pFNote
tKSB tSBK tSBH
tSBL
5
160
ns
5
SCK rise and fall times
tR4 tF4
5
When not using the external device expansion function
700
ns
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
34
PD78P014
(e)
2-wire serial I/O mode (SCK... Internal clock output)
Parameter Symbol tKCY5 3800 ns ns ns ns ns 250 1000 ns ns tKH5 tKL5 tSIK5 tKSI5 tKSO5 R = 1 k, C = 100 pFNote VDD = 4.5 to 6.0 V R = 1 k, C = 100 pFNote tKCY5/2 - 50 tKCY5/2 - 50 300 600 0 0 Test Conditions VDD = 4.5 to 6.0 V MIN. 1600 TYP. MAX. Unit ns
SCK cycle time SCK high-level width SCK low-level width SB0, SB1 setup time (to SCK) SB0, SB1 hold time (from SCK) SB0, SB1 output delay time from SCK
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. (f) 2-wire serial I/O mode (SCK... External clock input)
Parameter Symbol tKCY6 3800 SCK high-level width SCK low-level width SB0, SB1 setup time (to SCK) SB0, SB1 hold time (from SCK) SB0, SB1 output delay time from SCK tKH6 tKL6 tSIK6 tKSI6 tKSO6 R = 1 k, C = 100 pFNote VDD = 4.5 to 6.0 V 650 800 100 tKCY6/2 0 0 300 1000 160 ns ns ns ns ns ns ns ns Test Conditions VDD = 4.5 to 6.0 V SCK cycle time MIN. 1600 TYP. MAX. Unit ns
When using the external device expansion function When using the 16-bit timer output function When not using the 16-bit timer output function
5
SCK rise and fall times
tR6 tF6
When not using the external device expansion function
700
ns
5
1000
ns
5
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
35
PD78P014
(g)
3-wire serial I/O mode with automatic transmit/receive function (SCK...Internal clock output)
Parameter Symbol tKCY7 3200 ns ns ns ns ns 300 1000 tSBD tSBW 400 tKCY7 - 30 tKCY7 tKCY7 + 30 ns ns ns ns VDD = 4.5 to 6.0 V tKCY7/2 - 50 tKCY7/2 - 150 100 400 C = 100 pFNote VDD = 4.5 to 6.0 V Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns
SCK cycle time
SCK high/low-level width SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK STB from SCK Strobe signal highlevel width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK from busy inactive
tKH7 tKL7 tSIK7 tKSI7 tKSO7
tBYS
100
ns
tBYH
100
ns
tSPS
2tKCY7
ns
Note C is the load capacitance of the SO output line. (h) 3-wire serial I/O mode with automatic transmit/receive function (SCK...External clock input)
Parameter Symbol tKCY8 3200 SCK high/low-level width SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKH8 tKL8 tSIK8 tKSI8 VDD = 4.5 to 6.0 V tKSO8 C = 100 pF
Note
Test Conditions VDD = 4.5 to 6.0 V
MIN. 800
TYP.
MAX.
Unit ns ns ns ns ns ns
SCK cycle time
VDD = 4.5 to 6.0 V
400 1600 100 400 300 1000
ns ns ns
5
SCK rise and fall times tR8 tF8
When using the external device expansion function When not using the external device expansion function
160
5
1000
ns
Note C is the load capacitance of the SO output line.
36
PD78P014
A/D Converter Characteristics (Ta = -40 to +85 C, AVDD = VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error
Note
Symbol
Test Conditions
MIN. 8
TYP. 8
MAX. 8 0.6
Unit bit %
Conversion time Sampling time Analog input voltage Reference voltage AVREF current
tCONV tSAMP VIAN AVREF IREF
19.1 24/fx AVSS 2.7 0.5
200
s s
AVREF AVDD 1.5
V V mA
Note Excluding quantization error (1/2LSB). Shown as a percentage of the full scale value.
37
PD78P014
AC Timing Test Point (Excluding X1 and XT1 Input)
0.8 VDD 0.2 VDD
Point of measurement
0.8 VDD 0.2 VDD
Clock Timing
1/fX
tXL
tXH VDD - 0.5 V 0.4V
X1 Input
1/fXT
tXTL XT1 Input
tXTH VDD - 0.5 V 0.4V
TI Timing
1/fTI
tTIL TI0-TI2
tTIH
38
PD78P014
Read/Write Operation External fetch (no wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
39
PD78P014
External data access (no wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
RD tASTRD tRDL2
tRDWD
tWDS tWDWR
tWDH tWRADH
WR tASTWR tWRL1
External data access (wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD RD tRDL2 tRDWD WR tASTWR tWRL1 tWRADH tWDS tWDWR tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
40
PD78P014
Serial Transfer Timing 3-wire serial I/O mode:
tKCY 1.2
tKL1.2 tR2 SCK tSIK1.2 tKSI1.2
tKH1.2 tF2
5
SI tKSO1.2
Input Data
SO
Output Data
SBI mode (bus release signal transfer):
tKCY3.4 tKL3.4 tR4 SCK tKSB tSBL tSBH tSBK tSIK3.4 tKSI3.4 tKH3.4 tF4
5
SB0, SB1 tKSO3.4
SBI mode (command signal transfer):
tKCY3.4 tKL3.4 tR4 SCK tKSB tSBK tSIK3.4 tKSI3.4 tKH3.4 tF4
5
SB0, SB1 tKSO3.4
41
PD78P014
2-wire serial I/O mode:
tKCY5.6 tKL5.6 tKH5.6 tF6
5
SCK
tR6
tSIK5.6 tKSO5.6 SB0, SB1
tKSI5.6
3-wire serial I/O mode with automatic transmit/receive function:
SO
D2
D1
D0
D7
SI
D2 tSIK7.8 tKSO7.8
D1 tKSI7.8 tKH7.8
D0
D7
tF8
5
SCK tKL7.8 STB tSBD tR8 tSBW
tKCY7.8
3-wire serial I/O mode with automatic transmit/receive function (Busy processing):
SCK
7
8
9Note tBYS
10Note
10+nNote tBYH tSPS
1
BUSY (Active high)
Note The signal is not actually low here, but is represented in this way to show the timing.
42
PD78P014
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (Ta = -40 to +85 C)
Parameter Data retention power supply voltage Data retention power supply current Release signal set time Oscillation stabilization wait time
Symbol VDDDR
Test Conditions
MIN. 2.0
TYP.
MAX. 6.0
Unit V
IDDDR
VDDDR = 2.0 V Subsystem clock stop and feedback resistor disconnected 0 Release by RESET
0.1
10
A s
tSREL
218/fx Note
ms ms
tWAIT Release by interrupt
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/fx and 215/fx to 218/fx is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD Stop Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD Stop Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
43
PD78P014
Interrupt Input Timing
tINTL INTP0-INTP2
tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
44
PD78P014
DC Programming Characteristics (Ta = 25 5 C, VSS = 0 V)
Parameter Input voltage high Input voltage low Input leakage current Output voltage high Output voltage low Output leakage current VDDP supply voltage VPP supply voltage VDDP supply current
Symbol VIH
SymbolNote VIH
Test Conditions
MIN. 0.7 VDDP
TYP.
MAX. VDDP
Unit V
VIL ILIP VOH1 VOH2 VOL
VIL ILI VOH1 VOH2 VOL 0 VI VDDP IOH = -400 A IOH = -100 A IOL = 2.1 mA
0
0.3 VDDP 10
V
A
V V
2.4 VDD - 0.7 0.45
V
ILO
--
0 VO VDDP, OE = VIH
10
A
Program memory write mode VDDP VCC Program memory read mode Program memory write mode VPP VPP Program memory read mode Program memory write mode IDD ICC Program memory read mode CE = VIL, VI = VIH Program memory write mode CE = VIL, OE = VIH Program memory read mode
5.75 4.5 12.5
6.0 5.0 12.5 VPP = VDDP 5 5 5 1
6.25 5.5 12.8
V V V
30 30 30 100
mA mA mA
VPP supply current
IPP
IPP
A
Note Corresponding PD27C256A symbol.
45
PD78P014
Program Operation AC Characteristics (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Address setup time (to CE) OE delay time from data Input data setup time (to CE) Address hold time (from CE) Input data hold time (from CE) Output data hold time (from OE) VPP setup time (to CE) VDDP setup time (to CE) Initial program pulse width Additional program pulse width Data output time from OE
Symbol tSAC tDDOO tSIDC tHCA tHCID
SymbolNote tAS tOES tDS tAH tDH
Test Conditions
MIN. 2 2 2 2 2
TYP.
MAX.
Unit
s s s s s
tHOOD tSVPC tSVDC tWL1 tWL2 tDOOD
tDF tVPS tVDS tPW tOPW tOE
0 1 1 0.95 2.85 1.0
130
ns ms ms
1.05 78.75 1
ms ms
s
Note Corresponding PD27C256A symbol.
Read Operation AC Characteristics (Ta = 25 5 C, VDD = 5.0 0.5 V, VPP = VDD, VSS = 0 V)
Parameter Data output time from address Data output time from CE Data output time from OE Data hold time (from OE) Data hold time (from address)
Symbol tDAOD tDCOD tDOOD tHCOD tHAOD
SymbolNote tACC tCE tOE tDF tOH
Test Conditions
MIN.
TYP.
MAX. 200 200 75
Unit ns ns ns ns ns
0 0
60
Note Corresponding PD27C256A symbol. PROM Mode Setting AC Characteristics (Ta = 25 5 C, VSS = 0 V)
Parameter PROM mode setup time
Symbol tSMA
Test Conditions
MIN. 10
TYP.
MAX.
Unit
s
46
PD78P014
PROM Write Mode Timing
A0-A14 tSAC
Valid Address tHCA
D0-D7
Data Input tSIDC tHCID
Data Output tHOOD
Data Input tSIDC tHCID
V PP V PP V DDP tSVPC
V DDP+ 1 V DDP V DDP tSVDC V IH CE V IL tWL1 tDDOO V IH OE VIL tDOOD tWL2
Cautions 1. VDDP should be applied before VPP, and cut after VPP. 2. VPP should not reach +13V or above including overshoot.
47
PD78P014
PROM Read Mode Timing
A0-A14
Valid Address
CE tDCOD
OE tDOOD tDAOO D0-D7 Hi-z Data Output tHAOD tHCOD Hi-z
PROM Mode Setting Timing
VDDP VDD 0
RESET
VDDP V PP 0 tSMA
A0- A14
Valid Address
48
PD78P014
9. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
IDD vs VDD (Main System Clock : 8.38 MHz)
(Ta = 25C) 10.0 PCC=00H PCC=01H 5.0 PCC=02H PCC=03H PCC=04H PCC=30H and HALT (X1 Oscillation, XT1 Oscillation)
1.0
0.5
Supply Current I DD [mA]
PCC=B0H 0.1
0.05
HALT (X1 Stop, XT1 Oscillation)
STOP (X1 Stop, XT1 Oscillation) and Reset
0.01
0.005
f X = 8.38 MHz f XT = 32.768 kHz
0.001 0 2 3 4 5 6 7 8
Supply Voltage VDD [V]
49
PD78P014
IDD vs VDD (Main System Clock : 4.19 MHz)
(Ta = 25C) 10.0
5.0
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation)
1.0
0.5
Supply Current I DD [mA]
PCC=B0H 0.1
0.05 HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation)
0.01
0.005
f X = 4.19 MHz f XT = 32.768 kHz
0.001 0 2 3 4 5 6 7 8
Supply Voltage VDD [V]
50
PD78P014
VOL vs IOL (Ports 0 , 2 to 5, P64 to P67)
(Ta = 25 C)
30
VDD = 6 V
VDD = 5 V
Output Current Low IOL [mA]
VDD = 4 V 20
VDD = 3 V
10
0
0
0.5
1.0
Output Voltage Low VOL [V]
VOL vs IOL (Port 1)
(Ta = 25 C)
30
VDD = 6 V
VDD = 5 V
VDD = 4 V
Output Current Low IOL [mA]
20
VDD = 3 V
10
0 0 0.5 1.0 Output Voltage Low VOL [V]
51
PD78P014
VOL vs IOL (P60 to P63)
(Ta = 25 C)
30
VDD = 6 V VDD = 5 V
Output Current Low IOL [mA]
20 VDD = 4 V
VDD = 3 V 10
0
0
0.5
1.0
Output Voltage Low VOL [V]
VOH vs IOH (Ports 0 to 5, P64 to P67)
(Ta = 25 C)
-10 Output Current High IOH [mA]
VDD = 6 V VDD = 5 V
VDD = 4 V
VDD = 3 V
-5
0 0 0.5 1.0 Output Voltage High VDD - VOH [V]
52
PD78P014
10. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25+0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020+0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010+0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
53
PD78P014
64 PIN CERAMIC SHRINK DIP (750 mil)
S 64 33
1 A
32
K L
J G H I
F D
N
M
CB
M
0 to 15
P64DW-70-750A
NOTES 1) Each lead centerline is located within 0.25 mm (0.010 inch) of its true position (T.P.) at maxi-mum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N S
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.)
+0.05 0.46 -
INCHES 2.310 MAX. 0.070 MAX. 0.070 (T.P.) 0.018
+0.002 -
0.8 MIN.
- 3.5 +0.3
0.031 MIN. 0.138 -
+0.012
1.0 MIN. 3.0 5.08 MAX. 19.05 (T.P.) 18.8 0.25 0.25 8.89
+0.05 -
0.039 MIN. 0.118 0.200 MAX. 0.750 (T.P.) 0.740 0.010 -0.003 0.01 0.350
+0.002
54
PD78P014
64 PIN PLASTIC QFP (
14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J
K P
N
L
P64GC-80-AB8-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q S
MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX.
M
INCHES 0.693 0.016 0.551 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
55
Q
55
PD78P014
11. RECOMMENDED SOLDERING CONDITIONS
The PD78P014 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman.
Table 11-1. Surface Mounted Type Soldering Conditions
PD78P014GC-AB8: 64-pin plastic QFP (14 x 14 mm)
Soldering Method Soldering Conditions Package peak temperature: 230 C Duration: 30 sec. max. (at 210 C or above) Number of times: Once Time limit: 2 daysNote (thereafter 20 hours prebaking required at 125 C) Package peak temperature: 215 C Duration: 40 sec. max. (at 200 C or above) Number of times: Once Time limit: 2 daysNote (thereafter 20 hours prebaking required at 125 C) Pin temperature: 300 C max. Duration: 3 sec. max. (Per side of the device) Symbol
Infrared ray reflow
IR30-202-1
VPS
VP15-202-1
Pin partial heating
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65% RH. Caution Use of more than one soldering method should be avoided (except in the case of pin partial heating).
Table 11-2. Insert Type Soldering Conditions
PD78P014CW: 64-pin plastic shrink DIP (750 mil) PD78P014DW: 64-pin ceramic shrink DIP (with window) (750 mil)
Soldering Method Wave soldering (Pin only) Soldering Conditions Solder bath temperature : 260 C max. Duration: 10 sec. max. Pin temperature: 300 C max. Duration: 3 sec. max (per 1 pin).
5
Pin partial heating
Caution The wave soldering applies to the pin only. Ensure that no solder touches the body directly.
56
PD78P014
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD78P014. Language Processing Software
RA78K/0 CC78K/0 DF78014
Note 1, 2, 3
78K/0 series common assembler package 78K/0 series common C compiler package
Note 1, 2, 3
Note 1, 2, 3
PD78014 subseries device file
78K/0 series common C compiler library source file
5
CC78K/0-L
Note 1, 2, 3
PROM Writing Tools
PG-1500 PA-78P014CW PA-78P014GC PG-1500 controller Note 1, 2
PROM programmer Programmer adapter connected to PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240CW-R EP-78240GC-R EV-9200GC-64 SD78K/0 SM78K/0 DF78014
Note 1, 2 Note 3, 4, 5, 6 Note 1, 2, 3, 4, 5
78K/0 series common in-circuit emulators 78K/0 series common break board
PD78002/78014 subseries evaluation emulation boards PD78244 subseries common emulation probes
Socket to be mounted on a user system board made for 64-pin plastic QFP IE-78000-R screen debugger 78K/0 series common system simulator
5
PD78014 subseries device file
Real-Time OS
RX78K/0 Note 1, 2, 3 MX78K/0 Note 1, 2, 3, 6
78K/0 series common real-time OS 78K/0 series common OS
5
57
PD78P014
Fuzzy Inference Development Support System
FE9000 Note 1/FE9200 Note 5 FT9080 Note 1/FT9085 Note 2 FI78K0 Note 1, 2 FD78K0 Note 1, 2 Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM (PC DOSTM) based 5 3. HP9000 series 300TM, HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based 4. PC-9800 series (MS-DOS+WindowsTM) based 5. IBM PC/AT (PC DOS + Windows) based 6. Under development Remarks 1. For third party development tools, see the 78K/0 Series Selection Guide (IF-1185). 2. RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used together with the DF78014.
5
58
PD78P014
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name Document No. (Japanese) Document No. (English) IEU-780 IEU-849 Basic I 78K/0 Series Application Notes Basic II Electronic Notebook IEA-715 IEA-740 IEA-744 IEU-1343 IEU-1372 IEA-1288 IEA-1299 IEA-1301
PD78014/78014Y Series User's Manual
78K/0 Series User's Manual Instructions
Development Tool Related Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler PG-1500 PROM Programmer PG-1500 Controller IE-78000-R IE-78000-R-BK SD78K/0 Screen Debugger Basic Reference Operation Language Document No. (Japanese) Document No. (English) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-651 EEU-704 EEU-810 EEU-867 EEU-852 EEU-816 EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 EEU-1291 EEU-1398 EEU-1427 EEU-1414 EEU-1413
Other Related Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on Semiconductor Devices Semiconductor Devices Quality Guarantee Guide Document No. (Japanese) Document No. (English) IEI-635 IEI-616 IEI-620 MEI-603 IEI-1213 IEI-1207 IEI-1209 MEI-1202
Caution The above related documents are subject to change without notice. For design purposes, etc., be sure to use the latest documents.
59
PD78P014
[MEMO]
60
PD78P014
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
61
PD78P014
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
FIP is a trademark of NEC Corporation. IEBus and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc.

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