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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78361A, 78362A
16/8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
PD78362A is provided with a high-speed, high-performance CPU and powerful operation functions. Unlike the
existing PD78328, PD78362A is also provided with a high-resolution PWM signal output function which substantially contributes to improving the performance of the inverter control. A PROM model, PD78P364A, is also available. Detailed functions, etc. are described in the following user's manual. Be sure to read the manual to design systems.
PD78362A User's Manual Hardware : U10745E PD78356 User's Manual Instruction : U12117E
FEATURES
* Internal 16-bit architecture, external 8-bit data bus * High-speed processing by pipeline control method and high- speed operating clock Minimum instruction execution time: 125 ns (internal clock: at 16 MHz, external clock: 8MHz) * Real-time pulse unit for inverter control * 10-bit resolution A/D converter: 8 channels * 8-/9-/10-/12-bit resolution variable PWM signal output function: 2 channels * Powerful serial interface: 2 channels * Internal memory : ROM RAM 32K bytes (PD78361A) 24K bytes (PD78362A) 2K bytes (PD78361A) 768 bytes (PD78362A)
APPLICATION EXAMPLES
* Inverter air conditioner * Factory automation fields, such as industrial robots and machine tools.
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic shrink DIP (750 mil) Internal ROM Mask ROM Mask ROM
PD78361ACW-xxx PD78362ACW-xxx
Remark xxx indicates a ROM code suffix.
Unless otherwise specified, the PD78362A is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Document No. U10098EJ2V0DS00 (2nd edition) Date Published August 1997 N Printed in Japan
The mark
shows major revised points.
(c)
1996
PD78361A, 78362A
78K/III Series Product Development
PD78372 subseries
Reinforced timer, A/D added (for control unit of automotive appliances)
PD78366A subseries
PD78361A PD78362A PD78P364A
Pulse output function for inverter control, expanded ROM, RAM
PD78363A PD78365A PD78366A PD78368A PD78P368A
(for inverter)
PD78356 subseries
(for camera, HDD)
PD78352A subseries
(for HDD)
A/D, D/A relative instruction added, expanded ROM, RAM
High-performance CPU, sum-of-products instruction added
Reinforced timer and A/D, expanded ROM and RAM
PD78334 subseries
(for control application in OA and FA fields)
PD78322 subseries
High-speed, multi-function, reinforced interrupt, 10-bit A/D
Pulse output function for inverter control
PD78328 subseries
(for inverter)
(for control application in OA and FA fields)
PD78312A subseries
(for control application in OA and FA fields)
2
PD78361A, 78362A
PIN CONFIGURATION (TOP VIEW)
* 64-pin plastic shrink DIP (750 mil)
PD78361ACW-xxx, 78362ACW-xxx
P57 P90 P91 P92 P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO04 P85/TO05 VSS P00/RTP0 P01/RTP1 P02/RTP2 P03/RTP3 VDD VSS X1 X2 RESET P04/PWM0 P05/PWM1/TCUD P06/TO40/TIUD P07/TCLRUD P30/TxD P31/RxD P32/SO/SB0 P33/SI/SB1 P34/SCK MODE P20/NMI P21/INTP0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 VSS VDD AVDD AVREF P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVSS P25/INTP4 P24/INTP3/TI P23/INTP2 P22/INTP1
Remark xxx indicates a ROM code suffix.
3
PD78361A, 78362A
P00-P07 P20-P25 P30-P34 P40-P47 P50-P57 P70-P77 P80-P85 P90-P92 RTP0-RTP3 NMI INTP0-INTP4 TI TIUD TCUD TCLRUD : Port0 : Port2 : Port3 : Port4 : Port5 : Port7 : Port8 : Port9 : Real-time Port : Nonmaskable Interrupt : Interrupt From Peripherals : Timer Input : Timer Input Up Down Counter : Timer Control Up Down Counter : Timer Clear Up Down Counter ANI0-ANI7 TXD RXD SI SO SB0, SB1 SCK PWM0, PWM1 MODE RESET X1, X2 AVDD AVSS AVREF VDD VSS : Analog Input : Transmit Data : Receive Data : Serial Input : Serial Output : Serial Bus : Serial Clock : Pulse Width Modulation Output : Mode : Reset : Crystal : Analog VDD : Analog VSS : Analog Reference Voltage : Power Supply : Ground
TO00-TO05, TO40 : Timer Output
4
PD78361A, 78362A
FUNCTIONAL OUTLINE
Item Minimum instruction execution time Internal memory ROM RAM Memory space General-purpose registers Number of basic instructions Instruction set
PD78361A
125 ns (internal clock: 16 MHz, external clock: 8 MHz)
PD78362A
32K bytes 2K bytes 64K bytes 8 bits x 16 x 8 banks 115 * * * * * *
24K bytes 768 bytes
16-bit transfer/operation Multiplication/division (16 bits x 16 bits, 32 bits / 16 bits) Bit manipulation String Sum-of-products operation (16 bits x 16 bits + 32 bits) Relative operation
I/O lines
Input I/O
14 (of which 8 are shared with analog input) 38 * 16-bit timer x 1 10-bit dead time timer x 3 16-bit compare register x 4 2 kinds of output mode can be selected Mode 0, set-reset output: 6 channels Mode 1, buffer output: 6 channels * 16-bit timer x 1 16-bit compare register x 1 * 16-bit timer x 1 16-bit capture register x 1 16-bit capture/compare register x 1 * 16-bit timer x 1 16-bit capture register x 2 16-bit capture/compare register x 1 * 16-bit timer x 1 16-bit compare register x 2 16-bit resolution PWM output: 1 channel Pulse outputs associated with real-time pulse unit: 4 lines 8-/9-/10-/12-bit resolution variable PWM output: 2 channels 10-bit resolution, 8 channels Dedicated baud rate generator UART: 1 channel Clocked serial interface/SBI: 1 channel * External: 6, internal: 14 (of which 2 are multiplexed with external) * 4 priority levels can be specified through software * 3 types of interrupt service modes selectable (vectored interrupt, macro service, and context switching) 64-pin plastic shrink DIP (750 mil) * Watchdog timer * Standby function (HALT and STOP modes) * PLL control circuit
Real-time pulse unit
Real-time output port PWM unit A/D converter Serial interface
Interrupt function
Package Others
5
PD78361A, 78362A
DIFFERENCES BETWEEN PD78362A AND PD78366A
Item Internal ROM RAM Input I/O lines I/O Serial Interface 38 Dedicated baud rate generator UART: 1 channel Clocked serial interface/SBI: 1 channel 49 Dedicated baud rate generator UART (with pin selection function): 1 channel Clocked serial interface/SBI: 1 channel Provided Provided * * In ordinary operation mode: MODE0, 1 = LL In ROM-less mode: MODE0, 1 = HH 786 bytes 2K bytes 14 (of which 8 are multiplexed with analog input) Product name ROM 24K bytes
PD78362A
32K bytes
PD78366A
External expansion function ROM-less mode MODE setting
None None Always set as follows: MODE = L
Package
64-pin plastic shrink DIP (750 mil)
80-pin plastic QFP (14 x 20 mm)
6
EXU Main RAM X2 RESET MODE
ALU
ROM/RAM X1
BCU
NMI PROGRAMMABLE INTERRUPT CONTROLLER SYSTEM CONTROL & BUS CONTROL & PREFETCH CONTROL
5
INTP
5
BLOCK DIAGRAM
4 &
GENERAL REGISTERS 128 x 8 & DATA MEMORY 128 x 8 ROM 24K x 8 32K x 8
TO MICRO SEQUENCE CONTROL MICRO ROM
7
TI
TIMER/COUNTER UNIT (REAL-TIME PULSE UNIT)
Peripheral RAM 512 x 8 1792 x 8
TIUD
TCUD
TCLRUD
SCK
SO/SB0
SI/B1 A/D CONVERTER
TxD
SERIAL INTERFACE (SBI) (UART)
RWM
WATCHDOG TIMER
PORT
RxD
2
8
8
3
6
8
5
6
8
8 ANI
P2
P0
P6
P5
P8
P7
P4
P3
3
2
AVSS
AVDD
PWM
AVREF
PD78361A, 78362A
Remark Internal ROM and RAM capacities differ depending on the product.
INTP2
RTP
4
REAL-TIME OUTPUT PORT
VDD VSS
7
PD78361A, 78362A
TABLE OF CONTENTS
1.
PIN FUNCTIONS ...................................................................................................................... 10
1.1 1.2 1.3 PORT PINS ..................................................................................................................................... 10 PINS OTHER THAN PORT PINS .................................................................................................. 11 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ....................................................... 12
2.
CPU ARCHITECTURE ............................................................................................................. 14
2.1 2.2 2.3 MEMORY SPACE ........................................................................................................................... 14 DATA MEMORY ADDRESSING .................................................................................................... 16 PROCESSOR REGISTERS ........................................................................................................... 18 2.3.1 2.3.2 2.3.3 Control Registers ................................................................................................................. 18 General-Purpose Registers .................................................................................................. 19 Special Function Registers (SFR) ........................................................................................20
3.
FUNCTIONAL BLOCKS ........................................................................................................... 26
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 EXECUTION UNIT (EXU) ............................................................................................................... 26 BUS CONTROL UNIT (BCU) ......................................................................................................... 26 ROM/RAM ....................................................................................................................................... 26 PORT FUNCTIONS ........................................................................................................................ 26 CLOCK GENERATOR CIRCUIT ................................................................................................... 28 REAL-TIME PULSE UNIT (RPU) .................................................................................................. 30 REAL-TIME OUTPUT PORT (RTP) .............................................................................................. 37 A/D CONVERTER .......................................................................................................................... 38 SERIAL INTERFACE ..................................................................................................................... 39
3.10 PWM UNIT ...................................................................................................................................... 41 3.11 WATCHDOG TIMER (WDT) .......................................................................................................... 42
4.
INTERRUPT FUNCTIONS ....................................................................................................... 43
4.1 4.2 4.3 OUTLINE ......................................................................................................................................... 43 MACRO SERVICE .......................................................................................................................... 44 CONTEXT SWITCHING ................................................................................................................. 47 4.3.1 4.3.2 4.3.3 Context Switching Function by Interrupt Request ................................................................ 47 Context Switching Function by BRKCS Instruction .............................................................. 48 Restoration from Context Switching ..................................................................................... 48
5. 6. 7. 8. 9.
STANDBY FUNCTIONS ...................................................................................................................... 49 RESET FUNCTION ................................................................................................................... 50 INSTRUCTION SET .................................................................................................................. 51 EXAMPLE OF SYSTEM CONFIGURATION ........................................................................... 65 ELECTRICAL SPECIFICATIONS ............................................................................................ 66
10. PACKAGE DRAWING .............................................................................................................. 75
8
PD78361A, 78362A
11. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 76 APPENDIX A. DIFFERENCES BETWEEN PD78362A AND PD78328 .................................. 77 APPENDIX B. TOOLS .................................................................................................................... 78
B.1 B.2 DEVELOPMENT TOOLS ............................................................................................................... 78 EMBEDDED SOFTWARE .............................................................................................................. 83
9
PD78361A, 78362A
1.
1.1
PIN FUNCTIONS
PORT PINS
I/O Function Port 0. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Shared by: RTP0-RTP3 PWM0 TCUD/PWM1 TIUD/TO40 TCLRUD Port 2. 6-bit input port. Input NMI INTP0 INTP1 INTP2 INTP3/TI INTP4 Port 3. 5-bit I/O port. Can be set in input or output mode in 1-bit units. TXD RXD SO/SB0 SI/SB1 SCK Port 4. 8-bit I/O Port. Can be set in input or output mode in 8-bit units. Port 5. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Port 7. 8-bit input port Port 8. 6-bit I/O port. Can be set in input or output mode in 1-bit units. Port 9. 3-bit I/O port. Can be set in input or output mode in 1-bit units. -
Pin name P00-P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P30 P31 P32 P33 P34 P40-P47
I/O
I/O
I/O
P50-P57
I/O
-
P70-P77
Input
ANI0-ANI7
P80-P85
I/O
TO00-TO05
P90-P92
I/O
-
10
PD78361A, 78362A
1.2 PINS OTHER THAN PORT PINS
I/O Output Function Real-time output port that outputs pulses in synchronization with trigger signal from real-time pulse unit. Non-maskable interrupt request input. External interrupt request input. Input Shared by: P00-P03 P20 P21 P22 P23 P24/TI P25 External count clock input to timer 1. Count operation selection control signal input to up/down counter (timer TCUD TIUD TCLRUD TO00-TO05 TO40 ANI0-ANI7 TXD RXD SCK SI SO SB0 I/O SB1 PWM0 Output PWM1 MODE RESET X1 X2 AVREF AVDD AVSS VDD VSS Input Input Input - Input - - - - PWM signal output. Control signal input to set operation mode. Connected to VSS. System reset input Crystal oscillator connecting pins for system clock. If a clock is externally supplied, input it to pin X1. Leave pin X2 open. A/D converter reference voltage input. A/D converter analog power supply. A/D converter GND. Positive power supply GND Serial data input/output of clocked serial interface in SBI mode. Input Output Input I/O Input Ouput Analog input to A/D converter. Serial data output of asynchronous serial interface. Serial data input of asynchronous serial interface. Serial clock input/output of clocked serial interface. Serial data input of clocked serial interface in 3-line mode. Serial data output of clocked serial interface in 3-line mode. Output Input 4). External count clock input to up/down counter (timer 4). Clear signal input to up/down counter (timer 4). Pulse output from real-time pulse unit. P05/PWM1 P06/TO40 P07 P80-P85 P06/TIUD P70-P77 P30 P31 P34 P33/SB1 P32/SB0 P32/SO P33/SI P04 P05/TCUD - - - - - - - - P24/INTP3
Pin name RTP0-RTP3 NMI INTP0 INTP1 INTP2 INTP3 INTP4 TI
11
PD78361A, 78362A
1.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
Table 1-1 shows the I/O circuit types of the respective pins, and recommended connections of the unused pins. Figure 1-1 shows the circuits of the respective pins.
Table 1-1. Pin I/O Circuit Type and Recommended Connections of Unused Pins
Pin P00/RTP0-P03/RTP3 P04/PWM0 P05/TCUD/PWM1 P06/TIUD/TO40 P07/TCLRUD P20/NMI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3/TI P25/INTP4 P30/TXD 5-A P31/RXD P32/SO/SB0 P33/SI/SB1 P34/SCK P40-P47 5-A P50-P57 P70/ANI0-P77/ANI7 P80/TO00-P85/TO05 5-A P90-P92 MODE RESET AVREF, AVSS AVDD - 1 - 2 Connect to VSS Connect to VDD 9 Connect to VSS Input : Independently connect to VDD or VSS through resistor 8-A Input : Independently connect to VDD or VSS through resistor Output : Open 2-A Connect to VSS 2 5-A Input : Independently connect to VDD or VSS through resistor Output : Open I/O circuit type Recommended connections
Output : Open
12
PD78361A, 78362A
Figure 1-1. Pin I/O Circuits
Type 1
VDD P-ch IN N-ch data output disable input enable
Type 5-A
pull-up enable VDD P-ch
VDD P-ch
IN/OUT N-ch
Type 2
Type 8-A
pull-up enable data VDD P-ch
VDD P-ch
IN
Schmitt trigger input with hysteresis characteristics
output disable
IN/OUT N-ch
Type 2-A
VDD
Type 9
Comparator IN P-ch pull-up enable P-ch N-ch + - Vref (Threshold voltage)
IN input enable
Schmitt trigger input with hysteresis characteristics
13
PD78361A, 78362A
2.
2.1
CPU ARCHITECTURE
MEMORY SPACE
The PD78362A can access a memory space of 64K bytes. Figure 2-1 and 2-2 show the memory map.
Figure 2-1. Memory Map (PD78361A)
MODE = L FFFFH Special function register (SFR) (256 x 8)
FF00H FEFFH
FEFFH FE80H FE25H FE06H
General-purpose register (128 x 8) Macro service control (32 x 8)
Main RAM (256 x 8) FF00H Data memory FDFFH Peripheral RAM (1792 x 8) F700H F6FFH
F700H
Data area (768 x 8)
Memory space (64 K x 8)
Cannot be used
7FFFH Program area 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLT instruction table area (64 x 8) Program memory Data memory Internal ROM (32768 x 8) 0040H 003FH Vector table area (64 x 8) 0000H 0000H CALLF instruction entry area (2048 x 8) Program area
8000H 7FFFH
Caution
For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address that specifies the operand must be an even value.
14
PD78361A, 78362A
Figure 2-2. Memory Map (PD78362A)
MODE = L FFFFH Special function register (SFR) (256 x 8)
FF00H FEFFH
FEFFH FE80H FE25H FE06H
General-purpose register (128 x 8) Macro service control (32 x 8)
Main RAM (256 x 8) FF00H Data memory FDFFH Peripheral RAM (512 x 8) FC00H FBFFH
FC00H
Data area (768 x 8)
Memory space (64 K x 8)
Cannot be used
5FFFH Program area 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLT instruction table area (64 x 8) Program memory Data memory Internal ROM (24576 x 8) 0040H 003FH Vector table area (64 x 8) 0000H 0000H CALLF instruction entry area (2048 x 8) Program area
6000H 5FFFH
Caution
For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address that specifies the operand must be an even value.
15
PD78361A, 78362A
2.2 DATA MEMORY ADDRESSING
The PD78362A is provided with many addressing modes that improve the operability of the memory and can be used with high-level languages. Especially, an area of addresses FC00H-FFFFH (F700H-FFFFH in the PD78361A) to which the data memory is mapped can be addressed in a mode peculiar to the functions provided in this area, including special function registers (SFR) and general-purpose registers.
Figure 2-3. Data Memory Addressing (PD78361A)
FFFFH Special function register (SFR)
FF20H FF1FH FF00H FEFFH
SFR addressing
General-purpose register FE80H FE7FH FE20H FE1FH Main RAM FE00H FDFFH Peripheral RAM F700H F6FFH Cannot be used 8000H 7FFFH Internal ROM
Register addressing
Short direct addressing
Direct addressing Register indirect addressing Based addressing Based indexed addressing Based indexed addressing (with displacement)
0000H
Caution
For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address that specifies the operand must be an even value.
16
PD78361A, 78362A
Figure 2-4. Data Memory Addressing (PD78362A)
FFFFH Special function register (SFR)
FF20H FF1FH FF00H FEFFH
SFR addressing
General-purpose register FE80H FE7FH FE20H FE1FH Main RAM FE00H FDFFH Peripheral RAM FC00H FBFFH Cannot be used 6000H 5FFFH Internal ROM
Register addressing
Short direct addressing
Direct addressing Register indirect addressing Based addressing Based indexed addressing Based indexed addressing (with displacement)
0000H
Caution
For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address that specifies the operand must be an even value.
17
PD78361A, 78362A
2.3 PROCESSOR REGISTERS * Control registers * General-purpose registers * Special function registers (SFRs) 2.3.1 Control Registers This is a 16-bit register that holds an address of the instruction to be executed next. (2) Program status word (PSW) This 16-bit register indicates the status of the CPU as a result of instruction execution. (3) Stack pointer (SP) This 16-bit register indicates the first address of the stack area (LIFO) of the memory.
The PD78362A is provided with the following three types of processor registers:
(1) Program counter (PC)
Figure 2-5. Configuration of Control Registers
15 PC PSW SP 0
Figure 2-6. Configuration of PSW
15 UF PSW 7 S Z UF S Z RSS AC IE P/V CY RSS AC IE P/V 0 CY RBS2 RBS1 RBS0 0 0 0 0 0 8
: User flag : Sign flag (MSB of execution result) : Zero flag : Register set select flag : Auxiliary carry flag : Interrupt request enable flag : Parity/overflow flag : Carry flag
RBS0-RBS2: Register bank select flag
18
PD78361A, 78362A
2.3.2 General-Purpose Registers
The PD78362A is provided with eight banks of general-purpose registers with one bank consisting of 8 words x 16 bits. Figure 2-7 shows the configuration of the general-purpose register banks. The general-purpose registers are mapped to an area of addresses FE80H-FEFFH. Each of these registers can be used as an 8bit register. In addition, two registers can be used as one 16-bit register pair (refer to Figure 2-8 ). These general-purpose registers facilitate complicated multitask processing.
Figure 2-7. Configuration of General-Purpose Register Banks
Bank 7
Bank 1 Bank 0 RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 15 0
Figure 2-8. Processing Bits of General-Purpose Registers
8-bit processing FEFFH RBNK0 RBNK1 RBNK2 RBNK3 RBNK4 RBNK5 RBNK6 FE80H RBNK7 7 R15 R13 R11 R9 R7 R5 R3 R1 07 R14 R12 R10 R8 R6 R4 R2 R0 0 16-bit processing
(FH) (DH) (BH) (9H) (7H) (5H) (3H) (1H)
RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0
(EH) (CH) (AH) (8H) (6H) (4H) (2H) (0H)
15
0
19
PD78361A, 78362A
2.3.3 Special Function Registers (SFR)
Special function registers (SFRs) are registers assigned special functions such as mode registers and control registers for internal peripheral hardware, and are mapped to a 256-byte address space at FF00H through FFFFH. Table 2-1 lists the SFRs. The meanings of the symbols in this table are as follows: * Symbol ................................... Indicates the mnemonic symbol for an SFR. This mnemonic can be coded in the operand field of an instruction. * R/W ........................................ Indicates whether the SFR can be read or written. R/W : Read/write R W : Read only : Write only
* Bit units for manipulation ...... Indicates bit units in which the SFR can be manipulated. The SFRs that can be manipulated in 16-bit units can be coded as an sfrp operand. Specify an even address for these SFRs. The SFRs that can be manipulated in 1-bit units can be coded as the operand of bit manipulation instructions. * On reset ................................. Indicates the status of the register at RESET input. Cautions 1. Do not access the addresses in the range FF00H-FFFFH to which no special function register is allocated. If these addresses are accessed, malfunctio ning may occur. 2. Do not write data to the read-only registers. Otherwise, the internal circuit may not operate normally. 3. When using read data as byte data, process undefined bit(s) first. 4. TOUT and TXS are write-only registers. Do no read these registers. 5. Bits 0, 1, and 4 of SBIC are write-only bits. When these bits are read, they are always "0".
20
PD78361A, 78362A
Table 2-1. List of Special Function Registers (1/5)
Bit units for manipulation 1 bit FF00H FF02H FF03H FF04H FF05H FF07H FF08H FF09H FF10H Compare register 00 FF11H FF12H Compare register 01 FF13H FF14H Compare register 02 FF15H FF16H Compare register 03 FF17H FF18H Buffer register CM00 FF19H FF1AH Buffer register CM01 FF1BH FF1CH Buffer register CM02 FF1DH FF1EH Timer register 0 FF1FH FF20H FF23H FF25H FF28H FF29H FF2CH Reload register FF2DH FF2EH FF2FH FF30H Compare register 10 FF31H FF32H Timer register 1 FF33H TM1 R - - 0000H CM10 - - Timer unit mode register 0 Timer unit mode register 1 TUM0 TUM1 R/W - - Undefined 00H DTIME - - Port 0 mode register Port 3 mode register Port 5 mode register Port 8 mode register Port 9 mode register PM0 PM3 PM5 PM8 PM9 R/W - - - - - TM0 R - - 0000H FFH xxx1 1111B FFH xx11 1111B xxxx x111B Undefined BFCM02 - - BFCM01 - - BFCM00 - - CM03 - - CM02 R/W - - CM01 - - Undefined CM00 - - Port 0 Port 2 Port 3 Port 4 Port 5 Port 7 Port 8 Port 9 P0 P2 P3 P4 P5 P7 P8 P9 R - R/W R/W R - 8 bits 16 bits - - - - - - - -
Address
Special function register (SFR)
Symbol
R/W
On reset
21
PD78361A, 78362A
Table 2-1. List of Special Function Registers (2/5)
Bit units for manipulation 1 bit FF34H Capture/compare register 20 FF35H Undefined FF36H Capture register 20 FF37H R FF38H Timer register 2 FF39H FF3AH Buffer register CM03 FF3BH FF3CH FF3DH FF40H FF43H FF44H FF45H FF48H FF4EH FF4FH FF50H Capture/compare register 30 FF51H FF52H Capture register 30 FF53H FF54H Capture register 31 FF55H FF56H Timer register 3 FF57H FF58H Compare register 40 FF59H R/W FF5AH Compare register 41 FF5BH FF5CH Timer register 4 FF5DH FF5EH FF5FH FF60H FF61H FF62H FF68H Timer control register 4 Timer out register Real-time output port register Real-time output port mode register Port read control register A/D converter mode register TMC4 TOUT RTP RTPM R/W PRDC ADM - - 00H R/W W - - - - - - 00H xx01 0101B Undefined TM4 R - - 0000H CM41 - - Undefined CM40 - - TM3 - - 0000H CT31 R - - CT30 - - Undefined CC30 - - External interrupt mode register 0 External interrupt mode register 1 Port 0 mode control register Port 3 mode control register Pull-up resistor option register L Pull-up resistor option register H Port 8 mode control register Sampling control register 0 Sampling control register 1 INTM0 INTM1 PMC0 PMC3 PUOL PUOH PMC8 SMPC0 SMPC1 R/W - - - - - 00H - - - 00H - xx00 0000B xxx0 0000B 00H BFCM03 - - Underfined TM2 - - 0000H CT20 - - CC20 R/W - - 8 bits 16 bits
Address
Special function register (SFR)
Symbol
R/W
On reset
22
PD78361A, 78362A
Table 2-1. List of Special Function Registers (3/5)
Bit units for manipulation 1 bit FF70H FF71H FF72H FF73H FF74H FF75H FF76H FF77H FF78H FF79H FF7AH FF7BH FF7CH FF7DH FF7EH FF7FH FF80H FF82H FF84H FF85H FF86H FF88H FF8AH FF8CH FF8EH FFA0H FFA1H FFA2H FFA2H PWM register 0 FFA3H PWM0 - - Slave buffer register 0 Slave buffer register 1 Slave buffer register 2 Slave buffer register 3 Slave buffer register 4 Slave buffer register 5 Master buffer register 0 Master buffer register 1 Master buffer register 2 Master buffer register 3 Master buffer register 4 Master buffer register 5 Timer control register 0 Timer control register 1 Timer control register 2 Timer control register 3 Clocked serial interface mode register Serial bus interface control register Baud rate generator control register Baud rate generator compare register Serial I/O shift register Asynchronous serial interface mode register Asynchronous serial interface status register Serial receive buffer: UART Serial transfer shift register: UART PWM control register 0 PWM control register 1 PWM register 0L SBUF0 SBUF1 SBUF2 SBUF3 SBUF4 SBUF5 MBUF0 MBUF1 MBUF2 MBUF3 MBUF4 MBUF5 TMC0 TMC1 TMC2 TMC3 CSIM SBIC BRGC BRG SIO ASIM ASIS RXB TXS PWMC0 PWMC1 PWM0L R/W R W - - - R/W - R/WNote R/W 8 bits 16 bits - - - - - - Undefined - - - - - - - - - - - - - - Undefined - - - - Undefined - - 00H - - Undefined 80H 00H 00H
Address
Special function register (SFR)
Symbol
R/W
On reset
Note
Bits 7 and 5
: read/write
Bits 6, 3, and 2 : read-only Bits 4, 1, and 0 : write-only
23
PD78361A, 78362A
Table 2-1. List of Special Function Registers (4/5)
Bit units for manipulation 1 bit FFA4H FFA4H PWM register 1 FFA5H FFA8H FFAAH FFACH FFACH Interrupt mask register 0 FFADH FFADH FFB0H A/D conversion result register 0 FFB1H FFB1H FFB2H A/D conversion result register 1 FFB3H FFB3H FFB4H A/D conversion result register 2 FFB5H FFB5H FFB6H A/D conversion result register 3 FFB7H R FFB7H FFB8H A/D conversion result register 4 FFB9H FFB9H FFBAH A/D conversion result register 5 FFBBH FFBBH FFBCH A/D conversion result register 6 FFBDH FFBDH FFBEH A/D conversion result register 7 FFBFH FFBFH FFC0H FFC2H A/D conversion result register 7H Standby control register Watchdog timer mode register ADCR7H STBCNote WDMNote R/W - - - - - - 0000 x000B 00H ADCR7 - - A/D conversion result register 6H ADCR6H - - ADCR6 - - A/D conversion result register 5H ADCR5H - - ADCR5 - - A/D conversion result register 4H ADCR4H - - ADCR4 - - A/D conversion result register 3H ADCR3H - - Undefined ADCR3 - - A/D conversion result register 2H ADCR2H - - ADCR2 - - A/D conversion result register 1H ADCR1H - - ADCR1 - - A/D conversion result register 0H ADCR0H - - ADCR0 - - Interrupt mask register 0H MK0H - FFH MK0 In-service priority register Interrupt mode control register Interrupt mask register 0L ISPR IMC MK0L R/W - - FFFFH R - - - 00H 80H FFH PWM1 PWM register 1L PWM1L R/W - - 8 bits 16 bits - Undefined
Address
Special function register (SFR)
Symbol
R/W
On reset
Note
Can be written when a special instruction is executed.
24
PD78361A, 78362A
Table 2-1. List of Special Function Registers (5/5)
Bit units for manipulation 1 bit FFC4H FFC6H Programmable wait control register FFC7H FFE0H FFE1H FFE2H FFE3H FFE4H FFE5H FFE6H FFE7H FFE8H FFE9H FFEAH FFEBH FFECH FFEDH FFEEH FFEFH Interrupt control register (INTOV3) Interrupt control register (INTP0/INTCC30) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3/INTCC20) Interrupt control register (INTP4) Interrupt control register (INTTM0) Interrupt control register (INTCM03) Interrupt control register (INTCM10) Interrupt control register (INTCM40) Interrupt control register (INTCM41) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTAD) OVIC3 PIC0 PIC1 PIC2 PIC3 PIC4 TMIC0 CMIC03 CMIC10 CMIC40 CMIC41 SERIC SRIC STIC CSIIC ADIC - - - - - - PWC - - C0AAH Memory expansion mode register MM 8 bits 16 bits - Note
Address
Special function register (SFR)
Symbol
R/W
On reset
R/W
- - 43H - - - - - - - -
Note
The value of the MM register on reset differs depending on the product.
PD78361A **** 20H PD78362A **** 60H
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PD78361A, 78362A
3.
3.1
FUNCTIONAL BLOCKS
EXECUTION UNIT (EXU)
EXU controls address computation, arithmetic and logical operations, and data transfer through microprogram. EXU has an internal main RAM. This RAM can be accessed by instructions faster than the peripheral RAM. 3.2 BUS CONTROL UNIT (BCU)
BCU starts necessary bus cycles according to the physical address obtained by the execution unit (EXU).If EXU does not request start of the bus cycle, an address is generated to prefetch an instruction. The prefetched op code is stored in an instruction queue. 3.3 ROM/RAM
Internal ROM and RAM capacities differ depending on the product. The PD78361A has a 32K-byte ROM and a 1792-byte peripheral RAM. The PD78362A has a 24K-byte ROM and a 512-byte peripheral RAM. 3.4 PORT FUNCTIONS
The PD78362A is provided with the ports shown in Figure 3-1 for various control operations. The functions of each port are listed in Table 3-1. These ports function not only as digital ports but also as input/output lines of the internal hardware.
Figure 3-1. Port Configuration
P00
P50
Port 0
Port 5
P07 P20 Port 2 P25 P30 Port 3 P34
P57
P70-P77
8
Port 7
P80 Port 8 P85 P90 Port 9
Port 4
8
P40-P47
P92
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PD78361A, 78362A
Table 3-1. Functions of Each Port
Port Port function 8-bit I/O port. Can be set in input or output mode in 1-bit units. Multiplexed function In control mode, serves as real-time output port (RTP), or input operation control signal of real-time pulse unit (RPU) and output PWM signal. Inputs external interrupt and count pulse of real-time pulse unit (RPU) (fixed to the control mode). In control mode, inputs/outputs signals of serial interfaces (UART, CSI). --
Port 0
Port 2
6-bit input port.
Port 3
5-bit I/O port. Can be set in input or output in 1-bit units. 8-bit I/O port. Can be set in input or output mode in 8-bit units. 8-bit I/O port. Can be set in input or output mode in 1-bit units. 8-bit input port.
Port 4
Port 5 Port 7
-- Input analog signals to A/D converter (fixed to the control mode). In control mode, outputs timer of real-time pulse unit (RPU).
Port 8
6-bit I/O port. Can be set in input or output mode in 1-bit units. 3-bit I/O port. Can be set in input or output mode in 1-bit units.
Port 9
--
27
PD78361A, 78362A
3.5 CLOCK GENERATOR CIRCUIT
The clock generator circuit generates and controls the internal system clock (CLK) that is supplied to the CPU.
Figure 3-2. Block Diagram of Clock Generator Circuit
X1 Frequency divider fXX or fX 1/2 PLL control circuit Frequency divider 1/2 fCLK Internal system clock (CLK)
X2
System cloock oscillator circuit
STOP mode
Remarks 1. 2. 3.
fXX : crystal oscillation frequency fX : external clock frequency fCLK : internal system clock frequency
By connecting an 8-MHz crystal resonator across the X1 and X2 pins, an internal system clock of up to 16 MHz (fCLK) can be generated. The system clock oscillation circuit oscillates by using the crystal resonator connected across the X1 and X2 pins. It stops oscillation in standby mode. An external clock can also be input. To do so, input the clock signal to the X1 pin and leave the X2 pin open. Caution Do not set STOP mode when the external clock is used.
28
PD78361A, 78362A
Figure 3-3. External Circuit of System Clock Oscillator Circuit
(a) crystal oscillator
PD78362A
VSS X1 X1
(b) external clock
PD78362A
X2
Open X2
Cautions 1. Wire the portion enclosed by dotted line in Figure 3-3 as follows to avoid adverse influences due to wiring capacity when using the system clock oscillation circuit. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal line. Make sure that the wiring is not close to lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground the circuit to a ground pattern through which a high current flows. * Do not extract signals from the oscillator circuit. 2. To input an external clock, do not connect a load such as wiring capacitance to the X2 pin.
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PD78361A, 78362A
3.6 REAL-TIME PULSE UNIT (RPU)
The real-time pulse unit (RPU) can measure pulse intervals and frequencies, and output programmable pulses (six channels of PWM control signals). The RPU consists of five 16-bit timers (timers 0 through 4), of which one is provided with a 10-bit dead time timer, which is ideal for inverter control. In addition, a function to turn off the output by the software or an external interrupt is also provided. Each timer has the following features: * Timer 0 : Controls the PWM period of the TO00 through TO05 pins. In addition, operates as a general-purpose interval timer. Timer 0 has the following five operation modes: General-purpose interval timer mode PWM mode 0 (symmetrical triangular wave) PWM mode 0 (asymmetrical triangular wave) PWM mode 0 (saw-tooth wave) PWM mode 1 * * * Timer 1 : Operates as a general-purpose interval timer. Timers 2 & 3 : Has a programmable input sampling circuit that rejects the noise of an input signal, and a capture function. Timer 4 : Operates as a general-purpose timer or an up-down counter. When operating as a generalpurpose timer, controls the PWM cycle of the TO40 output pin. Timer 4 has the following two operation modes: General-purpose timer mode Up/down counter mode (UDC mode) The RPU consists of the hardware shown in Table 3-2. Figures 3-4 through 3-12 show the block diagrams of the respective timers.
Table 3-2. Configuration of Real-Time Pulse Unit (RPU)
Timer register Register 16-bit compare register (CM00) Timer 0 16-bit timer (TM0) 16-bit compare register (CM01) 16-bit compare register (CM02) 16-bit compare register (CM03) Timer 1 16-bit timer (TM1) Timer 2 16-bit timer (TM2) 16-bit compare register (CM10) 16-bit capture/compare register (CC20) 16-bit capture register (CT20) 16-bit capture/compare register (CC30) Timer 3 16-bit timer (TM3) 16-bit capture register (CT30) 16-bit capture register (CT31) Timer 4 16-bit timer (TM4) 16-bit compare register (CM40) 16-bit compare register (CM41) Compare register coincidence interrupt - - - INTCM03 INTCM10 INTCC20 - INTCC30 - - INTCM40 INTCM41 INTP3 INTP0 INTP1 INTP4 - 1 TCLRUD INTCM40 - INTCC30 - INTCC20 - - INTCM10 Capture trigger Timer output Timer clear
-
6
INTCM03
30
PD78361A, 78362A
Figure 3-4. Block Diagram of Timer 0 (PWM mode 0 ... symmetrical triangular wave, asymmetrical triangular wave)
BFCM03 CM03 16 TM0 U/D 16 INTTM0 UP = 0 DOWN = 1 INTCM03
fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16
fCLK
DTIME
ALVTO Output off function by external interrupt and software Underflow R S R TO00 (U phase) TO01 (U phase)
BFCM00 CM00 R
10
DTM0 S
BFCM01 CM01 R DTM1 S Underflow
S
R S R
TO02 (V phase) TO03 (V phase)
BFCM02 CM02 R DTM2 S Underflow
S
R S R S
TO04 (W phase) TO05 (W phase)
TM0 CM00-CM03 DTIME DTM0-DTM2
: Timer register : Compare registers : Reload register : Dead time timers
ALVT0 : Bit 2 of TUM0 register U/D N : Bit 3 of TMC0 register
BFCM00-BFCM03 : Buffer registers
Remark fCLK: internal system clock
31
PD78361A, 78362A
Figure 3-5. Block Diagram of Timer 0 (PWM mode 0 ... saw-tooth wave)
BFCM03 CM03 16 TM0 fCLK 16 10 CM00 R DTM0 S Underflow R S R BFCM01 CM01 R DTM1 S Underflow R S R BFCM02 CM02 R DTM2 S Underflow R S R S TO04 (W phase) TO05 (W phase) S TO02 (V phase) TO03 (V phase) S TO00 (U phase) TO01 (U phase) Output off function by external interrupt and software DTIME ALVTO Clear INTCM03
fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16
BFCM00
TM0 CM00-CM03 DTIME DTM0-DTM2 ALVT0
: Timer register : Compare registers : Reload register : Dead time timers : Bit 2 of TUM0 register
BFCM00-BFCM03 : Buffer registers
Remark fCLK: internal system clock
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PD78361A, 78362A
Figure 3-6. Block Diagram of Timer 0 (PWM mode 1)
BFCM03 CM03 16 fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16 TM0 fCLK 16 10 BFCM00 CM00 T DTM0 6-bit buffer register Underflow SBUF1 MBUF0 SBUF0 MBUF3 SBUF3 MBUF2 BFCM01 CM01 T DTM1 Underflow SBUF2 MBUF5 SBUF5 MBUF4 SBUF4 6-bit buffer register MBUF1 DTIME Clear INTCM03
BFCM02 CM02 T DTM2
Underflow TOUT 6-bit write-only register Output off function by external interrupt and software
TO00 TO02 TO04 (U phase) (V phase) (W phase) TO01 TO03 TO05 (U phase) (V phase) (W phase)
TM0 CM00-CM03 DTIME DTM0-DTM2
: Timer register : Compare registers : Reload register : Dead time timers
MBUF0-MBUF5 : Master buffer registers SBUF0-SBUF5 : Slave buffer registers TOUT : Timer out register
BFCM00-BFCM03 : Buffer registers
Remark fCLK: internal system clock
33
PD78361A, 78362A
Figure 3-7. Block Diagram of Timer 0 (general-purpose interval timer mode)
Master buffer register (MBUF0) Compare register CM03 INTCM03
6
16
Slave buffer register (SBUF0)
Timer register TM0
6
Clear
Timer out register (TOUT)
Output off function by external interrupt and software TO00 TO02 TO04 TO01 TO03 TO05
Figure 3-8. Block Diagram of Timer 1
Clear
fCLK/4 fCLK/8 fCLK/16 TI
Timer register TM1 16 Compare register CM10 INTCM10
Remark fCLK: internal system clock
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PD78361A, 78362A
Figure 3-9. Block Diagram of Timer 2
Clear fCLK/22 fCLK/23 fCLK/24 fCLK/25 fCLK/26 fCLK/28 fCLK/29 fCLK/210 4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 fCLK/26 fCLK/27 fCLK/28 CLR2
Timer register TM2
16 Capture/compare register CC20
INTP3
INTP3/INTCC20
Capture register CT20
Remark fCLK: internal system clock
Figure 3-10. Block Diagram of Timer 3
Clear fCLK/22 fCLK/23 fCLK/24 fCLK/25 fCLK/26 fCLK/28 CLR3
Timer register TM3
INTOV3
16 4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 INTP1 4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 INTP4 4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 Capture register CT31 INTP4 Capture register CT30 INTP1 Capture/compare register CC30
INTP0
INTP0/INTCC30
Remark fCLK: internal system clock
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PD78361A, 78362A
Figure 3-11. Block Diagram of Timer 4 (General-Purpose Timer Mode)
Clear f CLK f CLK/2 f CLK/4 f CLK/8 f CLK/16 f CLK/32
Timer register TM4 INTCM40 16 Compare register CM40 ALV40 S R Compare register CM41 Q TO40
INTCM41
Remark fCLK: internal system clock
Figure 3-12. Block Diagram of Timer 4 (UDC Mode)
Clear TCLRUD
f CLK/4 f CLK/8 f CLK/16
Timer register TM4 16
OVF UDF
TIUD TCUD
Up/down detector
Compare register CM40
INTCM40
Compare register CM41
INTCM41
Remark fCLK: internal system clock
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PD78361A, 78362A
3.7 REAL-TIME OUTPUT PORT (RTP)
The real-time output port is a 4-bit port that can output the contents of the real-time output port register (RTP) in synchronization with the trigger signal from the real-time pulse unit (RPU). It can output synchronization pulses of multiple channels. Also, PWM modulation can be applied to P00-P03.
Figure 3-13. Block Diagram of Real-Time Output Port
Internal bus
4
RTP INTCM03 (from RPU) INTCM10 (from RPU) INTP0/INTCC30 (from RPU) Software trigger
Output trigger control circuit
4
RTPM
PWM0 PWM1
PWM signal control circuit
Output latch (P03-P00)
P03P02 P01P00
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PD78361A, 78362A
3.8 A/D CONVERTER
The PD78362A contains a high-speed, high-resolution 10-bit analog-to-digital (A/D) converter (conversion time 12.6s at an internal clock frequency of 16 MHz). Successive approximation type is adopted. This converter is provided with eight analog input lines (ANI0-ANI7) and can perform various operations as the application requires, in select, scan, and mixed modes. When A/D conversion ends, an internal interrupt (INTAD) occurs. This interrupt can start a macro service that executes automatic data transfer through hardware.
Figure 3-14. Block Diagram of A/D Converter
ANI0 ANI1
Sample & hold Resistor string
AVDD AVREF
ANI3 ANI4 ANI5
Input curcuit
ANI2
AVSS 9 Comparator 0 SAR (10) 10 9 ADCR0 ADCR1 0 10
ANI6 ANI7
INTCM03 INTP2 (Start trigger)
Controller
ADCR2 ADCR3 ADCR4 ADCR5
ADM (8) ADCR6 8 ADCR7 10 Internal bus
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PD78361A, 78362A
3.9 SERIAL INTERFACE
The PD78362A is provided with the following two independent serial interfaces:
* Asynchronous serial interface (UART) * Clocked serial interface
* 3-line serial I/O mode * Serial bus interface mode (SBI mode) Since the PD78362A contains a baud rate generator (BRG), any serial transfer rate can be set regardless of the operating clock frequency. The baud rate generator is a block to generate the shift clock for the transmit/ receive serial interface, and is used commonly with the two channels of the serial interfaces. The serial transfer rate can be selected in a range of 110 bps to 38.4 Kbps by the mode register.
Figure 3-15. Block Diagram of Asynchronous Serial Interface
Internal bus
ASIM Receive RXB buffer RXE PS1 PS0 CL SL SCK
ASIS RXD
Receive shift register
PE FE OVE
TXS
Transfer shift register
TXD Receive control parity check INTSER INTSR Transfer control parity append INTST
Selector
1 -- 16
1 -- 16
Transfer/ receive baud rate generator output fCLK/8
39
PD78361A, 78362A
Figure 3-16. Block Diagram of Clocked Serial Interface
Internal bus 8 CSIM CTXE CRXE WUP MOD2 MOD1 MOD0 CLS1 CLS0 8 8 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT CMDT 7
Selector
MOD1 MOD2 SI/SB1
0 Shift register (SIO) DQ
SO latch
SO/SB0
Busy/ acknowledge detector circuit
MOD1 MOD2
Selector
MOD1 Bus release/ command/ acknowledge detector circuit
WUP Interrupt signal generation control circuit
SCK
Serial clock counter
INTCSI
Serial clock control circuit CLS0 CLS1
Figure 3-17. Block Diagram of Baud Rate Generator
Internal bus
7 BRG
0
7 BRGC
Selector
1/2
Baud rate generator (BRG) fCLK/8 fCLK/32
0
1 -- 2
Coincidence
Clear TMBRG Prescaler fCLK/2
Serial interface
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PD78361A, 78362A
3.10 PWM UNIT
The PD78362A is provided with two lines that output 8-/9-/10-/12-bit resolution variable PWM signals. The PWM output can be used as a digital-to-analog conversion output by connecting an external lowpass filter, and ideal for controlling actuators such as motors. An output of between 244 Hz and 62.5 kHz can be obtaind, depending on the combination of the count clock (62.5 ns to 1 s) and counter bit length (8, 9, 10, or 12) (at an internal clock frequency of 16 MHz).
Figure 3-18. Block Diagram of PWM Unit
7 8 9 Overflow Counter (12) 11 S 0-7 0-8 0-9 Coincidence
fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16
ALVn
Q PWMn
R
Comparator (12)
0-11
Compare register CMPn (12)
PWM buffer register n (12)
Remark n = 0, 1
41
PD78361A, 78362A
3.11 WATCHDOG TIMER (WDT)
The watchdog timer is a free running timer equipped with a non-maskable interrupt function to prevent program hang-up or deadlock. An error of the program can be seen by the occurrence of the overflow interrupt (INTWDT) of the watchdog timer.
Figure 3-19. Block Diagram of Watchdog Timer
fCLK/29 fCLK/211 fCLK/213 Oscillation stabilization time control circuit Watchdog timer (8 bits) Overflow INTWDT
Clear WDT CLR WDT STOP
42
PD78361A, 78362A
4.
4.1
INTERRUPT FUNCTIONS
OUTLINE
The PD78362A is provided with powerful interrupt functions that can service interrupt requests from the internal hardware peripherals and external sources. In addition, the following three interrupt service modes are available. In addition, four levels of interrupt priority can be specified. * Vectored interrupt service * Macro service * Context switching
Table 4-1. Interrupt Sources
Interrupt source Type
Note
Name Trigger NMI pin input Watchdog timer Overflow of timer 3 - - 0 NMI INTWDT INTOV3
Source unit
Vector table address 0002H
Macro service
Context switching
Nonmaskable
External WDT RPU External/RPU External
None 0004H 0006H 0008H 000AH 000CH External/RPU External 000EH 0010H 0012H 0014H RPU 8 9 10 11 12 13 14 15 - INTCM10 INTCM40 INTCM41 INTSER INTSR INTST INTCSI INTAD BRK BRKCS TRAP RESET CM10 coincidence signal CM40 coincidence signal CM41 coincidence signal Receive error of UART End of UART reception End of UART transfer End of CSI transfer/reception End of A/D conversion BRK instruction BRKCS instruction Illegal op code trap Reset input CSI A/D - - - - UART 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 003EH - None 003CH Provided
None
1 INTP0/INTCC30 INTP0 pin input/CC30 coincidence signal 2 3 4 5 6 Maskable 7 INTP1 INTP2 INTP1 pin input INTP2 pin input
INTP3/INTCC20 INTP3 pin input/CC20 coincidence signal INTP4 INTTM0 INTCM03 INTP4 pin input Underflow of timer 0 CM03 coincidence signal
Provided
None Provided
Software - Exception Reset - -
None 0000H
Note Default priority : Priority that takes precedence when two or more maskable interrupts occur at the same time. 0 is the highest priority, and 15 is the lowest.
43
PD78361A, 78362A
4.2 MACRO SERVICE
The PD78362A has a total of five macro services. Each macro service is described below. (1) Counter mode: EVTCNT * Operation (a) Increments or decrements an 8-bit macro service counter (MSC). (b) A vectored interrupt request is generated when MSC reaches 0.
MSC
+1/-1
* Application example: As event counter, or to measure number of times a value is captured (2) Block transfer mode: BLKTRS * Operation (a) Transfers data block between a buffer and a SFR specified by SFR pointer (SFRP). (b) The transfer source and destination can be in SFR or buffer area. The length of the transfer data can be specified to be byte or word. (c) The number of times the data is to be transferred (block size) is specified by MSC. (d) MSC is auto decremented by one each time the macro service has been executed. (e) When MSC reaches 0, a vectored interrupt request is generated.
SFRP -1 MSC
Buffer N
Buffer 1
SFR
Internal bus
* Application example: To transfer/receive data through serial interface
44
PD78361A, 78362A
(3) Block transfer mode (with memory pointer): BLKTRS-P * Operation This is the block transfer mode in (2) above with a memory pointer (MEMP). The appended buffer area of MEMP can be freely set on the memory space. Remark Each time the macro service is executed, MEMP is auto incremented (by one for byte data transfer and by two for word data transfer).
Buffer N
SFRP -1 MSC MEMP
+1/+2
Buffer 1
SFR
Internal bus
* Application example: Same as (2) (4) Data differential mode: DTADIF * Operation (a) Calculates the difference between the contents of SFR (current value) specified by SFRP and the contents of SFR saved to the last data buffer (LDB). (b) Stores the result of the calculation in a predetermined buffer area. (c) Stores the contents of the current value of the SFR in LDB. (d) The number of times the data is to be transferred (block size) is specified by MSC. Each time the macro service is executed, MSC is auto decremented by one. (e) When MSC reaches 0, a vector interrupt request is generated. Remark The differential calculation can be carried out only with 16-bit SFRs.
SFRP -1 MSC LDB Buffer N SFR
Buffer 1
Differential calculation
Internal bus
* Application example : To measure cycle and pulse width by the capture register of the real-time pulse unit (RPU)
45
PD78361A, 78362A
(5) Data differential mode (with memory pointer): DTADIF-P * Operation This is the data differential mode in (4) above with memory pointer (MEMP). By appending MEMP, the buffer area in which the differential data is to be stored can be set freely on the memory space. Remarks 1. 2. The differential calculation can be carried out only with 16-bit SFRs. The buffer is specified by the result of operation by MEMP and MSCNote. MEMP is not updated after the data has been transferred. Note MEMP - (MSC x 2) + 2
SFRP Buffer N -1 MSC LDB MEMP Buffer 1 Differential calculation SFR
Internal bus
* Application example: Same as (4)
46
PD78361A, 78362A
4.3 CONTEXT SWITCHING
This function is to select a specific register bank through the hardware, and to branch execution to a vector address predetermined in the register bank. At the same time, it saves the present contents of the PC and PSW to the register bank when an interrupt occurs, or when the BRKCS instruction is executed. 4.3.1 Context Switching Function by Interrupt Request
When a context switching enable flag corresponding to each maskable interrupt request is set to 1 in the EI (interrupt enable) status, the context switching function can be started. The context switching operation by an interrupt request is performed as follows: (1) When an interrupt request is generated, a register bank to which the context is to be switched is specified by the contents of the lower 3 bits of the row address (even address) of the corresponding vector table. (2) A predetermined vector address is transferred to the PC in the register bank to which the context is to be switched, and the contents of the PC and PSW immediately before the switching takes place are saved to the register bank. (3) Execution branches to an address indicated by the contents of the PC newly set.
Figure 4-1. Operation of Context Switching
Registor Bank RP0 PC RP1 Exchange RP2 Save PSW RP5 RP6 RP7 RP3 RP4
Registor Bank (0-7)
47
PD78361A, 78362A
4.3.2 Context Switching Function by BRKCS Instruction
The context switching function can be started by the BRKCS instruction. The operation of context switching by an interrupt request is as follows: (1) An 8-bit register is specified by the operand of the BRKCS instruction, and the register bank to which the context is to be switched is specified by the contents of this register (only the lower 3 bits of 8 bits are valid). (2) The vector address predetermined in the register bank to which the context is to be switched is transferred to the PC, and at the same time, the contents of the PC and PSW immediately before the switching takes place are saved to the register bank. (3) Execution branches to the contents of the PC newly set. 4.3.3 Restoration from Context Switching
To restore from the switched context, one of the following two instructions are used. Which instruction is to be executed is determined by the source that has started the context switching.
Table 4-2. Instructions to Restore from Context Switching
Restore instruction RETCS RETCSB Context switching starting source Occurrence of interrupt Execution of BRKCS instruction
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PD78361A, 78362A
5. STANDBY FUNCTIONS
The PD78362A is provided with standby functions to reduce the power consumption of the system. The standby functions can be effected in the following two modes: * HALT mode ..... In this mode, the operating clock of the CPU is stopped. By using this mode in combination with an ordinary operation mode, the PD78362A operates intermittently to reduce the total power consumption of the system. * STOP mode .... In this mode, the oscillator is stopped, and therefore the entire system is stopped. Therefore, power consumption can be minimized with only a leakage current flowing. Each mode is set through software. Figure 5-1 shows the transition of the status in the standby modes (STOP and HALT modes).
Figure 5-1. Transition of Standby Status
Ordinary
RE
se
d
SE
lea
T
re
re lea
T
se
t
HA
SE
se
OP
LT
RE
d
ST
se
Un rru nte di s ske cur ma oc pt
t
STOP
NM
I
HALT
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PD78361A, 78362A
6. RESET FUNCTION
When a low level is input to the RESET pin, the system is reset, and each hardware enters the initial status (reset status). When the RESET pin goes high, the reset status is released, and program execution is started. Initialize the contents of each register through program as necessary. Especially, change the number of cycles of the programmable wait control register as necessary. The RESET pin is equipped with a noise rejecter circuit of analog delay to prevent malfunctioning due to noise. Caution While the RESET pin is active (low level), all the pins go into a high-impedance state (except AVREF, AVDD, AVSS, VDD, VSS, X1, and X2 pins).
Figure 6-1. Accepting Reset Signal
RESET input
Analog delay
Analog delay
Analog delay
Rejected as noise
Reset accepted
Reset released
To effect reset on when power is applied, make sure that sufficient time elapses to stabilize the oscillation after the power is applied until the reset signal is accepted, as shown in Figure 6-2.
Figure 6-2. Reset on Power Application
VDD
RESET Oscillation stabilization time
Analog delay Reset released
50
PD78361A, 78362A
7. INSTRUCTION SET
Describe an operand in the operand field of each instruction according to the description method of the instruction (for details, refer to the Assembler Specifications). Some instructions have two or more operands. Select one of them. Uppercase characters, +, -, #, $, !, [, and ] are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. To describe a label, be sure to describe #, $, !, [, or ].
Table 7-1. Operand Representation and Description
Representation r r1 r2 rp rp1 rp2 sfr sfrp Description R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15 R0, R1, R2, R3, R4, R5, R6, R7 C, B RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7 RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7 DE, HL, VP, UP Special function register symbol (Refer to Table 2-1.) Special function register symbol (register that can be manipulated in 16-bit units. Refer to Table 2-1.) RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7 (More than one symbol can be described. However, RP5 can be described only for PUSH and POP instructions, and PSW can be described only for PUSHU and POPU instructions.) [DE], [HL], [DE +], [HL +], [DE -], [HL -], [VP], [UP] [DE + A], [HL + A], [DE + B], [HL + B], [VP + DE], [VP + HL] [DE + byte], [HL + byte], [VP + byte], [UP + byte], [SP + byte] word[A], word[B], word[DE], word[HL] ; ; ; ; register indirect mode based indexed mode based mode indexed mode
post
mem
saddr saddrp $ addr16 ! addr16
FE20H-FF1FH immediate data or label FE20H-FF1EH immediate data (however, bit0 = 0) or label (manipulated in 16-bit units) 0000H-FDFFH immediate data or label; relative addressing 0000H-FDFFH immediate data or label; immediate addressing (However, up to FFFFH can be described for MOV instruction. Only FE00H-FEFFH can be described for MOVTBLW instruction.) 800H-FFFH immediate data or label 40H-7EH immediate data (however, bit0 = 0)Note or label 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label 3-bit immediate data (0-7)
addr11 addr5 word byte bit n
Note Do not access bit0 = 1 (odd address) in word units. Remarks 1. 2. 3. rp and rp1 are the same in terms of register name that can be described but are different in code to be generated. r, r1, rp, rp1, and post can be described in absolute name (R0-R15, RP0-RP7) and function name (X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, and UP). Immediate addressing can address the entire space. Relative addressing can address only a range of -128 to +127 from the first address of the next instruction.
51
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S r1, #byte saddr, #byte sfrNote , r, r1 A, r1 A, saddr saddr, A saddr, saddr A, sfr sfr, A MOV A, mem mem, A #byte 2 3 3 2 1 2 2 3 2 2 1-4 1-4 2 2 4 4 3 3 2 2 2 2 1 2 2-4 2 3 2 3 r1 byte (saddr) byte sfr byte r r1 A r1 A (saddr) (saddr) A (saddr) (saddr) A sfr sfr A A (mem) (mem) A A ((saddrp)) ((saddrp)) A A (addr16) (addr16) A PSWL byte PSWH byte PSWL A PSWH A A PSWL A PSWH A r1 r r1 A (mem) A (saddr) A sfr A ((saddrp)) (saddr) (saddr) x x x x x x x x x x Z AC P/V CY
8-bit data transfer
A, [saddrp] [saddrp], A A, !addr16 !addri16, A PSWL, #byte PSWH, #byte PSWL, A PSWH, A A, PSWL A, PSWH A, r1 r, r1 A, mem XCH A, saddr A, sfr A, [saddrp] saddr, saddr
Note When STBC or WDM is described as sfr, this instruction is treated as a dedicated instruction whose number of bytes is different from that of this instruction. Remark For symbols in flag, refer to the table below. Symbol (Blank) 0 1 x P V R No change Cleared to 0 Set to 1 Set/cleared according to result P/V flag functions as parity flag P/V flag operates as overflow flag Value previously saved is restored Remarks
52
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S rp1, #word saddrp, #word sfrp, #word rp, rp1 AX, saddrp saddrp, AX 3 4 4 2 2 2 3 2 2 4 4 2-4 2-4 2 3 3 2 2-4 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 rp1 word (saddrp) word sfrp word rp rp1 AX (saddrp) (saddrp) AX (saddrp) (saddrp) AX sfrp sfrp AX rp1 (addr16) (addr16) rp1 AX (mem) (mem) AX AX (saddrp) AX sfrp (saddrp) (saddrp) rp rp1 AX (mem) A, CY A + byte (saddr), CY (saddr) + byte sfr, CY sfr + byte r, CY r + r1 A, CY A + (saddr) A, CY A + sfr (saddr), CY (saddr) + (saddr) A, CY A + (mem) (mem), CY (mem) + A A, CY A + byte + CY (saddr), CY (saddr) + byte + CY sfr, CY sfr + byte + CY r, CY r + r1 + CY A, CY A + (saddr) + CY A, CY A + sfr + CY (saddr), CY (saddr) + (saddr) + CY A, CY A + (mem) + CY (mem), CY (mem) + A + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x Z AC P/V CY
16-bit data transfer
MOVW
saddrp, saddrp AX, sfrp sfrp, AX rp1, !addr16 !addr16, rp1 AX, mem mem, AX AX, saddrp AX, sfrp
XCHW
saddrp, saddrp rp, rp1 AX, mem A, #byte saddr, #byte sfr, #byte r, r1
ADD
A, saddr A, sfr
8-bit operation
saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte r, r1 ADDC A, saddr A, sfr saddr, saddr A, mem mem, A
53
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S A, #byte saddr, #byte sfr, #byte r, r1 SUB A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 A, CY A - byte (saddr), CY (saddr) - byte sfr, CY sfr - byte r, CY r - r1 A, CY A - (saddr) A, CY A - sfr (saddr), CY (saddr) - (saddr) A, CY A - (mem) (mem), CY (mem) - A A, CY A - byte - CY (saddr), CY (saddr) - byte - CY sfr, CY sfr - byte - CY r, CY r - r1 - CY A, CY A - (saddr) - CY A, CY A - sfr - CY (saddr), CY (saddr) - (saddr) - CY A, CY A - (mem) - CY (mem), CY (mem) - A - CY A A byte (saddr) (saddr) byte sfr sfr byte r r r1 A A (saddr) A A sfr (saddr) (saddr) (saddr) A A (mem) (mem) (mem) A x x x x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x x x x x AC P/V CY x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V P P P P P P P P P x x x x x x x x x x x x x x x x x x
8-bit operation
r, r1 SUBC A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte r, r1 AND A, saddr A, sfr saddr, saddr A, mem mem, A
54
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S A, #byte saddr, #byte sfr, #byte r, r1 OR A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 2 3 4 2 2 3 3 2-4 2-4 A A byte (saddr) (saddr) byte sfr sfr byte r, r r1 A A (saddr) A A sfr (saddr) (saddr) (saddr) A A (mem) (mem) (mem) A A A byte (saddr) (saddr) byte sfr sfr byte r r r1 A A (saddr) A A sfr (saddr) (saddr) (saddr) A A (mem) (mem) (mem) A A - byte (saddr) - byte sfr - byte r - r1 A - (saddr) A - sfr (saddr) - (saddr) A - (mem) (mem) - A x x x x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x AC P/V CY P P P P P P P P P P P P P P P P P P V V V V V V V V V x x x x x x x x x
8-bit operation
r, r1 XOR A, saddr A, sfr saddr, saddr A, mem mem, A A, #byte saddr, #byte sfr, #byte r, r1 CMP A, saddr A, sfr saddr, saddr A, mem mem, A
55
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S AX, #word saddrp, #word sfrp, #word ADDW rp, rp1 AX, saddrp AX, sfrp saddrp, saddrp AX, #word 3 4 5 2 2 3 3 3 4 5 2 2 3 3 3 4 5 2 2 3 3 2 2 2 2 2 AX, CY AX + word (saddrp), CY (saddrp) + word sfrp, CY sfrp + word rp, CY rp + rp1 AX, CY AX + (saddrp) AX, CY AX + sfrp (saddrp), CY (saddrp) + (saddrp) AX, CY AX - word (saddrp), CY (saddrp) - word sfrp, CY sfrp - word rp, CY rp - rp1 AX, CY AX - (saddrp) AX, CY AX - sfrp (saddrp), CY (saddrp) - (saddrp) AX - word (saddrp) - word sfrp - word rp - rp1 AX - (saddrp) AX - sfrp (saddrp) - (saddrp) AX AX x r1 AX (quotient), r1 (remainder) AX / r1 AX (higher 16 bits), rp1 (lower 16 bits) AX x rp1 AXDE (quotient), rp1 (remainder) AXDE / rp1 AX (higher 16 bits), rp1 (lower 16 bits) AX x rp1 AXDE (B) x (C) + AXDE B B + 2, C C + 2, n n - 1 End if n = 0 or P/V = 1 AXDE (B) x (C) + AXDE B B + 2, C C + 2, n n - 1 if overflow (P/V = 1) then AXDE 7FFFFFFFH if underflow (P/V = 1) then AXDE 80000000H end if n = 0 or P/V = 1 AX AX + | (DE) - (HL) | DE DE + 2 HL HL + 2 C C - 1 end if C = 0 or cy = 1 x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x AC P/V CY x x x x x x x x x x x x x x x x x x x x x V V V V V V V V V V V V V V V V V V V V V x x x x x x x x x x x x x x x x x x x x x
16-bit operation
saddrp, #word sfrp, #word SUBW rp, rp1 AX, saddrp AX, sfrp saddrp, saddrp AX, #word saddrp, #word sfrp, #word CMPW rp, rp1 AX, saddrp AX, sfrp saddrp, saddrp
Multiplication /division
MULU DIVUW MULUW DIVUX MULW
r1 r1 rp1 rp1 rp1
Sum-of- Signed products multiplioperation cation
MACW
n
3
x
x
x
V
x
Sum-of-products operation with saturation
MACSW
n
3
x
x
x
V
x
Relative operation
SACW
[DE + ], [HL + ]
4
x
x
x
V
x
56
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S MOVTBLW !addr16, n r1 saddr DEC r1 saddr INCW rp2 saddrp DECW ROR ROL RORC ROLC SHR SHL rp2 saddrp r1, n r1, n r1, n r1, n r1, n r1, n rp1, n 4 1 2 1 2 1 3 1 3 2 2 2 2 2 2 2 (addr16 + 2) (addr16), n n-1 addr16 addr16-2, End if n = 0 r1 r1 + 1 (saddr) (saddr) + 1 r1 r1 - 1 (saddr) (saddr) - 1 rp2 rp2 + 1 (saddrp) (saddrp) + 1 rp2 rp2 - 1 (saddrp) (saddrp) - 1 (CY, r17 r10, r1m - 1 r1m) x n times (CY, r10 r17, r1m + 1 r1m) x n times (CY r10, r17 CY, r1m-1 r1m) x n times (CY r17, r10 CY, r1m + 1 r1m) x n times (CY r10, r17 0, r1m - 1 r1m) x n times (CY r17, r10 0, r1m + 1 r1m) x n times (CY rp10, rp115 0, rp1m - 1 rp1m) x n times (CY rp115, rp10 0, rp1m+ 1 rp1m) x n times A3 - 0 (rp1)3 - 0, (rp1)7 - 4 A3 - 0, (rp1)3 - 0 (rp1)7 - 4 A3 - 0 (rp1)7 - 4, (rp1)3 - 0 A3 - 0, (rp1)7 - 4 (rp1)3 - 0 x x x x x x 0 0 0 P P P P P P P x x x x x x x x x x x x x x x x x x x V V V V Z AC P/V CY
Table shift
INC Increment/decrement Shift rotate
SHRW
SHLW
rp1, n
2
x
x
0
P
x
ROR4
[rp1]
2
ROL4
[rp1]
2
BCD adjustment
ADJBA 2 ADJBS Decimal Adjust Accumelator x x x P x
Data conversion
CVTBW
1
When A7 = 0, X A, A 00H When A7 = 1, X A, A FFH
Remarks 1. 2.
n of the shift rotate instruction indicates the number of times the shift rotate instruction is executed. The address of the table shift instruction ranges from FE00H to FEFFH.
57
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S CY, saddr.bit CY, sfr.bit CY, A.bit CY, X.bit CY, PSWH.bit CY, PSWL.bit MOV1 saddr.bit, CY sfr.bit, CY A.bit, CY X.bit, CY PSWH.bit, CY PSWL.bit, CY CY, saddr.bit CY, /saddr.bit CY, sfr.bit CY, /sfr.bit 3 3 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 2 3 3 2 2 2 2 CY (saddr.bit) CY sfr.bit CY A.bit CY X.bit CY PSWH.bit CY PSWL.bit (saddr.bit) CY sfr.bit CY A.bit CY X.bit CY PSWH.bit CY PSWL.bit CY CY CY (saddr.bit) CY CY (saddr.bit) CY CY sfr.bit CY CY sfr.bit CY CY A.bit CY CY A.bit CY CY X.bit CY CY X.bit CY CY PSWH.bit CY CY PSWH.bit CY CY PSWL.bit CY CY PSWL.bit CY CY (saddr.bit) CY CY (saddr.bit) CY CY sfr.bit CY CY sfr.bit CY CY A.bit CY CY A.bit CY CY X.bit CY CY X.bit CY CY PSWH.bit CY CY PSWH.bit CY CY PSWL.bit CY CY PSWL.bit x x x x x x x x x x x x x x x x x x x x x x x x x x x x Z AC P/V CY x x x x x x
Bit manipulation
CY, A.bit CY, /A.bit AND1 CY, X.bit CY, /X.bit CY, PSWH.bit CY, /PSWH.bit CY, PSWL.bit CY, /PSWL.bit CY, saddr.bit CY, /saddr.bit CY, sfr.bit CY, /sfr.bit CY, A.bit CY, /A.bit OR1 CY, X.bit CY, /X.bit CY, PSWH.bit CY, /PSWH.bit CY, PSWL.bit CY, /PSWL.bit
58
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S CY, saddr.bit CY, sfr.bit CY, A.bit XOR1 CY, X.bit CY, PSWH.bit CY, PSWL.bit saddr.bit sfr.bit A.bit SET1 X.bit PSWH.bit 2 2 2 2 3 2 2 2 2 3 3 2 2 2 2 1 1 1 2 2 2 2 3 2 3 3 2 CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY X.bit CY CY PSWH.bit CY CY PSWL.bit (saddr.bit) 1 sfr.bit 1 A.bit 1 X.bit 1 PSWH.bit 1 PSWL.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 X.bit 0 PSWH.bit 0 PSWL.bit 0 (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit CY 1 CY 0 CY CY x x x x x 1 0 x x x x x x x x x x x Z AC P/V CY x x x x x x
Bit manipulation
PSWL.bit saddr.bit sfr.bit A.bit CLR1 X.bit PSWH.bit PSWL.bit saddr.bit sfr.bit A.bit NOT1 X.bit PSWH.bit PSWL.bit SET1 CLR1 NOT1 CY CY CY
59
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S CALL !addr16 3 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (TPF, 00000000, addr5 + 1), PCL (TPF, 00000000, addr5 ), SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PCH rp1H, PCL rp1L, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PCH (rp1 + 1), PCL (rp1), SP SP - 2 (SP - 1) PSWH, (SP - 2) PSWL (SP - 3) (PC + 1)H, (SP - 4) (PC + 1)L, PCL (003EH), PCH (003FH), SP SP - 4, IE 0 PCL (SP), PCH (SP + 1), SP SP + 2 PCL (SP), PCH (SP +1) PSWL (SP + 2), PSWH (SP + 3) SP SP + 4 PCL (SP), PCH (SP + 1) PSWL (SP + 2), PSWH (SP + 3) SP SP + 4 (SP - 1) sfrH (SP - 2) sfrL SP SP - 2 {(SP - 1) postH, (SP - 2) postL, SP SP - 2} x n times (SP - 1) PSWH, (SP - 2) PSWL, SP SP - 2 {(UP - 1) postH, (UP - 2) postL, UP UP - 2} x n times sfrL (SP) sfrH (SP + 1) SP SP + 2 {postL (SP), postH (SP + 1), SP SP + 2} x n times PSWL (SP), PSWH (SP + 1), SP SP + 2 {postL (UP), postH (UP + 1), UP UP + 2} x n times SP word SP AX AX SP SP SP + 1 SP SP - 1 R R R R R R R R R R Z AC P/V CY
CALLF
!addr11
2
CALLT
[addr5]
1
rp1 Call/return CALL [rp1]
2
2
BRK
1
RET
1
RETB
1
RETI
1
R
R
R
R
R
sfrp PUSH post PSW PUSHU Stack manipulation post
3
2 1 2
sfrp
3
POP
post PSW
2 1 2 4 2 2 2 2
POPU
post SP, #word
MOVW
SP, AX AX, SP
INCW DECW
SP SP
Remark n of the stack manipulation instruction is the number of registers described as post.
60
PD78361A, 78362A
Unconditional Special Instructions branch
Flag Mnemonic Operand Byte Operation S CHKL CHKLA sfr sfr !addr16 rp1 BR [rp1] $addr16 BC $addr16 BL BNC $addr16 BNL BZ $addr16 BE BNZ $addr16 BNE BV $addr16 BPE BNV $addr16 BPO BN BP $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 BT X.bit, $addr16 PSWH.bit, $addr16 PSWL.bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 BF X.bit, $addr16 PSWH.bit, $addr16 PSWL.bit, $addr16 3 3 3 3 3 3 4 4 3 2 2 3 3 3 3 3 3 3 4 3 2 2 2 2 2 2 2 2 3 3 3 2 (pin level) (signal level before output buffer) A (pin level) (signal level before output buffer) PC addr16 PCH rp1H, PCL rp1L PCH (rp1 + 1), PCL (rp1) PC PC + 2 + jdisp8 PC PC + 2 + jdisp8 if CY = 1 x x Z x x AC P/V CY P P
PC PC + 2 + jdisp8 if CY = 0
PC PC + 2 + jdisp8 if Z = 1
PC PC + 2 + jdisp8 if Z = 0
PC PC + 2 + jdisp8 if P/V = 1
PC PC + 2 + jdisp8 if P/V = 0 PC PC + 2 + jdisp8 if S = 1 PC PC + 2 + jdisp8 if S = 0 PC PC + 3 + jdisp8 if (P/V S) Z = 0 PC PC + 3 + jdisp8 if P/V S= 0 PC PC + 3 + jdisp8 if P/V S = 1 PC PC + 3 + jdisp8 if (P/V S) Z = 1 PC PC + 3 + jdisp8 if Z CY = 0 PC PC + 3 + jdisp8 if Z CY = 1 PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if X.bit = 1 PC PC + 3 + jdisp8 if PSWH.bit = 1 PC PC + 3 + jdisp8 if PSWL.bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 3 + jdisp8 if X.bit = 0 PC PC + 3 + jdisp8 if PSWH.bit = 0 PC PC + 3 + jdisp8 if PSWL.bit = 0
Conditional branch
BGT BGE BLT BLE BH BNH
61
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S saddr.bit, $addr16 4 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 3 + jdisp8 if X.bit = 1 then reset X.bit PC PC + 3 + jdisp8 if PSWH.bit = 1 then reset PSWH.bit PC PC + 3 + jdisp8 if PSWL.bit = 1 then reset PSWL.bit PC PC + 4 + jdisp8 if (saddr.bit) = 0 then set (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 0 then set sfr.bit PC PC + 3 + jdisp8 if A.bit = 0 then set A.bit PC PC + 3 + jdisp8 if X.bit = 0 then set X.bit PC PC + 3 + jdisp8 if PSWH.bit = 0 then set PSWH.bit PC PC + 3 + jdisp8 if PSWL.bit = 0 then set PSWL.bit r2 r2 - 1, then PC PC + 2 + jdisp8 if 2 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 PCH R5, PCL R4, R7 PSWH, R6 PSWL, RBS2 - 0 n, RSS 0, IE 0 PCH R5, PCL R4, R5, R4 addr16 PSWH R7, PSWL R6 PCH R5, PCL R4, R5, R4 addr16 PSWH R7, PSWL R6 R R R R R x x x x x x x x x x Z AC P/V CY
sfr.bit, $addr16
4
A.bit, $addr16 BTCLR X.bit, $addr16
3
3
PSWH.bit, $addr16
3
PSWL.bit, $addr16 Conditional branch
3
saddr.bit, $addr16
4
sfr.bit, $addr16
4
A.bit, $addr16 BFSET X.bit, $addr16
3
3
PSWH.bit, $addr16
3
PSWL.bit, $addr16
3
r2, $addr16 DBNZ saddr, $addr16 Context switching
2
3
BRKCS
RBn
2
RETCS
!addr16
3
RETCSB
!addr16
4
R
R
R
R
R
62
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S [DE + ], A MOVM [DE - ], A 2 2 (DE + ) A, C C - 1 End if C = 0 (DE - ) A, C C - 1 End if C = 0 (DE + ) (HL + ), C C - 1 End if C = 0 (DE - ) (HL - ), C C - 1 End if C = 0 (DE + ) A, C C - 1 End if C = 0 (DE - ) A, C C - 1 End if C = 0 (DE + ) (HL + ), C C - 1 End if C = 0 (DE - ) (HL - ), C C - 1 End if C = 0 (DE + ) - A, C C - 1 End if C = 0 or Z = 0 (DE - ) - A, C C - 1 End if C = 0 or Z = 0 (DE + ) - (HL + ), C C - 1 End if C = 0 or Z = 0 (DE - ) - (HL - ), C C - 1 End if C = 0 or Z = 0 (DE + ) - A, C C - 1 End if C = 0 or Z = 1 (DE - ) - A, C C - 1 End if C = 0 or Z = 1 (DE + ) - (HL + ), C C - 1 End if C = 0 or Z = 1 (DE - ) - (HL - ), C C - 1 End if C = 0 or Z = 1 (DE + ) - A, C C - 1 End if C = 0 or CY = 0 (DE - ) - A, C C - 1 End if C = 0 or CY = 0 (DE + ) - (HL + ), C C - 1 End if C = 0 or CY = 0 (DE - ) - (HL - ), C C - 1 End if C = 0 or CY = 0 x x x V x Z AC P/V CY
[DE + ], [HL + ] MOVBK [DE - ], [HL - ]
2
2
[DE + ], A XCHM [DE - ], A
2
2
[DE + ], [HL + ] XCHBK [DE - ], [HL - ]
2
2
[DE + ], A CMPME String [DE - ], A
2
2
x
x
x
V
x
[DE + ], [HL + ] CMPBKE [DE - ], [HL - ]
2
x
x
x
V
x
2
x
x
x
V
x
[DE + ], A CMPMNE [DE - ], A
2
x
x
x
V
x
2
x
x
x
V
x
[DE + ], [HL + ] CMPBKNE [DE - ], [HL - ]
2
x
x
x
V
x
2
x
x
x
V
x
[DE + ], A CMPMC [DE - ], A
2
x
x
x
V
x
2
x
x
x
V
x
[DE + ], [HL + ] CMPBKC [DE - ], [HL - ]
2
x
x
x
V
x
2
x
x
x
V
x
63
PD78361A, 78362A
Instructions
Flag Mnemonic Operand Byte Operation S [DE + ], A CMPMNC 2 (DE + ) - A, C C - 1 End if C = 0 or CY = 1 (DE - ) - A, C C - 1 End if C = 0 or CY = 1 (DE + ) - (HL + ), C C - 1 End if C = 0 or CY = 1 (DE - ) - (HL - ), C C - 1 End if C = 0 or CY = 1 STBC byteNote WDM byteNote RSS RSS RBS2 - 0 n, RSS 0 RBS2 - 0 n, RSS 1 No Operation IE 1 (Enable Interruptt) IE 0 (Disable Interrupt) x Z x AC P/V CY x V x
String
[DE - ], A
2
x
x
x
V
x
[DE + ], [HL + ] CMPBKNC [DE - ], [HL - ] STBC, #byte WDM, #byte CPU control SWRS RBn SEL RBn, ALT NOP EI DI
2
x
x
x
V
x
2 4 4 1 2 2 1 1 1
x
x
x
V
x
MOV
Note If the op code of the STBC register and WDM register manipulation instructions is wrong, an op code trap interrupt occurs. Operation on trap: (SP - 1) PSWH, (SP - 2) PSWL, (SP - 3) (PC - 4)H, (SP - 4) (PC - 4)L, PCL (003CH), PCH (003DH), SP SP - 4, IE 0
64
PD78361A, 78362A
8. EXAMPLE OF SYSTEM CONFIGURATION
Controlling outdoor apparatus of inverter air conditioner
PD78362A
Real-time pulse unit CM03 Dead time setting register U/D 16-bit timer U U
CM00
TO00 TO01 Inverter
CM01
Pulse generation circuit
V V
TO02 TO03
CM02 (Analog signal)
AC power supply monitor External temperature Thermal exchange temperature Outlet temperature Inlet temperature
W W
TO04 TO05
ANI0 ANI1 ANI2 ANI3 ANI4
ROM 24K bytes 10-bit A/D converter RAM 768 bytes Generalpurpose port
P40 P41 P42 P43
4-way valve 2-way valve Outdoor fan motor
DC monitor Compressor motor temperature monitor
NMI INTP1
Programmable interrupt controller
Real-time output port
P00 P01 P02 P03
Stepping motor (electronic expansion valve)
RXD
Indoor apparatus controller
TXD
Serial interface
65
PD78361A, 78362A
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Power supply voltage Symbol VDD AVDD AVSS Input voltage VI Pins other than P70/ANI0-P77/ANI7 Test conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 Unit V V V V
Output voltage Low-level output current
VO IOL Note Output pins other than those in the note Total of all output pins
-0.5 to VDD + 0.5 20 4.0
V mA mA
200 -3.0 -25 AVSS - 0.5 to AVDD + 0.5 AVSS - 0.5 to AVDD + 0.5 -40 to +85 -60 to +150
mA mA mA V V C C
High-level output current
IOH
All output pins Total of all output pins
Analog input voltage A/D converter reference input voltage Operating ambient temperature Storage temperature
VIAN AVREF TA Tstg
P70/ANI0-P77/ANI7 pins
Note P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40, P07/TCLRUD, and P80/TO00P85/TO05 pins. Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momentarily. In other words, an absolute maxumum rating is a value at which the possibility of psysical damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the these ratings are not exceeded during use of the product.
Recommended Operating Conditions
Oscillation frequency 3 MHz fXX 8 MHz TA -40 to +85 C VDD +5.0 V 10 %
Capacitance (TA = 25 C, VSS = VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz 0 V except measured pins Test conditions MIN. TYP. MAX. 20 20 20 Unit pF pF pF
66
PD78361A, 78362A
Oscillator Characteristics (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Resonator Ceramic resonator or crystal resonator Recommended circuit Parameter Oscillation frequency (fXX) VSS X1 X2 MIN. 3 MAX. 8 Unit MHz
C1
C2
External clock X1 X2 Leave unconnected HCMOS inverter
X1 input frequency (fX)
3
8
MHz
X1 rise/fall time (tXR, tXF)
0
30
ns
X1 input high-/low-level width (tWXH, tWXL)
40
170
ns
Caution When using system clock oscillation circuits, to reduce the effect of the wiring capacitouce, etc, wire the area indicated by dotted-line as follows: * Make the wiring as short as possible. * Do not allow the wiring to intersect other signal lines. Keep it away from other lines in which varying high currents flow. * Make sure that the ground point of the oscillation circuit capacitor is always at the same electric potential as VSS. Do not allow the wiring to be grounded to a ground pattern in which very high currents are flowing. * Do not extract signals from the oscillation circuit.
67
PD78361A, 78362A
DC Characteristics (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter Low-level input voltage Symbol VIL1 VIL2 High-level input voltage VIH1 VIH2 Low-level output voltage VOL1 VOL2 VOL3 High-level output voltage Input leakage current Output leakage current VDD supply current VOH ILI ILO IDD1 IDD2 Data retention voltage Data retention current VDDDR IDDDR Note 1 Note 2 Note 1 Note 2 Note 3 Note 4 Note 5 IOH = -400 A 0 V VI VDD, AVDD = VDD 0 V VO VDD, AVDD = VDD Operating mode HALT mode STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5.0 V 10 % Pull-up resistance RL VI = 0 V 15 2.5 2 10 60 10 50 150 70 45 IOL = 2.0 mA IOL = 15 mA IOL = 10 mA VDD - 1.0 10 10 120 70 Test conditions MIN. 0 0 2.2 0.8VDD 0.45 1.5 1.5 TYP. MAX. 0.8 0.2VDD Unit V V V V V V V V
A A
mA mA V
A A
K
Notes 1. Pins other than those specified in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3/TI, P25/INTP4, P32/ SO/SB0, P33/SI/SB1 and P34/SCK pins. 3. Pins other than those specified in Notes 4 and 5. 4. P80/TO00-P85/TO05 pins (When IOL = 15 mA is in operation, up to three pins can be ON simultaneously.) 5. P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40 and P07/TCLRUD pins (When IOL = 10 mA is in operation, up to four pins can be ON simultaneously.) . Caution When the P80-P85, and P00-P07 pins are not used under the conditions specified in Notes 4 and 5, they have the same characteristics as in Note 3.
68
PD78361A, 78362A
AC Characteristics (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V, CL = 100 pF, fXX = 8 MHz)
System Clock Cycle
Parameter System clock cycle time Symbol tCYK Test conditions MIN. 62.5 MAX. 166.7 Unit ns
Serial Operation (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK SCK output SCK input Serial clock low-level width Serial clock high-level width SI setup time (vs. SCK ) SI hold time (vs. SCK ) SCK SO delay time tSRXSK tHSKRX tDSKTX R = 1 k, C = 100 pF tWSKH tWSKL SCK output SCK input SCK output SCK input Test conditions Internal 8 dividing External clock Internal 8 dividing External clock Internal 8 dividing External clock MIN. 500 500 210 210 210 210 80 80 210 MAX. Unit ns ns ns ns ns ns ns ns ns
Up/Down Counter Operation (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter TIUD high-/low-level width TCUD high-/low-level width TCLRUD high-/low-level width tWCLUH, tWCLUL TCUD setup time (vs. TIUD ) TCUD hold time (vs. TIUD ) TIUD setup time (vs. TCUD) TIUD hold time (vs. TCUD) TIUD & TCUD cycle time tSTCU tHTCU tS4TIU tH4TIU tCYC tCYC4 Mode 3 Mode 3 Mode 4 Mode 4 Other than mode 4 Mode 4 tWTCUH, tWTCUL Symbol tWTIUH, tWTIUL Test conditions Other than mode 4 Mode 4 Other than mode 4 Mode 4 MIN. 2T 4T 2T 4T 2T T T 2T 2T 4 2 MAX. Unit ns ns ns ns ns ns ns ns ns MHz MHz
Remark T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)
69
PD78361A, 78362A
Other Operations (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V)
Parameter Symbol Test conditions MIN. 2 1.5 Ts = T Ts = 4T Ts = 8T Ts = 16T INTP1 high-/low-level width tWI1H, tWI1L Ts = T Ts = 4T Ts = 8T Ts = 16T INTP2 high-/low-level width INTP3(TI) high-/lowlevel width tWI3H, tWI3L tWI2H, tWI2L Ts = T Ts = 4T Ts = T Ts = 4T Ts = 8T Ts = 16T Ts = 64T Ts = 128T Ts = 256T INTP4 high-/low-level width tWI4H, tWI4L Ts = T Ts = 4T Ts = 8T Ts = 16T 250 1.0 2.0 4.0 250 1.0 2.0 4.0 250 1.0 250 1.0 2.0 4.0 16.0 32.0 64.0 250 1.0 2.0 4.0 MAX. Unit
NMI high-/low-level width tWNIH, tWNIL RESET high-/low-level width tWRSH, tWRSL INTP0 high-/low-level width tWI0H, tWI0L
s s
ns
s s s
ns
s s s
ns
s
ns
s s s s s s
ns
s s s
Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.) 2. Ts refers to the input sampling frequency. INTP0-INTP4 can be selected to programmable.
70
PD78361A, 78362A
A/D Converter Characteristics (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD)
Parameter Resolution Total error Note 1 4.5 V AVREF AVDD 3.4 V AVREF AVDD Quantization error Conversion time tCONV 62.5 ns tCYK < 80 ns 80 ns tCYK 166.6 ns Sampling time tSAMP 62.5 ns tCYK < 80 ns 80 ns tCYK 166.6 ns Zero-scale error Note 1 4.5 V AVREF AVDD 3.4 V AVREF AVDD Full-scale error Note 1 4.5 V AVREF AVDD 3.4 V AVREF AVDD Nonlinearity error Note 1 4.5 V AVREF AVDD 3.4 V AVREF AVDD Analog input voltage Note 2 VIAN RAN When not sampling When sampling Reference voltage AVREF current AVDD supply current A/D converter data retention current AVREF AIREF AIDD AIDDDR Operating mode STOP mode AVDDDR = 2.5 V AVDDDR = 5 V 10 % 3.4 1.0 2.0 2 10 -0.3 10 Note 3 AVDD 3.0 6.0 10 50 V mA mA 208 169 24 20 1.5 1.5 1.5 1.5 1.5 1.5 2.5 4.5 2.5 4.5 2.5 4.5 AVREF + 0.3 Symbol Test conditions MIN. 10 0.4 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK tCYK tCYK LSB LSB LSB LSB LSB LSB V M
Analog input impedance
A A
Notes 1. The quantization error is excluded. 2. When -0.3 V VIAN 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed with the 10-bit resolution. When AVREF VIAN +0.3 V, the conversion result becomes 3FFH. 3. The analog input impedance at the time of sampling is the same as the equivalent circuit shown below. (The values in the diagram are TYP. values; they are not guaranteed values)
1 k Analog input pin 25 pF (Input capacitance included) 4 pF
71
PD78361A, 78362A
Cautions 1. When using the P70/ANI0-P77/ANI7 pins for both digital and analog inputs, the previously described characteristics are not guaranteed. Therefore, ensure that all of the eight P70/ANI0-P77/ANI7 pins are used either for analog input or digital input. 2. When using the P70/ANI0-P77/ANI7 pins as digital input, make sure to set that AVDD = VDD, and AVSS = VSS. AC Timing Test Point
VDD 0.8 VDD or 2.2 V Test point 0.2 VDD or 0.8 V 0V 0.2 VDD or 0.8 V 0.8 VDD or 2.2 V
72
PD78361A, 78362A
Serial Operation
tCYSK tWSKL SCK tDSKTX SO tWSKH
SI tSRXSK tHSKRX
Up/Down Counter (Timer 4) Input Timing
tWTIUH
TIUD
tSTCU tHTCU tWTCUL TCUD tWTCUH
tWTIUL
tWCLUH
TCLRUD
tWCLUL
TIUD tS4TIU tH4TIU tS4TIU tH4TIU
TCUD
73
PD78361A, 78362A
Interrupt Input Timing
tWNIH tWNIL
0.8 VDD NMI 0.2 VDD
tWInH
tWInL
0.8 VDD INTPn 0.2 VDD
Remark n = 0 - 4 Reset Input Timing
tWRSH
tWRSL
0.8 VDD RESET 0.2 VDD
74
PD78361A, 78362A
10. PACKAGE DRAWING
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
75
PD78361A, 78362A
11. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative.
Table 11-1. Insertion Type Soldering Conditions
PD78361ACW-xxx: 64-pin plastic shrink DIP (750 mil) PD78362ACW-xxx: 64-pin plastic shrink-DIP (750 mil)
Soldering method Wave soldering (pin only) Partial heating
Soldering conditions Solder bath temperature: 260 C or less, Time: 10 sec. max.,
Pin temperature: 300 C or less, Time: 3 sec. max. (per pin)
Caution Wave soldering is only for the pins in order that jet solder cannot contact with the chip directly.
76
PD78361A, 78362A
APPENDIX A. DIFFERENCES BETWEEN PD78362A AND PD78328
Product name Item Minimum instruction execution time Internal memory General-purpose registers Number of basic instructions Instruction set ROM RAM 125 ns 24K bytes 768 bytes 8 bits x 16 x 8 banks 115 * * * * 111
PD78362A
internal clock : 16 MHz external clock : 8 MHz 250 ns 16K bytes 512 bytes
PD78328
internal clock : 8 MHz, external clock : 16 MHz
16-bit transfer/operation Multiplication/division (16 bits x 16 bits, 32 bits / 16 bits) Bit manipulation String --
* Sum-of-products operation (16 bits x 16 bits + 32 bits) * Relative operation I/O lines Input I/O Real-time pulse unit 14 (of which 8 are multiplexed with analog input) 38 * * * * * 16-bit timer x 5 16-bit compare register x 7 16-bit capture register x 3 16-bit capture/compare register x 2 Two output modes selectable Mode 0, set-reset output : 6 channels Mode 1, buffer output : 6 channels
11 (of which 8 are multiplexed with analog input) 41 * * * * 16-bit timer x 3 16-bit compare register x 14 16-bit capture/compare register x 1 Two output modes selectable Mode 0, set-reset output : 6 channels toggle output : 1 channel Mode 1, buffer output : 8 channels
* 16-bit resolution PWM output: 1 channel Real-time output port PWM unit A/D converter Serial interface 4 (buffer output in 4-bit units) 8-/9-/10-/12-bit resolution variable PWM output: 2 channels 10-bit resolution, 8 channels Dedicated baud rate generator UART : 1 channel Clocked serial interface/SBI : 1 channel * External: 6, internal: 14 (2 multiplexed with external) * 4 programmable priority levels * External: 4, internal: 17 * 3 programmable priority levels 4/8 (buffer output in 4-/8-bit units) 8-bit resolution PWM output: 1 channel
Interrupt function
* Three service selectable (vectored interrupt/macro service/context switching) Test source External expansion function PLL control circuit Package Others Provided (external 8 MHz internal: 16 MHz) * 64-pin plastic shrink DIP (750 mil) * Watchdog timer * Standby functions (HALT mode, STOP mode) None * 64-pin plastic shrink DIP * 64-pin plastic QFP (14 x 20 mm) None None Internal: 1 Provided
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PD78361A, 78362A
APPENDIX B. TOOLS
B.1 DEVELOPMENT TOOLS The following development tools are available to support development of PD78362A program: LANGUAGE PROCESSOR
78K/III series relocatable assembler (RA78K3) A relocatable assembler, that can be used commonly for the 78K/III series products. Since this assembler is provided with macro functions, it enhances the developmnt efficency. A structured assembler, that can explicitly describe the program control structure, is also supplied, so that the program productivity and maintainability can be improved.
Host machine
OS
Supply media 3.5" 2HD
Order code (product name)
S5A13RA78K3 S5A10RA78K3 S7B13RA78K3 S7B10RA78K3 S3P16RA78K3 S3K15RA78K3 S3R15RA78K3
PC-9800 series
MS-DOSTM 5" 2HD
IBM PC/ATTM and its compatible model HP9000 series 700TM SPARCstationTM NEWSTM 78K/III series C compiler (CC78K3)
PC DOSTM
3.5" 2HC 5" 2HC
HP-UXTM SunOSTM NEWS-OSTM
DAT Cartridge tape (QIC-24)
This is a C compiler that can be commonly used for 78K/III series. This program converts the program written in C language to object codes microcontroller can execute. When using this compiler, the 78K3 series relocatable assembler (RA78K/III) is necessary. Host machine Order code (product name)
OS
Supply media 3.5" 2HD
S5A13CC78K3 S5A10CC78K3 S7B13CC78K3 S7B10CC78K3 S3P16CC78K3 S3K15CC78K3 S3R15CC78K3
PC-9800 series
MS-DOS 5" 2HD
IBM PC/AT and its compatible model HP9000 series 700 SPARC station NEWS
PC DOS
3.5" 2HC 5" 2HC
HP-UX SunOS NEWS-OS
DAT Cartridge tape (QIC-24)
Remark The operations of the relocatable assembler and C compiler are guaranteed only on the specified host machine and OS described above.
78
PD78361A, 78362A
PROM WRITING TOOLS
PG-1500 This is a PROM programmer that can program PROM-contained single-chip microcontrollers in standalone mode or under control of a host machine when the accessory board and an optional programmer adapter are connected. It can also program representative PROMs from 256K-bit to 4M-bit models. PROM programmer adapters that writes a program to the PD78P364A on a general-purpose PROM programmer such as the PG-1500. PA-78P364CW : for PD78P364ACW Connects the PG-1500 and a host machine with a serial intrface and a parallel interface to control the PG-1500 from the host machine.
Hardware
PA-78P364CW
PG-1500 controller
Host machine Software
OS
Supply media 3.5" 2HD
Order code (part number)
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
PC-9800 series
MS-DOS 5" 2HD
IBM PC/AT and compatible machines
PC DOS
3.5" 2HD 5" 2HC
Remark The operation of the PG-1500 controller is guaranteed only on the above host machine and OS. DEBUGGING TOOLS (WHEN IE CONTROLLER IS USED)
IE-78350-R Hardware In-circuit emulator that can be used to develop and debug application systems. Connected to a host machine for debugging. I/O emulation board that emulates the peripheral functions of the target device such as I/O ports. Emulation prove that connects the IE-78350-R to the target system. Program that controls the IE-78350-R on the host machine. It can automatically execute commands, enhancing debugging efficiency. Host machine Software Order code (part number)
IE-78365-R-EM1 EP-78327CW-R IE-78350-R control program (IE controller)
OS
Supply media 3.5" 2HD
S5A13IE78365A S5A10IE78365A S7B13IE78365A S7B10IE78365A
PC-9800 series
MS-DOS 5" 2HD
IBM PC/AT and compatible machines
PC DOS
3.5" 2HC 5" 2HC
Remark The operation of the IE controller is guaranteed only on the above host machine and OS.
79
PD78361A, 78362A
DEVELOPMENT TOOL CONFIGURATION (WHEN USING IE CONTROLLER)
Host machine PC-9800 series IBM PC series EWS
RS-232-C
IE-78350-R in-circuit emulator IE-78365-R-EM1 I/O emulation board (optional)
+
Emulation prove
Software
RS-232-C PROM programmer
EP-78327CW-R
Relocatable assembler
C compiler
PG-1500 controller
+
Conversion socket for connecting the emulation prove and the target system Note PG-1500
IE controller Socket for SDIP Built-in PROM models
PD78P364ACW
+
Programmer adapter Target system
PA-78P364CW
Note Use the socket available on the market. Remarks 1. 2. Host machine and PG-1500 can be directly connected by RS-232-C. 3.5-inch FD represents the supply media of software in this figure.
80
PD78361A, 78362A
DEBUGGING TOOLS (WHEN INTEGRATED DEBUGGER IS USED)
IE-784000-R IE-78350-R-EM-A IE-78365-R-EM1 EP-78327CW-R IE-70000-98-IF-B IE-70000-98N-IF In-circuit emulation that can be used to develop and debug the application system. Connected to a host machine for debugging. Emulation board that emulates the peripheral functions of the target device such as I/O ports. I/O emulation board that emulates the peripheral functions of the target device such as I/O ports. Emulation probe connecting the IE-784000-R to the target system. Interface adapter to connect PC-9800 series (except notebook type personal computer) as the host machine.
Hardware
Interface adapter and cable to connect PC-9800 series notebook type personal computer as the host machine. IE-70000-PC-IF-B Interface adapter to connect IBM PC as the host machine. IE-78000-R-SV3 Interface adapter and cable to connect EWS as the host machine. Integrated debugger Program controlling the in-circuit emulator for the 78K/III series. Used in combination with a (ID78K3) device file (DF78365). Can debug a program coded in the C language, structured assembly language, or assembly language at source program level. Can also split the screen of the host machine into windows on each of which information is displayed, enhancing debugging efficiency. Host machine OS PC-9800 series MS-DOS + WindowsTM Supply media 3.5" 2HD 5" 2HD Order code (part number)
Device File (DF78365)
SAA13ID78K3 SAA10ID78K3 IBM PC/AT and compatible PC DOS 3.5" 2HC SAB13ID78K3 + Windows 5" 2HC SAB10ID78K3 machines (Japanese Windows) IBM PC/AT and compatible 3.5" 2HC SBB13ID78K3 machines (English Windows) 5" 2HC SBB10ID78K3 File containing information peculiar to device. Use in combination with an assembler (RA78K3), C compiler (CC78K3), and integrated debugger (ID78K3). Host machine Order code (part number) OS Supply media PC-9800 series MS-DOS 3.5" 2HD S5A13DF78365 5" 2HD S5A10DF78365 IBM PC/AT and compatible PC DOS 3.5" 2HC S7B13DF78365 machines 5" 2HC S7B10DF78365
Remark The operation of the integrated debugger and device file is guaranteed only on the above host machine and OS.
Software
81
PD78361A, 78362A
DEVELOPMENT TOOL CONFIGURATION (WHEN USING INTEGRATED DEBUGGER)
Host machine PC-9800 series IBM PC/AT EWS IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B
IE-784000-R in-circuit emulator IE-78350-R-EM-A emulation board (optional) IE-78365-R-EM1 I/O emulation board (optional) EP-78327CW-R
+ +
Emulation prove
Software
RS-232-C Relocatable assembler C compiler PG-1500 controller
+
Conversion socket for connecting the emulation prove and the target system Note PROM programmer PG-1500 Socket for SDIP
Integrated Device file debugger Built-in PROM models
PD78P364ACW
+
Programmer adapter Target system
PA-78P364CW
Note Use the socket available on the market. Remarks 1. 2. Desk top-type PC represents host machine in this figure. 3.5-inch FD represents the supply media of software in this figure.
82
PD78361A, 78362A
B.2 EMBEDDED SOFTWARE The following embedded software is available for enhancing the efficiency of program development and maintenance. REAL-TIME OS
Real-time OS (RX78K/III) Note RX78K/III is intended to implement a multi-tasking environment for use in the control field where real-time capability is a must. It can allocate the idle time of the CPU to other processing to improve the overall performance of the system. RX78K/III provides system calls conforming to the ITRON specification. The RX78K/III package supplies a tool (configurator) to create the nucleus of RX78K/III and multiple information tables. Host machine OS PC-9800 series IBM PC/AT and compatible machines MS-DOS PC DOS Supply media 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC Pending Pending Pending Pending Order code (part number)
Note Under development Caution Before purchasing this product, you are requested to conclude a contract licensing use by filling out a specified form. Remark When using the RX78K/III real-time OS, the RA78K3 assembler package (optional) is necessary.
83
PD78361A, 78362A
FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM
Fuzzy knowledge data Program that supports input/editing and evaluation (simulation) of fuzzy knowledge (fuzzy rules and membership functions). creation tool Host machine Order code (part number) (FE9000, FE9200) OS PC-9800 series MS-DOS Supply media 3.5" 2HD 5" 2HD 3.5" 2HC
S5A13FE9000 S5A10FE9000 IBM PC/AT and compatible PC DOS S7B13FE9200 + machines Windows 5" 2HC S7B10FE9200 Translator (FT78K3) Note Program that converts the fuzzy knowledge data obtained by using the fuzzy knowledge data creation tool into assembler source program for the RA78K3. Host machine Order code (part number) OS Supply media PC-9800 series MS-DOS 3.5" 2HD S5A13FT78K3 5" 2HD S5A10FT78K3 IBM PC/AT and compatible PC DOS 3.5" 2HC S7B13FT78K3 machines 5" 2HC S7B10FT78K3 Fuzzy inference module Program that executes fuzzy inference when linked with the fuzzy knowledge data converted by the translator. (FI78K3) Note Host machine Order code (part number) OS Supply media S5A13FI78K3 PC-9800 series MS-DOS 3.5" 2HD 5" 2HD S5A10FI78K3 IBM PC/AT and compatible PC DOS 3.5" 2HC S7B13FI78K3 machines 5" 2HC S7B10FI78K3 Fuzzy inference debugger Support software that evaluates and adjusts the fuzzy knowledge data at the hardware level by using an in-circuit emulator. (FD78K3) Host machine Order code (part number) OS Supply media PC-9800 series MS-DOS 3.5" 2HD S5A13FD78K3 S5A10FD78K3 5" 2HD IBM PC/AT and compatible PC DOS 3.5" 2HC S7B13FD78K3 S7B10FD78K3 machines 5" 2HC
Note Under development
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[MEMO]
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
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PD78361A, 78362A
MS-DOS and windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademark of Sony Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
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