View UPD16700_90543.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD16700
256-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The PD16700 is a TFT-LCD gate driver equipped with 256-output lines. It can output a high-gate scanning voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit. It can also drive the XGA/SXGA panel.
FEATURES
* CMOS level input (3.3 V) * 256 outputs * High-output voltage (VDD2-VEE2 = amplitude: 40 V MAX.) * Capable of All-on outputting (AO)
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16700N-xxx
Remark The TCP's external shape is customized. To order the required shape, please contact an one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14085EJ1V1DS00 (1st edition) Date Published July 2000 NS CP (K) Printed in Japan
The mark * shows major revised points.
(c)
1999
PD16700
1. BLOCK DIAGRAM
R,/L LS1
Note
CLK
LS1Note
STVR
LS1Note SR1 SR2 SR3
256-bit shift register SR254 SR255 SR256
LS1Note
STVL
OE1
LS1Note
OE2
LS1Note
OE3
LS1Note
AO
LS1Note
LS2Note VEE2
LS2Note LS2Note
LS2
Note
LS2Note LS2Note
O1
O2
O3
O254
O255
O256
Note LS1: shifts CMOS level and internal level, LS2: shifts interval level and output level (VDD2-VEE2). Remark /xxx indicates active low signal.
2
Data Sheet S14085EJ1V1DS00
PD16700
2. PIN CONFIGURATION ( PD16700N-xxx)
VEE2 VEE1 VSS STVR R,/L CLK OE1 OE2 OE3 STVL AO VDD1 VDD2
O1 O2 O3
Copper foil Surface
O254 O255 O256
Remark This figure does not specify the TCP package.
Data Sheet S14085EJ1V1DS00
3
PD16700
3. PIN FUNCTIONS
Pin Symbol O1 to O256 Pin Name Driver output Description These pins output scan signals that drive the vertical direction (gate lines) of a TFT-LCD. The output signals change in synchronization with the rising edge of shift clock CLK. The driver output amplitude is VDD2 - VEE2.
R,/L STVR, STVL
Shift direction select R,/L = H (right shift) : STVR O1 O256 STVL input R,/L = L (left shift) : STVL O256 O1 STVR Start pulse input/output This is the input of the internal shift register. The start pulse is read at the rising edge of shift clock CLK, and scan signals are output from the driver output pins. The input level is a CMOS (3.3 V) level. The start pulse is output at the falling edge of the 256th clock of shigt clock CLK, and is cleared at the falling edge of the 257th clock. The output level is VDD1 VSS (logic level). This pin inputs a shift clock to the internal shift register. The shift operation is performed in synchronization with the rising edge of this input. When this pin goes H, the driver output is fixed to VEE2 level. The shift register is not cleared. OE1: O1, O4, ... O250, O253, O256 OE1: O2, O5, ... O251, O254 OE1: O3, O6, ... O252, O255 When this pin goes L, the driver output is fixed to VDD2 level. The shift register is not cleared. This pin has priority over OE1 to OE3. 3.3 V 0.3 V
CLK OE1,OE2,OE3
Shift clock input Output enable input
*
AO VDD1 VDD2 VSS VEE1
All-on control Logic power supply
Driver positive power 15 to 25 V supply The driver output : H level Logic ground Negative Power supply for internal operation Driver negative power supply Connect this pin to the ground of the system. -15 to -5 V
VEE2
The driver output : L level (VEE2-VEE1 < 6.0 V)
Cautions 1. To prevent latch up, turn on power to VDD1, VEE1/2, VDD2, and logic input in this order. Turn off power in the reverse order. These power up/down sequence must be observed also during transition period. 2. Insert a capacitor of about 0.1 F between each power line, as shown below, to secure noise margin such as VIH and VIL.
VDD2 VDD1 0.1 F VSS 0.1 F VEE1/2 0.1 F
4
Data Sheet S14085EJ1V1DS00
PD16700
* 4. TIMING CHART (R,/L = H, AO = H)
1 CLK 2 3 255 256 257 258
259
OE1
OE2
OE3
STVR (STVL)
O1 (O256)
O2 (O255)
O3 (O254)
O255 (O2)
O256 (O1)
STVL (STVR)
O1 of next stage (O256 of next stage)
O2 of next stage (O255 of next stage)
Data Sheet S14085EJ1V1DS00
5
PD16700
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Logic Supply Voltage Driver Positive Supply Voltage Power Supply Voltage Internal Operation Negative Supply Voltage Driver Negative Supply Voltage Input Voltage Operating Ambient Temperature Storage Temperature Symbol VDD1 VDD2 VDD2-VEE1, VEE2 VEE1 VEE2 VI TA Tstg Rating -0.5 to +7.0 -0.5 to +28 -0.5 to +42 -16 to + 0.5 VEE1 - 0.3 to VEE1 + 7.0 -0.5 to VDD1 + 0.5 -20 to +75 -55 to +125 Unit V V V V V V C C
*
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = -20 to +75C, VSS = 0 V)
Parameter Logic Supply Voltage Driver Positive Supply Voltage Internal Operation Negative Supply Voltage Power Supply Voltage Symbol VDD1 VDD2 VEE1 VDD2-VEE1 VEE2-VEE1 Clock Frequency fCLK MIN. 3.0 15 -15 20 0 TYP. 3.3 23 -10 33 MAX. 3.6 25 -5.0 40 6.0 100 Unit V V V V V kHz
Electrical Characteristics (TA = -20 to +75C, VDD1 = 3.3 V 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage LCD Driver Output ON Resistance Input Leak Current Static Current Dissipation Symbol VIH VIL VOH VOL RON IIL IDD1 Condition CLK, STVR (STVL), R,/L, OE1-OE3 STVR (STVL), IOH = -40 A STVR (STVL), IOL = +40 A VOUT = VEE2 + 1.0 V, or VDD2 - 1.0 V VI = 0 V or 3.6 V VDD1, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load IDD2 VDD2, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load IEE VEE1, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load -1100 -550 50 100 500 1.0 1000 MIN. 0.8 VDD1 VSS VDD1 - 0.4 VSS TYP. MAX. VDD1 0.2 VDD1 VDD1 VSS + 0.4 1.0 Unit V V V V k
A A
A
A
6
Data Sheet S14085EJ1V1DS00
PD16700
Switching Characteristics (TA = -20 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter Cascade Output Delay Time Symbol tPHL1 tPLH1 Driver Output Delay Time tPHL2 tPLH2 tPHL3 tPLH3 Output Rise Time Output Fall Time Input Capacitance tTLH tTHL CI TA = 25 C CL = 300 pF CL = 300 pF, OEn On Condition CL = 20 pF, CLK STVL (STVR) CL = 300 pF, CLK On MIN. TYP. MAX. 800 800 800 800 800 800 350 350 15 Unit ns ns ns ns ns ns ns ns pF
Timing Requirements (TA = -20 to +75C, VDD1 = 3.3 V 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter Clock Pulse High Width Clock Pulse Low Width Enable Pulse Width Data Setup Time Data Hold Time Symbol PWCLK(H) PWCLK(L) PWOE tSETUP tHOLD STVR (STVL) CLK CLK STVR(STVL) Condition MIN. 500 500 1.0 200 200 TYP. MAX. Unit ns ns
s
ns ns
Caution
Keep the time and fall time of the logic input to tr = tf = 20 ns (10 to 90 % of the rated values).
Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1. For details, refer to 6. SWITCHING CHARACTERISTIC WAVEFORM.
Data Sheet S14085EJ1V1DS00
7
8 Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1.
PWCLK(H) CLK 50 % 1 2 3 PWCLK(L) 4 5 6 7 253 254 255 50 % 90% 256 10% tr tf tSETUP tHOLD 50 % STVR tPLH2 tPHL2 90 % O1 10 % 90% O2 * * * O255
Data Sheet S14085EJ1V1DS00
6. SWITCHING CHARACTERISTIC WAVEFORM (R,/L= H)
10% tTLH
tTHL
O256 tPLH1 50 % tPHL1
STVL
PWOE OE 50 %
tPHL3 O1-O256 90 %
tPLH3
PD16700
10 %
PD16700
7. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the PD16700. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions.
PD16700N-xxx : TCP (TAB Package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C, heating for 2 to 3 seconds : pressure 100g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100C: pressure 3 to 8 kg/cm : time 3 to 5 sec. Real bonding 165 to 180C: pressure 25 to 45 kg/cm : time 30 to 40 sec. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd).
2 2
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.
Data Sheet S14085EJ1V1DS00
9
PD16700
[MEMO]
10
Data Sheet S14085EJ1V1DS00
PD16700
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14085EJ1V1DS00
11
PD16700
Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC's Semiconductor Devices(C11531E)
* The information in this document is current as of July, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

▲Up To Search▲

Price & Availability of UPD16700

	To Download UPD16700 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .